Semiconductor structure and high-frequency semiconductor device

Abstract

The invention provides a semiconductor structure and a high-frequency semiconductor device. The semiconductor structure comprises a substrate; the common collector layer, the base layer and the emitter layer are stacked on the substrate; wherein the base electrode layer comprises a first base electrode and a second base electrode, and the emitter electrode layer comprises a first emitter electrode located on the first base electrode and a second emitter electrode located on the second base electrode; the first base electrode and the second base electrode as well as the first emitting electrode and the second emitting electrode are symmetrically arranged along the same symmetry plane; a common metal structure disposed on the common collector layer, the base layer, and the emitter layer, respectively; wherein the common metal structure also forms a symmetrical layout along the symmetry plane. Through the reasonable metal structure layout design, the stray capacitance can be reduced and the high-frequency response capability can be improved on the basis of considering the performance of multiple aspects such as current transmission and heat dissipation.

Description

Technical Field

[0001] The embodiments in the present application relate to the technical field of power amplifiers, and particularly to a semiconductor structure and a high-frequency semiconductor device. Background Art

[0002] With the rapid development of wireless communication technology, the requirements for high-frequency performance, efficiency, and device miniaturization of radio frequency power amplifiers are constantly increasing. As a core component of radio frequency power amplifiers in high-frequency and high-power applications, the performance of HBT (Heterojunction Bipolar Transistor) is crucial to the overall performance of radio frequency power amplifiers.

[0003] In HBT devices, the design of the metal structure directly affects various performances such as current transmission, heat dissipation, and high-frequency response. In related technologies, the metal structure of HBT usually adopts a single-layer metal or a simple multi-layer metal stacking method, resulting in problems such as large parasitic capacitance and insufficient high-frequency response performance. Summary of the Invention

[0004] In view of this, multiple embodiments of the present application are dedicated to providing a semiconductor structure and a high-frequency semiconductor device, which can reduce parasitic capacitance and improve high-frequency response ability.

[0005] An embodiment of the present application provides a semiconductor structure, including: a substrate; a common collector layer, a base layer, and an emitter layer stacked on the substrate; wherein, the base layer includes a first base and a second base, and the emitter layer includes a first emitter located on the first base and a second emitter located on the second base; the first base and the second base, and the first emitter and the second emitter form a symmetric layout along the same symmetry plane; a common metal structure composed of metal layers respectively disposed on the common collector layer, the base layer, and the emitter layer; wherein, the common metal structure also forms a symmetric layout along the symmetry plane.

[0006] Optionally, the common collector layer, the first base, and the first emitter form a first heterojunction bipolar transistor, and form a second heterojunction bipolar transistor with the second base and the second emitter; the common metal structure includes: a first conductive metal layer disposed on the common collector layer, a second conductive metal layer commonly connected to the first base and the second base, and a heat dissipation metal layer commonly connected to the first emitter and the second emitter.

[0007] Optionally, the thicknesses of the first conductive metal layer and the second conductive metal layer are less than the thickness of the heat dissipation metal layer.

[0008] Optionally, the thicknesses of both the first conductive metal layer and the second conductive metal layer fall within the range of 500 nm to 1500 nm, and the thickness of the heat dissipation metal layer falls within the range of 2000 nm to 5000 nm.

[0009] Optionally, the electrical conductivity of the first conductive metal layer and the second conductive metal layer is higher than that of the heat dissipation metal layer, and the thermal conductivity of the first conductive metal layer and the second conductive metal layer is lower than that of the heat dissipation metal layer; and / or, the materials of the first conductive metal layer and the second conductive metal layer are gold or aluminum, and the material of the heat dissipation metal layer is copper or a copper alloy.

[0010] Optionally, a third conductive metal layer and a fourth conductive metal layer are further respectively disposed on the first emitter and the second emitter; the third conductive metal layer is located between the heat dissipation metal layer and the first emitter, and the fourth conductive metal layer is located between the heat dissipation metal layer and the second emitter; wherein, the thicknesses of the third conductive metal layer and the fourth conductive metal layer are less than the thickness of the heat dissipation metal layer.

[0011] Optionally, the common collector layer is connected to the first conductive metal layer through a first conductive via, and the first conductive via is symmetrically formed along the symmetry plane; the first base and the second base are respectively connected to the second conductive metal layer through second conductive vias symmetrically formed along the symmetry plane; the first emitter and the second emitter are respectively connected to the third conductive metal layer and the fourth conductive metal layer through third conductive vias symmetrically formed along the symmetry plane; the third conductive metal layer and the fourth conductive metal layer are respectively connected to the heat dissipation metal layer through fourth conductive vias symmetrically formed along the symmetry plane.

[0012] Optionally, the height of the first conductive metal layer relative to the substrate is less than the height of the second conductive metal layer relative to the substrate, and the height of the second conductive metal layer relative to the substrate is less than the height of the heat dissipation metal layer relative to the substrate.

[0013] Optionally, the first conductive via and the first conductive metal layer are located in a first opening region formed between the first base and the second base; the second conductive via and the second conductive metal layer are located in a second opening region formed between the first emitter and the second emitter; wherein, the width of the first opening region is less than the width of the second opening region, and the width of the second opening region is less than the width of the heat dissipation metal layer.

[0014] Another embodiment of the present application provides a high-frequency semiconductor device, including the semiconductor structure as described above.

[0015] In multiple embodiments provided by the present application, by providing a first heterojunction bipolar transistor and a second heterojunction bipolar transistor with a symmetric layout and a shared metal structure, not only can the shared metal structure be used as a shared metal layer between the electrodes of the first heterojunction bipolar transistor and the second heterojunction bipolar transistor to reduce the coupling area and parasitic capacitance, but also, since the shared metal structure and the first heterojunction bipolar transistor and the second heterojunction bipolar transistor all form a symmetric layout along the same symmetry plane, the difference in current or electric field intensity in a local area can be reduced, further reducing the capacitive coupling effect in the semiconductor structure, thereby improving the high-frequency response performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. is a schematic diagram of a semiconductor structure provided by an embodiment of the present application.

[0017] DESCRIPTION OF THE REFERENCE NUMERALS:

[0018] 100, semiconductor structure; 101, substrate; 102, shared collector layer; 103, base layer; 104, emitter layer; 1031, first base; 1032, second base; 1041, first emitter; 1042, second emitter; 105, shared metal structure; 1051, first conductive metal layer; 1052, second conductive metal layer; 1053, third conductive metal layer; 1054, fourth conductive metal layer; 1055, heat dissipation metal layer; 1061, first conductive via; 1062, second conductive via; 1063, third conductive via; 1064, fourth conductive via; 107, first opening region; 108, second opening region. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0020] In the present application, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0021] Unless otherwise specified, all technical and scientific terms used in the present application have the same meaning as commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the embodiments of the present application and the appended claims includes any and all combinations of one or more of the related listed items. The singular forms "a", "above-mentioned", and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0022] In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the embodiments of the present application, the meaning of "a plurality" is two or more, unless otherwise specifically and clearly defined.

[0023] In the description of the present application, the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of simplifying the description of the present application and does not indicate that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, that is, it cannot be construed as a limitation to the present application.

[0024] In the description of the present application, unless otherwise clearly defined, the terms "mounted", "connected", "coupled", "fixed", "arranged", etc. shall be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can also be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0025] In a heterojunction bipolar transistor (HBT) device, the role of the metal structure is mainly reflected in providing efficient electrical connection, optimized thermal management, and enhanced operating performance. Specifically, the metal structure is used to form effective contacts with the emitter, base, and collector, ensuring that current can be efficiently injected and withdrawn, while reducing the contact resistance and improving the frequency response characteristics. Therefore, through reasonable metal layout design, the performance of various aspects of the HBT device can be improved.

[0026] In related technologies, the metal structure in HBT devices mostly adopts a layout design of single-layer metal or simple multi-layer metal stacking. This metal structure layout easily generates additional capacitive coupling between different layers or between parts within the same layer of the HBT device, resulting in an increase in parasitic capacitance and affecting the high-frequency response performance of the HBT device. By adjusting the dielectric thickness between metal layers and selecting low-dielectric-constant materials, the parasitic capacitance can be reduced, but it will also degrade the performance of the HBT device in other aspects such as current transmission and heat dissipation.

[0027] Therefore, it is necessary to provide an HBT device that can reduce parasitic capacitance and improve high-frequency response ability on the basis of considering multiple performance aspects such as current transmission and heat dissipation through a reasonable metal structure layout design.

[0028] Please refer to Figure 1 An embodiment of the present application provides a semiconductor structure 100, and the semiconductor structure 100 may be an HBT device including multiple heterojunction bipolar transistors. The heterojunction bipolar transistor can construct a heterojunction by using materials with different bandgap widths between the base and the emitter or the collector, which not only effectively improves the current gain and frequency response characteristics, but also can reduce the base resistance and noise level, making the HBT device perform well in high-frequency and high-power applications. For example, in the radio frequency front-end module of a mobile communication device, the HBT device can be used in the design of a power amplifier. Thanks to its thermal stability and linearity, it can ensure the efficient amplification of signals at high frequencies and at the same time maintain low power consumption and heat generation.

[0029] In this embodiment, the semiconductor structure 100 may include a substrate 101, a common collector layer 102, a base layer 103, an emitter layer 104, and a common metal structure 105.

[0030] In this embodiment, the common collector layer 102, the base layer 103, and the emitter layer 104 may be sequentially stacked on the substrate 101. Specifically, the common collector layer 102 may cover the surface of the substrate 101, and at least part of its surface is covered by the base layer 103, and at least part of the surface of the base layer 103 may be covered by the emitter layer 104. Among them, the emitter layer 104 and the base layer 103 may respectively adopt semiconductor materials with different bandgap widths to form a heterojunction. For example, the emitter layer 104 may adopt a material with a wider bandgap (such as AlGaAs, InGaP), while the base layer 103 uses a material with a narrower bandgap (such as GaAs, InGaAs, GaAsSb, etc.) to improve the electron injection efficiency and reduce unnecessary carriers flowing from the base layer 103 to the emitter layer 104, thereby improving the current gain and frequency response. Of course, in some embodiments, a heterojunction may also be introduced between the base layer 103 and the common collector layer 102, that is, the base layer 103 and the common collector layer 102 respectively adopt semiconductor materials with different bandgap widths. For example, the common collector layer 102 may adopt a material with a slightly wider bandgap than the material of the base layer 103 (such as InGaP, AlGaAs).

[0031] In this embodiment, the base layer 103 may include the bases of multiple different heterojunction bipolar transistors. In a heterojunction bipolar transistor, the base can control the carrier transport process through its optimized energy band structure, reduce the recombination loss, and improve the injection efficiency. Specifically, asFigure 1 As shown, the base layer 103 may include a first base 1031 and a second base 1032. The first base 1031 and the second base 1032 may be the bases of two adjacent heterojunction bipolar transistors respectively, that is, the bases of the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

[0032] Similarly, the emitter layer 104 may also include the emitters of multiple different heterojunction bipolar transistors. In a heterojunction bipolar transistor, the emitter layer 104 may be used to inject carriers (electrons or holes) into the base layer 103. Specifically, as Figure 1 shown, the emitter layer 104 may include a first emitter 1041 located on the first base 1031 and a second emitter 1042 located on the second base 1032. The first emitter 1041 and the second emitter 1042 may be the emitters of the first heterojunction bipolar transistor and the second heterojunction bipolar transistor respectively.

[0033] In this embodiment, the common collector layer 102 may serve as the common collector of two adjacent heterojunction bipolar transistors. In a heterojunction bipolar transistor, the collector may be used to collect carriers and conduct them out to complete the amplification of current. Specifically, the common collector layer 102 may form a first heterojunction bipolar transistor with the first base 1031 and the first emitter 1041, and form a second heterojunction bipolar transistor with the second base 1032 and the second emitter 1042.

[0034] In this embodiment, the first base 1031 and the second base 1032 may cover a part of the surface of the common collector layer 102. Among them, a first opening region 107 that does not cover the common collector layer 102 is formed between the first base 1031 and the second base 1032. In this embodiment, the width of the first emitter 1041 located on the surface of the first base 1031 may be smaller than the width of the first base 1031, and the width of the second emitter 1042 located on the surface of the second base 1032 may be smaller than the width of the second base 1032. The first emitter 1041 and the second emitter 1042 respectively cover a part of the surface of the first base 1031 and the second base 1032. Among them, a second opening region 108 is formed between the first emitter 1041 and the second emitter 1042. The second opening region 108 may include the first opening region 107 and the regions formed by the uncovered surfaces of the first base 1031 and the second base 1032.

[0035] In this embodiment, the first heterojunction bipolar transistor and the second heterojunction bipolar transistor may be symmetrically arranged, that is, they are mirror-symmetric about a symmetry plane. Specifically, between the first base 1031 and the second base 1032, between the first emitter 1041 and the second emitter 1042, and the common collector layer 102 may all form a symmetric arrangement along the above-mentioned symmetry plane, that is, they are mirror-symmetric about the symmetry plane. In this embodiment, the symmetry plane may be located within the first opening region 107.

[0036] Optionally, the symmetry plane has a normal vector parallel to the arrangement direction of the first heterojunction bipolar transistor and the second heterojunction bipolar transistor. Optionally, the common collector layer 102 is located on the surface of the first opening region 107, and grooves may be formed on the side surfaces of the first base 1031 and the second base 1032 facing each other, and the symmetry plane may be coplanar with the center line of the groove in its extending direction. It can be understood that the groove, the first opening region 107, and the second opening region 108 are also mirror-symmetric about the symmetry plane.

[0037] In this embodiment, at least one metal layer shared by the first heterojunction bipolar transistor and the second heterojunction bipolar transistor is provided on the common collector layer 102, the base layer 103, and the emitter layer 104 respectively to form a common metal structure 105. The at least one metal layer may be electrically connected to the common collector layer 102, the base layer 103, and the emitter layer 104 respectively to construct a conductive path for connecting the external circuit for the first heterojunction bipolar transistor and the second heterojunction bipolar transistor. Specifically, the collectors of the first heterojunction bipolar transistor and the second heterojunction bipolar transistor may share at least one metal layer located on the common collector layer 102, the first base 1031 and the second base 1032 may share at least one metal layer located on the base layer 103, and the first emitter 1041 and the second emitter 1042 may share at least one metal layer located on the emitter layer 104.

[0038] In some embodiments, at least one metal layer disposed on the common collector layer 102, base layer 103, and emitter layer 104 may each include one or more metals. Among them, when the at least one metal layer is a multi-layer metal, a functional layer design can be adopted. By optimizing the thickness and material properties of each layer of metal, the requirements of current transmission and thermal effects can be balanced. Specifically, for example, the at least one metal layer may include three layers of metal, M1 - M3. Among them, the top layer metal (M3) can be selected from high thermal conductivity materials (such as copper or copper alloy), and the heat dissipation performance can be significantly improved by increasing the thickness. The bottom layer metal (M1) uses high conductivity materials (such as gold or aluminum), and the influence of parasitic capacitance on high-frequency characteristics can be effectively reduced by reducing the thickness, while maintaining low resistance characteristics. This functional layer multi-layer metal layout can not only improve the heat dissipation ability of the device, but also optimize the overall electrical performance.

[0039] In this embodiment, the common metal structure 105 formed by at least one metal layer disposed on the common collector layer 102, base layer 103, and emitter layer 104 may also form a symmetric layout along the symmetry plane. It can be understood that the first heterojunction bipolar transistor, the second heterojunction bipolar transistor, and the common metal structure 105 as a whole can be in a symmetric layout.

[0040] In this embodiment, by setting the common metal structure 105, at least one metal layer is shared between the collectors, bases, and emitters of the first heterojunction bipolar transistor and the second heterojunction bipolar transistor respectively, which can effectively reduce the coupling area between the electrodes of the semiconductor structure 100 and the metal layer, and reduce parasitic capacitance. Moreover, the common metal structure 105, the first heterojunction bipolar transistor, and the second heterojunction bipolar transistor all form a symmetric layout along the same symmetry plane, which can reduce the current or electric field intensity difference in the local area, effectively reduce the capacitive coupling effect in the semiconductor structure 100, and improve the response performance. Especially for high-frequency and high-power applications, since the capacitive coupling effect is particularly obvious in high-frequency signal transmission, the symmetric layout adopted above can effectively suppress crosstalk and delay between signals, thereby improving the overall high-frequency response performance and stability.

[0041] It should be noted that the first heterojunction bipolar transistor and the second heterojunction bipolar transistor are not specifically designated, but represent any two adjacent heterojunction bipolar transistors in the semiconductor structure 100. The present application does not specifically limit the number of heterojunction bipolar transistors included in the semiconductor structure 100.

[0042] Please continue to refer to Figure 1. In some embodiments, the common metal structure 105 may include: a first conductive metal layer 1051 disposed on the common collector layer 102, a second conductive metal layer 1052 to which the first base 1031 and the second base 1032 are commonly connected, and a heat dissipation metal layer 1055 to which the first emitter 1041 and the second emitter 1042 are commonly connected.

[0043] In some embodiments, the first conductive metal layer 1051 and the second conductive metal layer 1052 may respectively provide low-impedance conduction paths for the base layer 103 and the common collector layer 102. The heat dissipation metal layer 1055 may be used to dissipate heat for the semiconductor structure 100 under high-power operating conditions, thereby improving the reliability and service life of the semiconductor structure 100. The first conductive metal layer 1051, the second conductive metal layer 1052, and the heat dissipation metal layer 1055 have different functional positions. It can be understood that the conductivity of the first conductive metal layer 1051 and the second conductive metal layer 1052 is higher than that of the heat dissipation metal layer 1055, while the thermal conductivity of the heat dissipation metal layer 1055 is higher than that of the first conductive metal layer 1051 and the second conductive metal layer 1052.

[0044] Optionally, the materials of the first conductive metal layer 1051 and the second conductive metal layer 1052 may be materials with high conductivity, such as gold or aluminum. The material of the heat dissipation metal layer 1055 may be a material with high thermal conductivity, such as copper or a copper alloy.

[0045] In some embodiments, the thicknesses of the first conductive metal layer 1051 and the second conductive metal layer 1052 are less than the thickness of the heat dissipation metal layer 1055. By increasing the thickness of the heat dissipation metal layer 1055, its heat dissipation performance can be further improved. By reducing the thicknesses of the first conductive metal layer 1051 and the second conductive metal layer 1052, the resistance can be reduced, the conductivity can be improved, and the parasitic capacitance can be reduced.

[0046] Optionally, the thicknesses of the first conductive metal layer 1051 and the second conductive metal layer 1052 both fall within the range of 500 nm to 1500 nm; the thickness of the heat dissipation metal layer 1055 falls within the range of 2000 nm to 5000 nm.

[0047] In some embodiments, a third conductive metal layer 1053 and a fourth conductive metal layer 1054 are respectively disposed on the first emitter 1041 and the second emitter 1042; the third conductive metal layer 1053 is located between the heat dissipation metal layer 1055 and the first emitter 1041, and the fourth conductive metal layer 1054 is located between the heat dissipation metal layer 1055 and the second emitter 1042; wherein, the thicknesses of the third conductive metal layer 1053 and the fourth conductive metal layer 1054 are less than the thickness of the heat dissipation metal layer 1055.

[0048] In some embodiments, the functions, materials, and size selections of the third conductive metal layer 1053 and the fourth conductive metal layer 1054 may be the same as those of the second conductive metal layer 1052, that is, the third conductive metal layer 1053 and the fourth conductive metal layer 1054 belong to the same layer in the metal layer layout of the shared metal structure and are formed through the same process.

[0049] In some embodiments, by disposing the third conductive metal layer 1053 and the fourth conductive metal layer 1054 between the heat dissipation metal layer 1055 and the emitter layer 104, the conductive performance can be improved while ensuring the heat dissipation performance. Through functional layering, the balance between current transmission and heat effect requirements can be achieved, bringing an improvement in the overall performance.

[0050] In some embodiments, the shared collector layer 102 is connected to the first conductive metal layer 1051 through a first conductive via 1061, and the first conductive via 1061 is symmetric along the symmetry plane; the first base 1031 and the second base 1032 are respectively connected to the second conductive metal layer 1052 through second conductive vias 1062 that are symmetric along the symmetry plane; the first emitter 1041 and the second emitter 1042 are respectively connected to the third conductive metal layer 1053 and the fourth conductive metal layer 1054 through third conductive vias 1063 that are symmetric along the symmetry plane; the third conductive metal layer 1053 and the fourth conductive metal layer 1054 are respectively connected to the heat dissipation metal layer 1055 through fourth conductive vias 1064 that are symmetric along the symmetry plane.

[0051] In some embodiments, electrical connections are made between different metal layers and between the metal layers and the common collector layer 102, emitter layer 104, and base layer 103 by means of conductive vias. The conductive vias also exhibit a symmetric layout along the same symmetry plane, which can effectively balance and shorten the current transmission path, further reducing transmission loss and power dissipation. Specifically, the conductive vias are arranged in a symmetric layout, reducing the problem of local high current density existing in the common collector layer 102, the first base 1031 and the second base 1032, and the first emitter 1041 and the second emitter 1042, effectively alleviating the thermal loss and the increase in local resistance caused by the crowding effect. In addition, by making electrical connections through vertical conductive vias, the current path can be optimized, the transmission distance of the current can be shortened, the path loss can be reduced, and the current transmission efficiency of high-power density devices can be improved, thereby further enhancing the high-frequency performance. And by optimizing the via morphology and interface characteristics, efficient connection between different metal layers can be achieved, avoiding performance degradation caused by the electromigration effect.

[0052] In some embodiments, the resistance of the conductive vias can be further reasonably set by further adjusting the diameter, depth, and shape of the conductive vias to avoid overheating problems caused by local current concentration. At the same time, the optimized via layout reduces the overall connection impedance, preventing the degradation of the metal layer caused by the electromigration effect, enabling the semiconductor structure 100 to maintain stable performance in long-term high-power and high-frequency applications.

[0053] In addition, the layout of the conductive vias and the layout of the metal layers form a synergistic effect, which can improve the uniformity of the current distribution inside the common metal structure 105, reduce the generation of local hot spots, and thus further improve the thermal management performance of the semiconductor structure 100.

[0054] In some embodiments, a contact metal can be provided on the surface of the common collector layer 102 and connected to the first conductive via 1061. Similarly, contact metals can be provided on the surfaces of the first base 1031 and the second base 1032, and the first emitter 1041 and the second emitter 1042, and connected to the corresponding conductive vias.

[0055] In some embodiments, the height of the first conductive metal layer 1051 relative to the substrate 101 is less than the height of the second conductive metal layer 1052 relative to the substrate 101, and the height of the second conductive metal layer 1052 relative to the substrate 101 is less than the height of the heat dissipation metal layer 1055 relative to the substrate 101.

[0056] In some embodiments, since the heights of the common collector layer 102, the base layer 103, and the emitter layer 104 with respect to the substrate 101 increase in sequence from low to high, arranging the first conductive metal layer 1051 on the common collector layer 102, the second conductive metal layer 1052 on the base layer 103, and the heat dissipation metal layer 1055 on the emitter layer 104 in height according to this sequence is conducive to more effectively utilizing the layout space and reducing the overall thickness of the semiconductor structure 100.

[0057] In some embodiments, the first conductive via 1061 and the first conductive metal layer 1051 are located in a first opening region 107 formed between the first base 1031 and the second base 1032; the second conductive via 1062 and the second conductive metal layer 1052 are located in a second opening region 108 formed between the first emitter 1041 and the second emitter 1042; wherein, the width of the first opening region 107 is smaller than the width of the second opening region 108, and the width of the second opening region 108 is smaller than the width of the heat dissipation metal layer 1055.

[0058] In some embodiments, the projection range of the heat dissipation metal layer 1055 on the substrate 101 is larger than the projection range of the second conductive metal layer 1052 on the substrate 101, and the projection range of the second conductive metal layer 1052 on the substrate 101 is larger than the projection range of the first conductive metal layer 1051 on the substrate 101.

[0059] In some embodiments, using the spaces of the first opening region 107 and the second opening region 108 to arrange the metal layers improves the utilization rate of the layout space and is conducive to reducing the overall size of the semiconductor structure 100.

[0060] An embodiment of the present application further provides a high-frequency semiconductor device, and the high-frequency semiconductor device may include the semiconductor structure in any of the foregoing embodiments.

[0061] In this embodiment, the high-frequency semiconductor device is generally used in radio frequency (RF) and microwave applications, such as in the fields of communication, radar, amplifiers, etc. The high-frequency semiconductor device may include a bipolar transistor based on heterojunction technology, which is mainly used for high-performance, high-frequency, and high-speed signal amplification.

[0062] It can be understood that the specific examples herein are only for helping those skilled in the art better understand the embodiments of the present application, rather than limiting the scope of the present invention.

[0063] It can be understood that in various embodiments of the present application, the magnitude of the sequence numbers of the various processes does not imply the order of execution, and the order of execution of the various processes should be determined by their functions and internal logics, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0064] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0065] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meaning as commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the related listed items. The singular forms "a", "above-mentioned", and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0066] As described above, the above are only specific embodiments of the present application, but the protection scope of the present invention is not limited thereto. Any person skilled in the technical field who can easily think of changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Including: A substrate; A common collector layer, a base layer, and an emitter layer stacked on the substrate; wherein, the base layer includes a first base and a second base, and the emitter layer includes a first emitter on the first base and a second emitter on the second base; the first base and the second base, and the first emitter and the second emitter form a symmetric layout along the same symmetry plane; A common metal structure composed of metal layers respectively disposed on the common collector layer, the base layer, and the emitter layer; wherein, the common metal structure also forms a symmetric layout along the symmetry plane.

2. The semiconductor structure according to claim 1, wherein The common collector layer, the first base, and the first emitter form a first heterojunction bipolar transistor, and form a second heterojunction bipolar transistor with the second base and the second emitter; The common metal structure includes: a first conductive metal layer disposed on the common collector layer, a second conductive metal layer commonly connecting the first base and the second base, and a heat dissipation metal layer commonly connecting the first emitter and the second emitter.

3. The semiconductor structure according to claim 2, wherein The thickness of the first conductive metal layer and the second conductive metal layer is less than the thickness of the heat dissipation metal layer.

4. The semiconductor structure according to claim 3, characterized in that, The thicknesses of the first conductive metal layer and the second conductive metal layer both fall within the range of 500 nm to 1500 nm, and the thickness of the heat dissipation metal layer falls within the range of 2000 nm to 5000 nm.

5. The semiconductor structure according to claim 2, wherein The electrical conductivity of the first conductive metal layer and the second conductive metal layer is higher than that of the heat dissipation metal layer, and the thermal conductivity of the first conductive metal layer and the second conductive metal layer is lower than that of the heat dissipation metal layer; and / or, the materials of the first conductive metal layer and the second conductive metal layer are gold or aluminum, and the material of the heat dissipation metal layer is copper or a copper alloy.

6. The semiconductor structure according to claim 2, wherein Third conductive metal layers and fourth conductive metal layers are respectively disposed on the first emitter and the second emitter; the third conductive metal layer is located between the heat dissipation metal layer and the first emitter, and the fourth conductive metal layer is located between the heat dissipation metal layer and the second emitter; wherein, the thicknesses of the third conductive metal layer and the fourth conductive metal layer are less than the thickness of the heat dissipation metal layer.

7. The semiconductor structure according to claim 6, wherein, The common collector layer and the first conductive metal layer are connected through a first conductive via hole, and the first conductive via hole forms a symmetry along the symmetry plane; the first base and the second base are respectively connected to the second conductive metal layer through second conductive via holes that form a symmetry along the symmetry plane; the first emitter and the second emitter are respectively connected to the third conductive metal layer and the fourth conductive metal layer through third conductive via holes that form a symmetry along the symmetry plane; the third conductive metal layer and the fourth conductive metal layer are respectively connected to the heat dissipation metal layer through fourth conductive via holes that form a symmetry along the symmetry plane.

8. The semiconductor structure according to claim 7, wherein, The height of the first conductive metal layer relative to the substrate is less than the height of the second conductive metal layer relative to the substrate, and the height of the second conductive metal layer relative to the substrate is less than the height of the heat dissipation metal layer relative to the substrate.

9. The semiconductor structure according to claim 8, wherein The first conductive via and the first conductive metal layer are located in a first opening region formed between the first base and the second base; the second conductive via and the second conductive metal layer are located in a second opening region formed between the first emitter and the second emitter; wherein, the width of the first opening region is smaller than the width of the second opening region, and the width of the second opening region is smaller than the width of the heat dissipation metal layer.

10. A high-frequency semiconductor device, characterized in that, Comprising the semiconductor structure according to any one of claims 1 to 9.

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