Preparation method of passivation contact battery with double tunneling polycrystalline silicon layers and battery

Abstract

The invention discloses a preparation method of a passivation contact cell with double tunneling polycrystalline silicon layers. A first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doping p-type amorphous silicon layer, a second tunneling oxide layer, a high-doping p-type amorphous silicon layer and a first silicon dioxide mask layer are sequentially deposited in a p region on the back surface of a silicon wafer; sequentially depositing a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doping n-type amorphous silicon layer, a fourth tunneling oxide layer, a high-doping n-type amorphous silicon layer and a second silicon dioxide mask layer in an n region on the back surface of the silicon wafer; and the p-type amorphous silicon and the n-type amorphous silicon are simultaneously converted into p-type polycrystalline silicon and n-type polycrystalline silicon through high-temperature annealing crystallization treatment, so that the preparation of the p-region and n-region dual-tunneling passivation contact structure of the TBC battery is realized. The doping level and passivation performance of the p-region p-type polycrystalline silicon and the n-region n-type polycrystalline silicon are improved, the conversion efficiency of the TBC battery is improved, the production steps are reduced, and the preparation cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of photovoltaic manufacturing, and particularly relates to a method for preparing a passivated contact battery with a double tunneling polysilicon layer. Background Art

[0002] With the continuous increase in the global demand for clean energy, the research and development of high-efficiency solar cells has become the core focus in the photovoltaic field. The tunnel oxide passivating full BackContact solar cell (TBC) battery, as a new type of solar cell structure, exhibits great performance potential due to its unique tunneling effect and back contact design. The TBC battery can effectively reduce carrier recombination, improve the open-circuit voltage and short-circuit current of the battery, and thus significantly enhance the photoelectric conversion efficiency. In practical application scenarios, the TBC battery is widely used in large-scale photovoltaic power stations to supply efficient and stable power to the power grid; in distributed photovoltaic power generation systems, such as industrial and commercial rooftops, residential rooftops, etc., the TBC battery is also favored for its high efficiency and aesthetics, and can maximize the power generation benefit in a limited space.

[0003] In the current TBC battery preparation process, the preparation of the p-region and the n-region follows a specific process. Regarding the preparation of the p-region, first, an intrinsic polysilicon layer is deposited using low-pressure chemical vapor deposition (LPCVD) technology. The LPCVD technology can chemically react with gaseous reactants on the substrate surface under relatively low pressure to uniformly deposit a high-quality intrinsic polysilicon. After the deposition of the intrinsic polysilicon layer, boron diffusion is carried out on it. By diffusing boron atoms into the intrinsic polysilicon layer, its electrical properties are changed to achieve the preparation of p-type polysilicon. Similarly, when preparing the n-region, an intrinsic polysilicon layer is first deposited using the LPCVD method, and then phosphorus diffusion is carried out on this intrinsic polysilicon layer to achieve the preparation of n-type polysilicon. This set of preparation processes can, to a certain extent, build the basic framework of the TBC battery.

[0004] Under the existing preparation methods, both p-type polysilicon and n-type polysilicon have low doping concentrations. The low doping concentration limits the carrier transport efficiency and is difficult to fully utilize the electrical performance advantages of polysilicon. More critically, this method is difficult to achieve precise layered doping. In the actual TBC battery structure, different layers have different requirements for doping concentration, and the existing process cannot precisely control the doping concentration of each layer, resulting in an unreasonable internal electric field distribution in the battery and affecting the separation and collection efficiency of carriers.

[0005] The poor passivation performance of the p-region and n-region is another significant drawback of the existing preparation methods. The main function of the passivation layer is to reduce the recombination of carriers at the interface and improve the open-circuit voltage of the battery. However, the passivation layers of the p-region and n-region prepared by the current process cannot effectively suppress carrier recombination, resulting in a large amount of photo-generated carriers being lost at the interface, reducing the overall performance of the battery, and thus leading to a low photoelectric conversion efficiency.

[0006] From the equipment level, when the LPCVD equipment is running, polysilicon will be deposited on the quartz tube wall, and there is a large thermal stress difference between polysilicon and quartz. During the heating and cooling processes of the equipment, this thermal stress difference will cause the quartz tube to rupture, and then it needs to be replaced frequently. Moreover, during the boron diffusion process, due to the diffusion temperature being as high as 1040 °C, such a high temperature causes great thermal shock to the quartz tube, accelerating the rupture of the quartz tube and also requiring frequent replacement. Frequent replacement of the quartz tube not only increases the equipment maintenance cost but also seriously affects the production utilization rate and product yield, comprehensively resulting in high production costs. Summary of the Invention

[0007] The purpose of the present invention is to provide a preparation method for a passivated contact battery with a double tunneling polysilicon layer, so as to solve the technical problems of the p-type polysilicon doping level and passivation performance in the p-region and the n-type polysilicon doping level and passivation performance in the n-region, improve the conversion efficiency of the TBC battery, reduce the production steps, and lower the preparation cost.

[0008] To achieve the above purpose, the specific technical solution of a preparation method for a passivated contact battery with a double tunneling polysilicon layer of the present invention is as follows:

[0009] A preparation method for a passivated contact battery with a double tunneling polysilicon layer includes the following steps:

[0010] S1. Silicon wafer surface treatment: The silicon wafer is successively subjected to alkali washing, polishing, acid washing, water washing, and drying;

[0011] S2. Deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a first silicon dioxide mask layer on the back surface of the silicon wafer in sequence;

[0012] S3. Remove the first silicon dioxide mask layer in the n-region on the back surface of the silicon wafer by laser etching;

[0013] S4. Remove the first silicon dioxide mask layer deposited around the front surface of the silicon wafer by acid etching;

[0014] S5. Polish the n-region on the back surface of the silicon wafer by alkali etching to remove the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the low-doped p-type amorphous silicon layer, the second tunneling oxide layer, and the high-doped p-type amorphous silicon layer in the n-region on the back surface of the silicon wafer and around the front surface of the silicon wafer;

[0015] S6. Deposit a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doped n-type amorphous silicon layer, a fourth tunneling oxide layer, a highly doped n-type amorphous silicon layer, and a second silicon dioxide mask layer on the back side of the silicon wafer in sequence;

[0016] S7. Anneal and crystallize the silicon wafer, converting the low-doped p-type amorphous silicon layer into a low-doped p-type polycrystalline silicon layer, the highly doped p-type amorphous silicon layer into a highly doped p-type polycrystalline silicon layer, the low-doped n-type amorphous silicon layer into a low-doped n-type polycrystalline silicon layer, and the highly doped p-type amorphous silicon layer into a highly doped p-type polycrystalline silicon layer;

[0017] S8. Remove the second silicon dioxide mask layer on the p-region on the back side of the silicon wafer and the spacer region between the p-region and the n-region by laser etching;

[0018] S9. Remove the second silicon dioxide mask layer deposited around the front side of the silicon wafer by acid etching;

[0019] S10. Remove the third tunneling oxide layer, the second intrinsic amorphous silicon layer, the low-doped n-type amorphous silicon layer, the fourth tunneling oxide layer, and the highly doped n-type amorphous silicon layer on the front side of the silicon wafer, the p-region on the back side of the silicon wafer, and the spacer region between the p-region and the n-region on the back side of the silicon wafer, form a textured surface on the surfaces of the front side of the silicon wafer and the spacer region between the p-region and the n-region on the back side of the silicon wafer, then sequentially perform acid washing to remove the first silicon dioxide mask layer in the p-region on the back side of the silicon wafer and the second silicon dioxide mask layer in the n-region, water washing, and hot drying;

[0020] S11. Deposit an aluminum oxide layer on both sides of the silicon wafer;

[0021] S12. Deposit an antireflection film on both sides of the silicon wafer;

[0022] S13. Complete the production of the front and back electrodes of the silicon wafer by screen printing and sintering;

[0023] S14. The silicon wafer undergoes light injection treatment to activate the H atoms from the passivation layer, obtaining a passivated contact cell with a double tunneling polycrystalline silicon layer.

[0024] As a further improvement of the present invention, in S1, the weight reduction of the silicon wafer is controlled at 0.3 - 0.5 g / wafer, and the reflectivity is controlled at 43% - 47%, including the following steps:

[0025] S1.1. Alkaline washing: Place the silicon wafer in a mixed solution of NaOH and H2O2 for cleaning the surface oil stain. The volume fraction of NaOH in the mixed solution is 0.5% - 1.5%, the volume fraction of H2O2 is 4% - 10%, the temperature is 60 - 70 °C, and the cleaning time is 100 - 250 s;

[0026] S1.2, Polishing: The silicon wafer is polished in an NaOH solution. The volume fraction of NaOH in the NaOH solution is 8% - 12%, the temperature is 78 - 85°C, and the polishing time is 120 - 180 s;

[0027] S1.3, Pickling: Neutralize the NaOH solution, and clean metal ions and the oxide layer in a mixed acid solution;

[0028] S1.4, Water washing and heat drying treatment.

[0029] As a further improvement of the present invention, in S2, a coating device is used to deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a first silicon dioxide mask layer on the back of the silicon wafer in sequence at a temperature of 350 - 430°C using SiH4, N2O, B2H6, and H2 gases;

[0030] In S6, a coating device is used to deposit a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doped n-type amorphous silicon layer, a fourth tunneling oxide layer, a high-doped n-type amorphous silicon layer, and a second silicon dioxide mask layer on the back of the silicon wafer in sequence at a temperature of 400 - 460°C using SiH4, N2O, PH3, and H2 gases.

[0031] As a further improvement of the present invention, in S3, a green picosecond laser is used to etch and remove the first silicon dioxide mask layer in the n-region on the back of the silicon wafer according to a designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W;

[0032] In S8, a green picosecond laser is used to etch and remove the second silicon dioxide mask layer in the p-region and the interval region between the p-region and the n-region on the back of the silicon wafer according to a designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W.

[0033] As a further improvement of the present invention, in S4, a chain cleaning device is used to clean the first silicon dioxide mask layer plated around the front of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out;

[0034] In S9, a chain cleaning device is used to clean the second silicon dioxide mask layer plated around the front of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out.

[0035] As a further improvement of the present invention, the polishing in S5 includes the following steps:

[0036] S5.1. Place the silicon wafer in a polishing solution in a trough-type cleaning equipment for cleaning and etching. The volume fraction of the alkaline solution in the polishing solution is 3-6%, the volume fraction of the additive is 0.6-1.0%, the temperature is 70-80 °C, and the polishing time is 300-500 s;

[0037] S5.2. Neutralize the alkaline solution and clean metal ions in an acidic solution;

[0038] S5.3. Perform water washing and heat drying treatments.

[0039] As a further improvement of the present invention, in S7, the silicon wafer is placed in a tube annealing furnace for high-temperature annealing and crystallization treatment. The annealing and crystallization temperature is 900-960 °C, the nitrogen flow rate is 5000-7000 sccm, the pressure is 700-900 mbar, the crystallization annealing time is 3000-4200 s, and the sheet resistance of the back n-region after annealing and crystallization is controlled at 30-60 Ω / □.

[0040] As a further improvement of the present invention, in S10, the weight reduction of the silicon wafer is controlled at 0.2-0.4 g / wafer, and the surface texture reflectance is controlled at 9%-11%. It includes the following steps:

[0041] S10.1. Place the silicon wafer in a texturing solution in a trough-type cleaning equipment. The volume fraction of the alkaline solution in the texturing solution is 0.9-1.3%, the volume fraction of the additive is 0.4-0.8%, the temperature is 80-85 °C, and the texturing time is 400-500 s;

[0042] S10.2. Remove the first silicon dioxide mask layer in the p-region on the back of the silicon wafer and the second silicon dioxide mask layer in the n-region in an acid pickling solution. The volume fraction of the acid in the acid pickling solution is 15-25%, the temperature is 20-30 °C, and the acid pickling time is 100-150 s;

[0043] S10.3. Perform water washing and heat drying treatments.

[0044] As a further improvement of the present invention, the front film layer of the silicon wafer in S12 is a multi-layer SiN x / SiO x N y / SiO2 structure, and the back film layer of the silicon wafer is a multi-layer SiN x structure.

[0045] As a further improvement of the present invention, in S11, a tube-type ALD atomic layer deposition equipment is used to deposit aluminum oxide on the front and back of the silicon wafer. The deposition temperature is 250-350 °C, the TMA flow rate is 15-25 sccm, the pure water flow rate is 15-25 sccm, the number of cycles is 30-50 times, and the thickness of the aluminum oxide is controlled at 4-6 nm;

[0046] In S13, the front and back electrodes are fabricated by screen printing process according to the designed printing pattern. Silver-aluminum paste is used for printing in the p region, and pure silver paste is used for printing in the n region. After printing, an infrared industrial belt sintering furnace is used for rapid sintering at a peak temperature of 730 - 800 °C to form metal contact electrodes.

[0047] In S14, an industrial belt optical injection furnace is used for optical injection treatment at a temperature of 600 - 680 °C to activate H atoms from the passivation layer.

[0048] As a further improvement of the present invention, in S2, a PECVD tube coating device is used to sequentially deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a first silicon dioxide mask layer on the back of the silicon wafer at a temperature of 350 - 430 °C, including the following deposition parameters:

[0049] First tunneling oxide layer: The N2O flow rate is 10000 - 12000 sccm, the RF power is 13000 - 16000 W, the duty cycle is 1:(80 - 120), the deposition time is 80 - 150 s, and the film thickness is controlled to be 1 - 2 nm;

[0050] First intrinsic amorphous silicon layer: The SiH4 flow rate is 2500 - 3500 sccm, the H2 flow rate is 9000 - 15000 sccm; the RF power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 150 - 300 s, and the film thickness is controlled to be 15 - 30 nm;

[0051] Low-doped p-type amorphous silicon layer: The SiH4 flow rate is 2500 - 3500 sccm, the H2 flow rate is 9000 - 15000 sccm, the ratio of B2H6 flow rate to SiH4 flow rate is 1:(3 - 5), the RF power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 200 - 400 s, and the film thickness is controlled to be 20 - 40 nm;

[0052] Second tunneling oxide layer: The N2O flow rate is 10000 - 12000 sccm, the RF power is 13000 - 16000 W, the duty cycle is 1:(80 - 120), the deposition time is 80 - 150 s, and the film thickness is controlled to be 1 - 2 nm;

[0053] High-doped p-type amorphous silicon: The SiH4 flow rate is 2500 - 3500 sccm, the H2 flow rate is 9000 - 15000 sccm, the ratio of B2H6 flow rate to SiH4 flow rate is 1:(1 - 2), the RF power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 900 - 1300 s, and the film thickness is controlled to be 100 - 140 nm;

[0054] The first silicon dioxide mask layer: the flow rate of SiH4 is 1800 - 2200 sccm, the flow rate of N2O is 7500 - 10000 sccm, the RF power is 11000 - 15000 W, the duty cycle is 1:(15 - 25), the deposition time is 60 - 120 s, and the film thickness is controlled to be 5 - 10 nm.

[0055] As a further improvement of the present invention, in S6, a PECVD tube coating device is used to sequentially deposit a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doped n-type amorphous silicon layer, a fourth tunneling oxide layer, a high-doped n-type amorphous silicon layer, and a second silicon dioxide mask layer on the back of the silicon wafer at a temperature of 400 - 460 °C, including the following deposition parameters:

[0056] The third tunneling oxide layer: the flow rate of N2O is 9000 - 11000 sccm, the RF power is 13000 - 17000 W, the duty cycle is 1:(60 - 120), the deposition time is 80 - 130 s, and the film thickness is controlled to be 1.5 - 2.5 nm;

[0057] The second intrinsic amorphous silicon layer: the flow rate of SiH4 is 2300 - 3300 sccm, the flow rate of H2 is 11000 - 13000 sccm; the RF power is 11000 - 13000 W, the duty cycle is 1:(10 - 20), the deposition time is 150 - 250 s, and the film thickness is controlled to be 20 - 30 nm;

[0058] The low-doped n-type amorphous silicon layer: the flow rate of SiH4 is 2300 - 3300 sccm, the flow rate of H2 is 11000 - 13000 sccm, the ratio of the flow rate of PH3 to the flow rate of SiH4 is 1:(7 - 13), the RF power is 11000 - 13000 W, the duty cycle is 1:(10 - 20), the deposition time is 200 - 300 s, and the film thickness is controlled to be 20 - 40 nm;

[0059] The fourth tunneling oxide layer: the flow rate of N2O is 9000 - 11000 sccm, the RF power is 13000 - 17000 W, the duty cycle is 1:(20 - 120), the deposition time is 80 - 130 s, and the film thickness is controlled to be 1.5 - 2.5 nm;

[0060] The high-doped n-type amorphous silicon layer: the flow rate of SiH4 is 2300 - 3300 sccm, the flow rate of H2 is 11000 - 13000 sccm, the ratio of the flow rate of PH3 to the flow rate of SiH4 is 1:(3 - 7), the RF power is 11000 - 13000 W, the duty cycle is 1:(10 - 20), the deposition time is 500 - 700 s, and the film thickness is controlled to be 60 - 80 nm;

[0061] Second silicon dioxide mask layer: The flow rate of SiH4 is 1500 - 1800 sccm, the flow rate of N2O is 6000 - 8000 sccm, the radio frequency power is 11000 - 13000 W, the duty cycle is 1:(15 - 25), the deposition time is 60 - 90 s, and the film thickness is controlled to be 5 - 10 nm.

[0062] As a further improvement of the present invention, the anti-reflection film on the front side of the silicon wafer in S12 is a multi-layer SiN x / SiO x N y / SiO2 structure, which successively includes the following structures and deposition parameters:

[0063] The first layer of SiN x The deposition temperature is 450 - 500 °C, the flow rate of silane is 2300 - 2600 sccm, the flow rate of ammonia is 7000 - 9000 sccm, the power is 10000 - 13000 W, the deposition time is 100 - 130 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 2.2 - 2.3%;

[0064] The second layer of SiN x The deposition temperature is 450 - 500 °C, the flow rate of silane is 1700 - 1900 sccm, the flow rate of ammonia is 11000 - 13000 sccm, the power is 12000 - 15000 W, the deposition time is 180 - 220 s, the film thickness is controlled to be 15 - 20 nm, and the refractive index is controlled to be 2.1 - 2.2%;

[0065] The third layer of SiN x The deposition temperature is 450 - 500 °C, the flow rate of silane is 1100 - 1500 sccm, the flow rate of ammonia is 11000 - 15000 sccm, the power is 13000 - 15000 W, the deposition time is 200 - 250 s, the film thickness is controlled to be 17 - 24 nm, and the refractive index is controlled to be 2 - 2.1%;

[0066] The first layer of SiO x N y The deposition temperature is 450 - 500 °C, the flow rate of silane is 900 - 1100 sccm, the flow rate of ammonia is 4000 - 6000 sccm, the flow rate of nitrous oxide is 5000 - 7000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.8 - 2%;

[0067] The second layer of SiO x N yThe deposition temperature is 450 - 500 °C, the silane flow rate is 700 - 900 sccm, the ammonia flow rate is 3500 - 4500 sccm, the nitrous oxide flow rate is 7000 - 9000 sccm, the power is 14000 - 16000 W, the deposition time is 140 - 160 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.6 - 1.8%;

[0068] For SiO2 deposition, the temperature is 450 - 500 °C, the silane flow rate is 700 - 900 sccm, the nitrous oxide flow rate is 9000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 80 - 120 s, the film thickness is controlled to be 5 - 10 nm, and the refractive index is controlled to be 1.4 - 1.6%;

[0069] The anti - reflection film on the back of the silicon wafer is a multi - layer SiN x structure, which successively includes the following structures and deposition parameters:

[0070] The first layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 2500 - 2900 sccm, the ammonia flow rate is 8000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled to be 15 - 25 nm, and the refractive index is controlled to be 2.2 - 2.3%;

[0071] The second layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1700 - 2100 sccm, the ammonia flow rate is 13000 - 15000 sccm, the power is 14500 - 16500 W, the deposition time is 170 - 210 s, the film thickness is controlled to be 20 - 30 nm, and the refractive index is controlled to be 2.1 - 2.2%;

[0072] The third layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1300 - 1500 sccm, the ammonia flow rate is 12000 - 15000 sccm, the power is 15000 - 19000 W, the deposition time is 250 - 300 s, the film thickness is controlled to be 30 - 40 nm, and the refractive index is controlled to be 2 - 2.1%.

[0073] A passivated contact cell with a double - tunneling polysilicon layer is prepared by the above - mentioned preparation method.

[0074] Beneficial effects:

[0075] By first depositing an intrinsic amorphous silicon layer and then depositing low-doped and highly doped p-type and n-type amorphous silicon layers respectively, and annealing and crystallizing them into polycrystalline silicon layers, the doping concentrations in different regions and different layers can be precisely controlled. Compared with traditional methods, the problems of low doping concentration and inability to precisely dope in layers are solved. For example, by setting low-doped and highly doped layers in the p-region and n-region respectively, the internal electric field distribution can be optimized according to the carrier transport requirements, improving the carrier separation and collection efficiency, which lays a foundation for improving the photovoltaic conversion efficiency of the battery. Two tunneling oxide layers are set in the p-region and n-region respectively, namely the first and second tunneling oxide layers and the third and fourth tunneling oxide layers, which cooperate with the corresponding intrinsic amorphous silicon layer and doped amorphous silicon layer. A tunneling oxide layer with an appropriate thickness (such as the thickness of the first tunneling oxide layer is controlled to be 1-2 nm) can effectively utilize the tunneling effect, reduce the probability of carrier recombination, further improve the carrier transport efficiency, thereby increasing the open-circuit voltage and short-circuit current of the battery and enhancing the overall performance.

[0076] Aluminum oxide layers are deposited on both sides of the silicon wafer. Aluminum oxide has good passivation performance, which can effectively reduce the dangling bonds on the silicon wafer surface and lower the carrier recombination rate. Combined with the double tunneling structure, the carrier recombination at the interface is further suppressed, significantly improving the passivation performance of the p-region and n-region. Compared with the existing preparation methods, the loss of photo-generated carriers at the interface is greatly reduced, increasing the open-circuit voltage of the battery, thereby enhancing the photovoltaic conversion efficiency. A multilayer SiNx / SiOxNy / SiO2 structure is used on the front side of the silicon wafer, and a multilayer SiNx structure is used as an antireflection film on the back side. This multilayer film structure can effectively reduce light reflection, increase light absorption, and improve light utilization. For example, by precisely controlling the deposition parameters of each layer of film on the front side (such as the deposition temperature of the first layer of SiNx is 450-500 °C, the film thickness is controlled to be 10-15 nm, and the refractive index is controlled to be 2.2-2.3%, etc.), high-efficiency antireflection of light with different wavelengths is achieved, further increasing the short-circuit current of the battery, which has a positive effect on improving the photovoltaic conversion efficiency.

[0077] Different from the traditional LPCVD equipment where the quartz tube frequently breaks due to thermal stress, this process uses a PECVD tube coating equipment. By setting reasonable process parameters, it avoids equipment damage caused by large thermal stress differences between the deposited substances and the equipment components. For example, when depositing each layer of film, parameters such as gas flow rate, RF power, duty cycle, and deposition time are precisely controlled, reducing stress concentration inside the equipment, lowering equipment maintenance costs, and increasing production operation rate. The entire preparation process is designed with reasonable steps. For example, in different stages, laser etching, acid etching, alkali etching, etc. are used to accurately remove unnecessary film layers, avoiding complex and error-prone operations in the traditional process. For example, when removing the silicon dioxide mask layer around the front of the silicon wafer and the film layer in specific areas on the back, appropriate etching methods and parameters are used, reducing damage to other film layers and the silicon wafer itself, improving product yield, simplifying the production process, and reducing comprehensive production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Figure 1 It is a schematic structural diagram of a passivated contact battery with a double-tunneling polysilicon layer of the present invention;

[0079] Description of the marks in the figure: 1. First tunneling oxide layer; 2. First intrinsic amorphous silicon layer; 3. Low-doped p-type polysilicon layer; 4. Second tunneling oxide layer; 5. High-doped p-type polysilicon layer; 6. Aluminum oxide layer; 71. Back antireflection film; 72. Front antireflection film; 8. Third tunneling oxide layer; 9. Second intrinsic amorphous silicon layer; 10. Low-doped n-type polysilicon layer; 11. Fourth tunneling oxide layer; 12. High-doped n-type polysilicon layer; 13. Positive electrode; 14. Negative electrode; 15. Silicon wafer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0080] In order to better understand the purpose, structure, and function of the present invention, the following further describes in detail the preparation method of a passivated contact battery with a double-tunneling polysilicon layer of the present invention in conjunction with the drawings.

[0081] Example 1:

[0082] As Figure 1A passivated contact cell with a double-tunneling polysilicon layer is shown. On the back p-region of the silicon wafer 15, a first tunneling oxide layer 1, a first intrinsic amorphous silicon layer 2, a low-doped p-type polysilicon layer 3, a second tunneling oxide layer 4, and a highly doped p-type polysilicon layer 5 are sequentially arranged; on the back n-region of the silicon wafer, a third tunneling oxide layer 8, a second intrinsic amorphous silicon layer 9, a low-doped n-type polysilicon layer 10, a fourth tunneling oxide layer 11, and a highly doped n-type polysilicon layer 12 are sequentially arranged; at the same time, an alumina layer 6 is arranged on both sides, and an antireflection film 71 on the back and an antireflection film 72 on the front are provided, realizing a double-tunneling passivated contact structure for the p-region and n-region of the TBC cell, improving the doping level and passivation performance of the p-type polysilicon in the p-region, similarly improving the doping level and passivation performance of the n-type polysilicon in the n-region, enhancing the conversion efficiency of the TBC cell, and reducing the production steps and the preparation cost. The preparation method of this cell is as follows:

[0083] Step 1: Surface treatment of the silicon wafer, cleaning and polishing both sides of the silicon wafer. Place the n-type silicon wafer in a mixed solution of NaOH and H2O2 for cleaning the surface oil stain. The cleaning solution has a volume fraction of NaOH of 1.0%, a volume fraction of H2O2 of 7.5%, a temperature of 66°C, and a cleaning time of 150 s; perform polishing treatment on the silicon wafer in the NaOH solution, with a volume fraction of NaOH of 10.3%, a temperature of 80°C, and a polishing time of 150 s; perform neutralization of the NaOH solution, cleaning of metal ions and oxide layers in a mixed acid solution of HCl and HF; complete water washing and hot drying treatments; control the weight loss of the silicon wafer at 0.4 g / wafer and the reflectivity at 45%.

[0084] Step 2: Using a PECVD tube coating equipment, at a temperature of 380 °C, with SiH4, N2O, B2H6, and H2 gases, deposit the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the low-doped p-type amorphous silicon layer, the second tunneling oxide layer, the high-doped p-type amorphous silicon layer, and the first silicon dioxide mask layer on the back side of the silicon wafer in sequence. The N2O flow rate of the first tunneling oxide layer is 11000 sccm, the RF power is 14000 W, the duty cycle is 1:100, the deposition time is 125 s, and the film thickness is controlled to be 1.6 nm; the SiH4 flow rate of the first intrinsic amorphous silicon layer is 3000 sccm, and the H2 flow rate is 11000 sccm; the RF power is 13000 W, the duty cycle is 1:15, the deposition time is 200 s, and the film thickness is controlled to be 20 nm; the SiH4 flow rate of the low-doped p-type amorphous silicon layer is 3000 sccm, the H2 flow rate is 11000 sccm, the ratio of the B2H6 flow rate to the SiH4 flow rate is 1:4, the RF power is 13000 W, the duty cycle is 1:15, the deposition time is 310 s, and the film thickness is controlled to be 30 nm; the N2O flow rate of the second tunneling oxide layer is 11000 sccm, the RF power is 14000 W, the duty cycle is 1:100, the deposition time is 125 s, and the film thickness is controlled to be 1.6 nm; the SiH4 flow rate of the high-doped p-type amorphous silicon layer is 3000 sccm, the H2 flow rate is 12000 sccm, the ratio of the B2H6 flow rate to the SiH4 flow rate is 1:1.5, the RF power is 14000 W, the duty cycle is 1:15, the deposition time is 1100 s, and the film thickness is controlled to be 120 nm; the SiH4 flow rate of the first silicon dioxide mask layer is 2000 sccm, the N2O flow rate is 9000 sccm, the RF power is 13000 W, the duty cycle is 1:20, the deposition time is 90 s, and the film thickness is controlled to be 8 nm.

[0085] Step 3: Use a green picosecond laser to etch and remove the first silicon dioxide mask layer in the n-region of the battery according to the designed pattern. The laser spot width is 150 um, and the laser power is 120 W.

[0086] Step 4: Use a chain cleaning equipment to clean off the first silicon dioxide mask layer that is coated around the front side of the silicon wafer in an HF solution. The volume fraction of HF is 35%, and then dry it.

[0087] Step 5: Place the silicon wafer in a polishing solution using a trough-type cleaning equipment for cleaning and etching. The volume fraction of the alkaline solution in the polishing solution is 4.5%, the volume fraction of the additive is 0.8%, the temperature is 75°C, and the alkali polishing time is 400 s. Since the amorphous silicon layer covered with a silicon dioxide mask of more than 5 nm has alkali corrosion resistance under the protection of the additive, the p-type amorphous silicon layer and the tunneling oxide layer in the p region will not be corroded. The p-type amorphous silicon layer and the tunneling oxide layer in the n region are removed, and the n-region amorphous silicon layer is polished again. At the same time, the p-type amorphous silicon layer and the tunneling layer plated on the front are removed. Then, neutralize the NaOH solution and clean metal ions in the HCl solution. Complete the water washing and heat drying processes.

[0088] Step 6: Use a PECVD tube coating equipment to deposit the third tunneling oxide layer, the second intrinsic amorphous silicon layer, the low-doped n-type amorphous silicon layer, the fourth tunneling oxide layer, the highly doped n-type amorphous silicon layer, and the second silicon dioxide mask layer on the back of the silicon wafer at a temperature of 430°C using SiH4, N2O, PH3, and H2 gases. The N2O flow rate of the third tunneling oxide layer is 10000 sccm, the radio frequency power is 15000 W, the duty cycle is 1:100, the deposition time is 110 s, and the film thickness is controlled at 2 nm. The SiH4 flow rate of the second intrinsic amorphous silicon layer is 2850 sccm, and the H2 flow rate is 11500 sccm. The radio frequency power is 12000 W, the duty cycle is 1:15, the deposition time is 200 s, and the film thickness is controlled at 25 nm. The SiH4 flow rate of the low-doped n-type amorphous silicon layer is 2880 sccm, the H2 flow rate is 12000 sccm, the ratio of the PH3 flow rate to the SiH4 flow rate is 1:10, the radio frequency power is 12000 W, the duty cycle is 1:15, the deposition time is 250 s, and the film thickness is controlled at 30 nm. The N2O flow rate of the fourth tunneling oxide layer is 10000 sccm, the radio frequency power is 15000 W, the duty cycle is 1:100, the deposition time is 110 s, and the film thickness is controlled at 2 nm. The SiH4 flow rate of the highly doped n-type amorphous silicon layer is 2880 sccm, the H2 flow rate is 12000 sccm, the ratio of the PH3 flow rate to the SiH4 flow rate is 1:5.3, the radio frequency power is 12000 W, the duty cycle is 1:15, the deposition time is 600 s, and the film thickness is controlled at 75 nm. The SiH4 flow rate of the second silicon dioxide mask layer is 1600 sccm, the N2O flow rate is 7000 sccm, the radio frequency power is 12000 W, the duty cycle is 1:20, the deposition time is 75 s, and the film thickness is controlled at 7 nm.

[0089] Step 7: Put the silicon wafer into a tube annealing furnace for high-temperature annealing crystallization treatment. The low-doped p-type amorphous silicon layer is converted into a low-doped p-type polycrystalline silicon layer, the high-doped p-type amorphous silicon layer is converted into a high-doped p-type polycrystalline silicon layer, the low-doped n-type amorphous silicon layer is converted into a low-doped n-type polycrystalline silicon layer, and the high-doped p-type amorphous silicon layer is converted into a high-doped p-type polycrystalline silicon layer. The annealing crystallization temperature is 930 °C, the nitrogen flow rate is 6000 sccm, the pressure is 800 mbar, the crystallization annealing time is 3600 s, and the sheet resistance of the back n-region after annealing crystallization is controlled at 50 Ω / □.

[0090] Step 8: Use a green picosecond laser to etch and remove the second silicon dioxide mask layer in the p-region of the battery and the interval region between the p-region and the n-region according to the designed pattern. The laser spot width is 130 um and the laser power is 100 W.

[0091] Step 9: Use a chain cleaning equipment to clean the second silicon dioxide mask layer plated around the front of the silicon wafer in an HF solution. The volume fraction of HF is 35%, and then dry it.

[0092] Step 10: Use a tank cleaning equipment to place the silicon wafer in a mixed solution of NaOH and additives for front surface texturing. The volume fraction of the additive in the texturing solution is 0.6%, the volume fraction of the alkali solution is 1.1%, the temperature is 82 °C, and the texturing time is 450 s. Since the polycrystalline silicon layer covered with the silicon dioxide mask layer has alkali corrosion resistance under the protection of the additive, the phosphorus-doped polycrystalline silicon and the tunneling oxide layer in the n-region will not be corroded. The phosphorus-doped polycrystalline silicon and the tunneling oxide layer in the p-region and the interval region between the p-region and the n-region are removed, and a textured surface structure is formed in the interval region and the front surface. Pickle in an HF solution to remove the first silicon dioxide mask layer in the back p-region and the second silicon dioxide mask layer in the n-region of the silicon wafer. The volume fraction of HF in the solution is 20%, the temperature is 25 °C, and the pickling time is 130 s. Then complete the water washing and hot drying treatment. The weight loss of the silicon wafer is controlled at 0.3 g / wafer, and the reflectivity of the textured surface is controlled at 9.8%.

[0093] Step 11: Use a tube ALD atomic layer deposition equipment to deposit a layer of alumina on the entire front and back of the silicon wafer at the same time. The deposition temperature is 295 °C, the TMA flow rate is 20 sccm, the pure water flow rate is 20 sccm, the number of cycles is 40 times, and the thickness of the alumina is controlled at 5 nm.

[0094] Step 12: Use a tube PECVD equipment to deposit the front antireflection film first. The front film layer is a multi-layer SiN x / SiO x N y / SiO2 structure. The first layer of SiN xThe deposition temperature is 475 °C, the silane flow rate is 2450 sccm, the ammonia flow rate is 8000 sccm, the power is 12000 W, the deposition time is 110 s, the film thickness is controlled at 12 nm, and the refractive index is controlled at 2.25%; the second layer of SiN x The deposition temperature is 475 °C, the silane flow rate is 1800 sccm, the ammonia flow rate is 12000 sccm, the power is 13500 W, the deposition time is 200 s, the film thickness is controlled at 17 nm, and the refractive index is controlled at 2.15%; the third layer of SiN x The deposition temperature is 475 °C, the silane flow rate is 1400 sccm, the ammonia flow rate is 13000 sccm, the power is 14000 W, the deposition time is 220 s, the film thickness is controlled at 18 nm, and the refractive index is controlled at 2.05%; the first layer of SiO x N y The deposition temperature is 475 °C, the silane flow rate is 1000 sccm, the ammonia flow rate is 5000 sccm, the nitrous oxide flow rate is 6000 sccm, the power is 15000 W, the deposition time is 140 s, the film thickness is controlled at 12 nm, and the refractive index is controlled at 1.9%; the second layer of SiO x N y The deposition temperature is 475 °C, the silane flow rate is 800 sccm, the ammonia flow rate is 4000 sccm, the nitrous oxide flow rate is 8000 sccm, the power is 15000 W, the deposition time is 150 s, the film thickness is controlled at 11 nm, and the refractive index is controlled at 1.7%; the deposition temperature of SiO2 is 475 °C, the silane flow rate is 800 sccm, the nitrous oxide flow rate is 10000 sccm, the power is 15000 W, the deposition time is 100 s, the film thickness is controlled at 7 nm, and the refractive index is controlled at 1.5%.

[0095] After the front-side coating is completed, the silicon wafer is taken out, the silicon wafer is turned over and put into the PECVD equipment again, and an antireflection film is deposited on the back side. The back-side film layer is a multi-layer SiN x structure; the first layer of SiN x The deposition temperature is 530 °C, the silane flow rate is 2700 sccm, the ammonia flow rate is 9500 sccm, the power is 15000 W, the deposition time is 140 s, the film thickness is controlled at 20 nm, and the refractive index is controlled at 2.28%; the second layer of SiN x The deposition temperature is 530 °C, the silane flow rate is 1900 sccm, the ammonia flow rate is 14000 sccm, the power is 15000 W, the deposition time is 190 s, the film thickness is controlled at 26 nm, and the refractive index is controlled at 2.17%; the third layer of SiN x The deposition temperature is 530 °C, the silane flow rate is 1400 sccm, the ammonia flow rate is 13000 sccm, the power is 17000 W, the deposition time is 280 s, and the film thickness is controlled at 37 nm, and the refractive index is controlled at 2.06%.

[0096] Step 13: The front and back electrodes are fabricated using a screen printing process. According to the designed printing pattern, silver-aluminum paste is used for printing in the p-region, and pure silver paste is used for printing in the n-region. After printing, a rapid sintering is performed using an infrared industrial belt sintering furnace at a peak temperature of 780 °C to form the positive electrode 13 and the negative electrode 14 of the metal contact electrode.

[0097] Step 14: The silicon wafer is subjected to light injection treatment using an industrial belt light injection furnace at a temperature of 650 °C to activate the H atoms from the passivation layer, and finally a passivated contact cell with a double tunneling polysilicon layer is obtained.

[0098] Example 2

[0099] This example provides a method for preparing a passivated contact cell with a double tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s, and the deposition time of the second tunneling oxide layer is shortened to 118 s; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Example 1, so they will not be elaborated here.

[0100] Example 3

[0101] This example provides a method for preparing a passivated contact cell with a double tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is extended to 133 s, and the deposition time of the second tunneling oxide layer is extended to 133 s; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Example 1.

[0102] Example 4

[0103] This example provides a method for preparing a passivated contact cell with a double tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Example 1.

[0104] Example 5

[0105] This example provides a method for preparing a passivated contact cell with a double tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s; the deposition time of the first tunneling oxide layer in step 6 is shortened to 105 s, and the deposition time of the second tunneling oxide layer is shortened to 105 s; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Example 1.

[0106] Example 6

[0107] This embodiment provides a method for preparing a passivated contact battery with a double-tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s; the deposition time of the first tunneling oxide layer in step 6 is shortened to 105 s; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Embodiment 1.

[0108] Embodiment 7

[0109] This embodiment provides a method for preparing a passivated contact battery with a double-tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s, the deposition time of the highly doped p-type amorphous silicon layer is shortened to 1055 s, and the ratio of the B2H6 flow rate to the SiH4 flow rate is adjusted to 1:1.4; the deposition time of the first tunneling oxide layer in step 6 is shortened to 105 s; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Embodiment 1, so they will not be elaborated here.

[0110] Embodiment 8

[0111] This embodiment provides a method for preparing a passivated contact battery with a double-tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s, the deposition time of the highly doped p-type amorphous silicon layer is shortened to 1055 s, and the ratio of the B2H6 flow rate to the SiH4 flow rate is adjusted to 1:1.4; the deposition time of the first tunneling oxide layer in step 6 is shortened to 105 s, and the deposition time of the highly doped n-type amorphous silicon layer is shortened to 560 s; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Embodiment 1.

[0112] Embodiment 9

[0113] This embodiment provides a method for preparing a passivated contact battery with a double-tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s, the deposition time of the highly doped p-type amorphous silicon layer is shortened to 1055 s, and the ratio of the B2H6 flow rate to the SiH4 flow rate is adjusted to 1:1.4; the deposition time of the first tunneling oxide layer in step 6 is shortened to 105 s, the deposition time of the highly doped n-type amorphous silicon layer is shortened to 560 s, and the ratio of the PH3 flow rate to the SiH4 flow rate is adjusted to 1:5.25; the annealing crystallization temperature in step 7 is increased to 935 °C, the remaining steps and conditions are the same as those in Embodiment 1.

[0114] Embodiment 10

[0115] This embodiment provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 118 s, the deposition time of the highly doped p-type amorphous silicon layer is shortened to 1055 s, and the ratio of the B2H6 flow rate to the SiH4 flow rate is adjusted to 1:1.4; in step 6, the deposition time of the first tunneling oxide layer is shortened to 105 s, the deposition time of the highly doped n-type amorphous silicon layer is shortened to 560 s, and the ratio of the PH3 flow rate to the SiH4 flow rate is adjusted to 1:5.2; in step 7, the annealing crystallization temperature is increased to 935 °C, and the remaining steps and conditions are the same as those in Embodiment 1.

[0116] Example 11

[0117] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 2 is shortened to 80 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0118] Example 12

[0119] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the second tunneling oxide layer in step 2 is extended to 150 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0120] Example 13

[0121] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the intrinsic amorphous silicon layer in step 2 is shortened to 150 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0122] Example 14

[0123] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the ratio of the B2H6 flow rate to the SiH4 flow rate of the lowly doped p-type amorphous silicon layer in step 2 is adjusted to 1:3, the remaining steps and conditions are the same as those in Embodiment 1.

[0124] Example 15

[0125] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the highly doped p-type amorphous silicon layer in step 2 is extended to 1300 s, the remaining steps and conditions are the same as those in Embodiment 1.

[0126] Example 16

[0127] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the ratio of the B2H6 flow rate to the SiH4 flow rate of the highly doped p-type amorphous silicon layer in step S2 is adjusted to 1:2, the remaining steps and conditions are the same as those in Embodiment 1.

[0128] Example 17

[0129] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the first tunneling oxide layer in step 6 is shortened to 80 s, the other steps and conditions are the same as those in Example 1.

[0130] Example 18

[0131] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the second tunneling oxide layer in step 6 is extended to 130 s, the other steps and conditions are the same as those in Example 1.

[0132] Example 19

[0133] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the intrinsic amorphous silicon layer in step 6 is shortened to 150 s, the other steps and conditions are the same as those in Example 1.

[0134] Example 20

[0135] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the lightly doped n-type amorphous silicon layer in step 6 is extended to 300 s, the other steps and conditions are the same as those in Example 1.

[0136] Example 21

[0137] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the ratio of the PH3 flow rate to the SiH4 flow rate of the lightly doped n-type amorphous silicon layer in step 6 is adjusted to 1:7, the other steps and conditions are the same as those in Example 1.

[0138] Example 22

[0139] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the deposition time of the heavily doped n-type amorphous silicon layer in step 6 is shortened to 500 s, the other steps and conditions are the same as those in Example 1.

[0140] Example 23

[0141] This comparative example provides a method for preparing a passivated contact cell with a double-tunneling polysilicon layer. Except that the annealing crystallization temperature in step 7 is increased to 960 °C, the other steps and conditions are the same as those in Example 1.

[0142] The specific electrical performance parameters of the fabricated solar cells in different embodiments are shown in Table 1. It can be seen that for the TBC solar cell fabricated in Embodiment 9, the Voc reaches 0.7478 V, the Isc reaches 14.174 A, the FF reaches 84.96%, and the photoelectric conversion efficiency Eta reaches 27.04%. The average efficiency is much higher than the industry level. This is because the double tunneling passivation contact structure in the p-region and n-region has better passivation performance. Additionally, precise doping is achieved in the p-type polysilicon layer in the p-region and the n-type polysilicon layer in the n-region, resulting in higher carrier transport and collection efficiency, thus improving the electrical performance.

[0143]

[0144]

[0145] Table 1 Electrical Performance Parameters of Solar Cells Fabricated in Embodiments and Comparative Examples

[0146] A method for fabricating a passivation contact solar cell with a novel double tunneling polysilicon layer according to the present invention uses plasma enhanced chemical vapor deposition technology (PECVD) to fabricate the tunneling oxide layer and p-type polysilicon in the p-region and the tunneling oxide layer and n-type polysilicon in the n-region, which can effectively improve the solar cell conversion efficiency and reduce the production cost of the solar cell. Compared with the method for fabricating the tunneling polycrystalline passivation contact structure in the p-region and n-region of a TBC solar cell using the traditional LPCVD + diffusion technology, the method for fabricating the TBC solar cell according to the present invention realizes a double tunneling passivation contact structure, improves the doping level and passivation performance of the p-type polysilicon in the p-region and the doping level and passivation performance of the n-type polysilicon in the n-region, and the efficiency can be increased by 0.15% - 0.25%. The fabrication of the double tunneling passivation contact structure avoids the use of LPCVD equipment and high-temperature boron diffusion, avoids frequent replacement due to quartz tube breakage, improves production stability, and reduces the production cost of the TBC solar cell. The amorphous silicon in the p-region and n-region can be simultaneously annealed and crystallized into polysilicon in one step, reducing the production steps and the production cost.

[0147] It can be understood that the present invention is described through some embodiments. Those skilled in the art know that without departing from the spirit and scope of the present invention, various changes or equivalent replacements can be made to these features and embodiments. Additionally, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A preparation method of a passivated contact battery with a double-tunneling polysilicon layer, characterized in that, It includes the following steps: S1. Wafer surface treatment: The wafer is successively subjected to alkali cleaning, polishing, acid cleaning, water washing and drying; S2. Deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a highly doped p-type amorphous silicon layer, and a first silicon dioxide mask layer on the back side of the wafer in sequence; S3. Remove the first silicon dioxide mask layer in the n-region on the back side of the wafer by laser etching; S4. Remove the first silicon dioxide mask layer deposited around the front side of the wafer by acid etching; S5. Polish the n-region on the back side of the wafer by alkali etching to remove the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the low-doped p-type amorphous silicon layer, the second tunneling oxide layer, and the highly doped p-type amorphous silicon layer in the n-region on the back side of the wafer and the first silicon dioxide mask layer deposited around the front side of the wafer; S6. Deposit a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doped n-type amorphous silicon layer, a fourth tunneling oxide layer, a highly doped n-type amorphous silicon layer, and a second silicon dioxide mask layer on the back side of the wafer in sequence; S7. Anneal and crystallize the wafer, convert the low-doped p-type amorphous silicon layer into a low-doped p-type polycrystalline silicon layer, convert the highly doped p-type amorphous silicon layer into a highly doped p-type polycrystalline silicon layer, convert the low-doped n-type amorphous silicon layer into a low-doped n-type polycrystalline silicon layer, and convert the highly doped p-type amorphous silicon layer into a highly doped p-type polycrystalline silicon layer; S8. Remove the second silicon dioxide mask layer in the p-region on the back side of the wafer and the spacer region between the p-region and the n-region by laser etching; S9. Remove the second silicon dioxide mask layer deposited around the front side of the wafer by acid etching; S10. Remove the third tunneling oxide layer, the second intrinsic amorphous silicon layer, the low-doped n-type amorphous silicon layer, the fourth tunneling oxide layer, and the highly doped n-type amorphous silicon layer on the front side of the wafer, in the p-region on the back side of the wafer, and in the spacer region between the p-region and the n-region on the back side of the wafer, form a textured surface structure on the front side of the wafer, in the p-region on the back side of the wafer, and in the spacer region between the p-region and the n-region on the back side of the wafer, then successively carry out acid washing to remove the first silicon dioxide mask layer in the p-region on the back side of the wafer and the second silicon dioxide mask layer in the n-region, water washing, and hot drying; S11. Deposit an aluminum oxide layer on both sides of the wafer; S12. Deposit an antireflection film on both sides of the wafer; S13. Complete the production of the front and back electrodes of the wafer by screen printing and sintering; S14. The wafer is subjected to light injection treatment to activate the H atoms from the passivation layer to obtain a passivated contact cell with a double tunneling polycrystalline silicon layer.

2. The preparation method of the passivated contact battery with a double-tunneling polysilicon layer according to claim 1, characterized in that, In S1, the weight reduction of the wafer is controlled at 0.3 - 0.5 g / wafer, and the reflectivity is controlled at 43% - 47%. It includes the following steps: S1.

1. Alkali cleaning: Place the wafer in a mixed solution of NaOH and H2O2 for cleaning the surface oil stain. The volume fraction of NaOH in the mixed solution is 0.5% - 1.5%, the volume fraction of H2O2 is 4% - 10%, the temperature is 60 - 70 °C, and the cleaning time is 100 - 250 s; S1.

2. Polishing: Carry out wafer polishing treatment in a NaOH solution. The volume fraction of NaOH in the NaOH solution is 8% - 12%, the temperature is 78 - 85 °C, and the polishing time is 120 - 180 s; S1.

3. Acid cleaning: Neutralize the NaOH solution, and clean metal ions and the oxide layer in a mixed acid solution; S1.4, water washing and heat drying treatment.

3. The method for preparing a passivated contact cell with a double-tunneling polysilicon layer according to claim 1, characterized in that, In S2, a coating equipment is used to deposit a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a low-doped p-type amorphous silicon layer, a second tunneling oxide layer, a high-doped p-type amorphous silicon layer, and a first silicon dioxide mask layer on the back of the silicon wafer in sequence at a temperature of 350 - 430 °C using SiH4, N2O, B2H6, and H2 gases. In S6, a coating equipment is used to deposit a third tunneling oxide layer, a second intrinsic amorphous silicon layer, a low-doped n-type amorphous silicon layer, a fourth tunneling oxide layer, a high-doped n-type amorphous silicon layer, and a second silicon dioxide mask layer on the back of the silicon wafer in sequence at a temperature of 400 - 460 °C using SiH4, N2O, PH3, and H2 gases.

4. The preparation method of the passivated contact battery with a double-tunneling polysilicon layer according to claim 1, characterized in that, In S3, a green picosecond laser is used to etch and remove the first silicon dioxide mask layer in the n-region on the back of the silicon wafer according to the designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W. In S8, a green picosecond laser is used to etch and remove the second silicon dioxide mask layer in the p-region and the spacer region between the p-region and the n-region on the back of the silicon wafer according to the designed pattern. The laser spot width is 100 - 200 um, and the laser power is 80 - 200 W.

5. The preparation method of the passivated contact cell with a double-tunneling polysilicon layer according to claim 1, characterized in that, In S4, a chain cleaning equipment is used to clean off the first silicon dioxide mask layer that is deposited by mistake on the front of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out. In S9, a chain cleaning equipment is used to clean off the second silicon dioxide mask layer that is deposited by mistake on the front of the silicon wafer in an HF solution. The volume fraction of HF is 30% - 40%, and then drying is carried out.

6. The preparation method of the passivated contact cell with a double-tunneling polysilicon layer according to claim 1, characterized in that, The polishing in S5 includes the following steps: S5.1, using a tank cleaning equipment to place the silicon wafer in a polishing solution for cleaning and etching. The volume fraction of the alkaline solution in the polishing solution is 3 - 6%, the volume fraction of the additive is 0.6 - 1.0%, the temperature is 70 - 80 °C, and the polishing time is 300 - 500 s. S5.2, neutralizing the alkaline solution and cleaning metal ions in an acidic solution. S5.3, water washing and heat drying treatment.

7. The method for preparing a passivated contact cell with a double-tunneling polysilicon layer according to claim 1, wherein, In S7, the silicon wafer is put into a tube annealing furnace for high-temperature annealing and crystallization treatment. The annealing and crystallization temperature is 900 - 960 °C, the nitrogen flow rate is 5000 - 7000 sccm, the pressure is 700 - 900 mbar, the crystallization annealing time is 3000 - 4200 s, and the sheet resistance of the back n-region after annealing and crystallization is controlled at 30 - 60 Ω / □.

8. The preparation method of the passivated contact cell with a double-tunneling polysilicon layer according to claim 1, characterized in that, In S10, the weight reduction of the silicon wafer is controlled at 0.2 - 0.4 g / wafer, and the surface texture reflectivity is controlled at 9% - 11%. It includes the following steps: S10.1, using a tank cleaning equipment to place the silicon wafer in a texturing solution. The volume fraction of the alkaline solution in the texturing solution is 0.9 - 1.3%, the volume fraction of the additive is 0.4 - 0.8%, the temperature is 80 - 85 °C, and the texturing time is 400 - 500 s. S10.2, removing the first silicon dioxide mask layer in the p-region and the second silicon dioxide mask layer in the n-region on the back of the silicon wafer in an acid pickling solution. The volume fraction of the acid in the acid pickling solution is 15 - 25%, the temperature is 20 - 30 °C, and the acid pickling time is 100 - 150 s. S10.3, water washing and heat drying treatment.

9. The preparation method of the passivated contact battery with a double-tunneling polysilicon layer according to claim 1, characterized in that, The front film layer of the silicon wafer in S12 is a multi-layer SiN x / SiO x N y / SiO2 structure, and the back film layer of the silicon wafer is a multi-layer SiN x structure.

10. The preparation method of the passivated contact battery with a double-tunneling polysilicon layer according to claim 1, wherein, In S11, a tubular ALD atomic layer deposition equipment is used to deposit aluminum oxide on the front and back sides of the silicon wafer. The deposition temperature is 250 - 350 °C, the flow rate of TMA is 15 - 25 sccm, the flow rate of pure water is 15 - 25 sccm, the number of cycles is 30 - 50 times, and the thickness of the aluminum oxide is controlled within 4 - 6 nm; In S13, a screen printing process is used to fabricate the front and back electrodes according to the designed printing pattern. Silver-aluminum paste is used for printing in the p region, and pure silver paste is used for printing in the n region; After printing, an infrared industrial belt sintering furnace is used to perform rapid sintering at a peak temperature of 730 - 800 °C to form metal contact electrodes; In S14, an industrial belt optical injection furnace is used to perform optical injection treatment at a temperature of 600 - 680 °C to activate H atoms from the passivation layer.

11. The preparation method of the passivated contact battery with a double-tunneling polysilicon layer according to claim 1, characterized in that, In S2, a PECVD tubular coating equipment is used to sequentially deposit the first tunneling oxide layer, the first intrinsic amorphous silicon layer, the low-doped p-type amorphous silicon layer, the second tunneling oxide layer, the high-doped p-type amorphous silicon layer, and the first silicon dioxide mask layer on the back side of the silicon wafer at a temperature of 350 - 430 °C, including the following deposition parameters: The first tunneling oxide layer: The flow rate of N2O is 10000 - 12000 sccm, the radio frequency power is 13000 - 16000 W, the duty cycle is 1:(80 - 120), the deposition time is 80 - 150 s, and the film thickness is controlled to be 1 - 2 nm; The first intrinsic amorphous silicon layer: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm; the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 150 - 300 s, and the film thickness is controlled to be 15 - 30 nm; The low-doped p-type amorphous silicon layer: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm, the ratio of the flow rate of B2H6 to the flow rate of SiH4 is 1:(3 - 5), the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 200 - 400 s, and the film thickness is controlled to be 20 - 40 nm; The second tunneling oxide layer: The flow rate of N2O is 10000 - 12000 sccm, the radio frequency power is 13000 - 16000 W, the duty cycle is 1:(80 - 120), the deposition time is 80 - 150 s, and the film thickness is controlled to be 1 - 2 nm; The high-doped p-type amorphous silicon: The flow rate of SiH4 is 2500 - 3500 sccm, the flow rate of H2 is 9000 - 15000 sccm, the ratio of the flow rate of B2H6 to the flow rate of SiH4 is 1:(1 - 2), the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(10 - 20), the deposition time is 900 - 1300 s, and the film thickness is controlled to be 100 - 140 nm; The first silicon dioxide mask layer: The flow rate of SiH4 is 1800 - 2200 sccm, the flow rate of N2O is 7500 - 10000 sccm, the radio frequency power is 11000 - 15000 W, the duty cycle is 1:(15 - 25), the deposition time is 60 - 120 s, and the film thickness is controlled to be 5 - 10 nm.

12. The preparation method of the passivated contact cell with a double-tunneling polysilicon layer according to claim 1, wherein, In S6, a PECVD tube coating equipment is used to sequentially deposit the third tunneling oxide layer, the second intrinsic amorphous silicon layer, the low-doped n-type amorphous silicon layer, the fourth tunneling oxide layer, the highly doped n-type amorphous silicon layer, and the second silicon dioxide mask layer on the back of the silicon wafer at a temperature of 400 - 460 °C, including the following deposition parameters: The third tunneling oxide layer: The flow rate of N2O is 9000 - 11000 sccm, the radio frequency power is 13000 - 17000 W, the duty cycle is 1:(60 - 120), the deposition time is 80 - 130 s, and the film thickness is controlled to be 1.5 - 2.5 nm; The second intrinsic amorphous silicon layer: The flow rate of SiH4 is 2300 - 3300 sccm, the flow rate of H2 is 11000 - 13000 sccm; the radio frequency power is 11000 - 13000 W, the duty cycle is 1:(10 - 20), the deposition time is 150 - 250 s, and the film thickness is controlled to be 20 - 30 nm; The low-doped n-type amorphous silicon layer: The flow rate of SiH4 is 2300 - 3300 sccm, the flow rate of H2 is 11000 - 13000 sccm, the ratio of the flow rate of PH3 to the flow rate of SiH4 is 1:(7 - 13), the radio frequency power is 11000 - 13000 W, the duty cycle is 1:(10 - 20), the deposition time is 200 - 300 s, and the film thickness is controlled to be 20 - 40 nm; The fourth tunneling oxide layer: The flow rate of N2O is 9000 - 11000 sccm, the radio frequency power is 13000 - 17000 W, the duty cycle is 1:(20 - 120), the deposition time is 80 - 130 s, and the film thickness is controlled to be 1.5 - 2.5 nm; The highly doped n-type amorphous silicon layer: The flow rate of SiH4 is 2300 - 3300 sccm, the flow rate of H2 is 11000 - 13000 sccm, the ratio of the flow rate of PH3 to the flow rate of SiH4 is 1:(3 - 7), the radio frequency power is 11000 - 13000 W, the duty cycle is 1:(10 - 20), the deposition time is 500 - 700 s, and the film thickness is controlled to be 60 - 80 nm; The second silicon dioxide mask layer: The flow rate of SiH4 is 1500 - 1800 sccm, the flow rate of N2O is 6000 - 8000 sccm, the radio frequency power is 11000 - 13000 W, the duty cycle is 1:(15 - 25), the deposition time is 60 - 90 s, and the film thickness is controlled to be 5 - 10 nm.

13. The preparation method of the passivated contact battery with a double-tunneling polysilicon layer according to claim 1, characterized in that, The anti-reflection film on the front side of the silicon wafer in S12 is a multi-layer SiN x / SiO x N y / SiO2 structure, which successively includes the following structures and deposition parameters: The first layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 2300 - 2600 sccm, the ammonia flow rate is 7000 - 9000 sccm, the power is 10000 - 13000 W, the deposition time is 100 - 130 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 2.2 - 2.3%. The second layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 1700 - 1900 sccm, the ammonia flow rate is 11000 - 13000 sccm, the power is 12000 - 15000 W, the deposition time is 180 - 220 s, the film thickness is controlled to be 15 - 20 nm, and the refractive index is controlled to be 2.1 - 2.2%; The third layer of SiN x The deposition temperature is 450 - 500 °C, the silane flow rate is 1100 - 1500 sccm, the ammonia flow rate is 11000 - 15000 sccm, the power is 13000 - 15000 W, the deposition time is 200 - 250 s, the film thickness is controlled at 17 - 24 nm, and the refractive index is controlled at 2 - 2.1%; The first layer of SiO x N y The deposition temperature is 450 - 500 °C, the silane flow rate is 900 - 1100 sccm, the ammonia flow rate is 4000 - 6000 sccm, the nitrous oxide flow rate is 5000 - 7000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.8 - 2%; The second layer of SiO x N y The deposition temperature is 450 - 500 °C, the silane flow rate is 700 - 900 sccm, the ammonia flow rate is 3500 - 4500 sccm, the nitrous oxide flow rate is 7000 - 9000 sccm, the power is 14000 - 16000 W, the deposition time is 140 - 160 s, the film thickness is controlled to be 10 - 15 nm, and the refractive index is controlled to be 1.6 - 1.8%. The deposition temperature of SiO2 is 450 - 500 °C, the flow rate of silane is 700 - 900 sccm, the flow rate of nitrous oxide is 9000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 80 - 120 s, the film thickness is controlled to be 5 - 10 nm, and the refractive index is controlled to be 1.4 - 1.6%; The anti-reflection film on the back of the silicon wafer is a multi-layer SiN x structure, which successively includes the following structures and deposition parameters: The first layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 2500 - 2900 sccm, the ammonia flow rate is 8000 - 11000 sccm, the power is 14000 - 16000 W, the deposition time is 130 - 150 s, the film thickness is controlled to be 15 - 25 nm, and the refractive index is controlled to be 2.2 - 2.3%; The second layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1700 - 2100 sccm, the ammonia flow rate is 13000 - 15000 sccm, the power is 14500 - 16500 W, the deposition time is 170 - 210 s, the film thickness is controlled to be 20 - 30 nm, and the refractive index is controlled to be 2.1 - 2.2%. The third layer of SiN x The deposition temperature is 500 - 550 °C, the silane flow rate is 1300 - 1500 sccm, the ammonia flow rate is 12000 - 15000 sccm, the power is 15000 - 19000 W, the deposition time is 250 - 300 s, the film thickness is controlled to be 30 - 40 nm, and the refractive index is controlled to be 2 - 2.1%.

14. A passivated contact cell with a double-tunneling polysilicon layer, characterized in that, Prepared by the preparation method according to any one of claims 1-13.

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