Fabrication method for back-contact battery with continuous back film deposition

Abstract

A fabrication method for a back-contact battery with a continuous back film deposition, comprising: forming in sequence a second semiconductor layer and a sacrificial isolation layer on the back surface of a silicon wafer obtained in S01, the second semiconductor layer comprising an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer; wherein the second semiconductor layer and the sacrificial isolation layer are deposited and formed in a deposition system using a plate-type CVD continuous deposition method; the deposition temperature of the second doped silicon layer and the deposition temperature of the isolation sacrificial layer being independently controlled at 150-200℃, and the sum of the deposition duration of the second doped silicon layer and the deposition duration of the sacrificial isolation layer being controlled at 1-4 minutes; and performing single-side cleaning to remove the sacrificial isolation layer and a wrap-around deposition layer on the back surface obtained in S7. Enabling the common utilization of a single deposition system greatly reduces equipment costs and simplifies processes. This effectively prevents contamination during continuous deposition, while maintaining optimal battery performance, and particularly superior passivation performance, fill factor, and battery conversion efficiency.

Description

A method for preparing a back contact battery with continuous back film plating

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410289465.7 filed with the Patent Office of China on March 14, 2024, entitled “A method for preparing a back-contact battery with back-film continuous plating”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure belongs to the technical field of back contact battery preparation, and particularly relates to a method for preparing a back contact battery with back film continuous plating. Background Art

[0004] At present, the back of the back contact battery is provided with a first semiconductor layer and a second semiconductor layer, and an intrinsic amorphous silicon layer is usually stacked with a doped (boron) amorphous or microcrystalline silicon layer as the second semiconductor layer. The intrinsic hydrogenated amorphous silicon layer and the doped amorphous / microcrystalline silicon layer are generally formed by plate-type PECVD coating. In order to avoid the contamination of the intrinsic film layer deposited on the subsequent carrier supporting the silicon wafer by the doping elements, resulting in a decrease in the passivation effect, two sets of deposition systems are used for the two film layers when depositing the second semiconductor layer, as shown in Figure 1, both using independent deposition chambers and independent carriers for carrying silicon wafers, that is, the intrinsic amorphous silicon is deposited in the first deposition system (placed on the first carrier 6 and sequentially passed through the loading system 1, preheating chamber 2, first coating chamber 3, cooling chamber 4, etc.). The deposition of the doped amorphous / microcrystalline silicon layer is carried out in a second deposition system (placed on a second carrier 8 and sequentially passing through the loading system 1, preheating chamber 2, second doping chamber 7, cooling chamber 4 and unloading system 5). Two loading and unloading systems are required (the loading and unloading systems include the loading system and the unloading system) and two coating systems (the coating system includes the preheating chamber, the coating chamber and the cooling chamber), and two carriers are used. The plate-type PECVD equipment is very expensive. Therefore, the back-contact battery currently has problems such as high equipment investment.

[0005] Although both CN101755072A and CN112267105A deposit an intrinsic hydrogenated amorphous silicon layer and a doped amorphous / microcrystalline silicon layer in a single chamber, both applications perform chamber purge after depositing the doped amorphous / microcrystalline silicon layer, and then deposit an intrinsic layer or an oxide layer to cover the entire chamber, thereby preventing contamination of the intrinsic layer during the next cycle of deposition. These are both chamber treatments. The disadvantages of chamber treatments are that the doping source in one chamber covers a large area, the treatment difficulty (such as time, deposition film thickness, and power) is relatively high, the cost is high, and production efficiency is reduced. Furthermore, due to the large area that needs to be covered, the risk of contamination of the intrinsic layer during the next cycle of deposition remains high.

[0006] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure and does not necessarily constitute prior art or public known technology.

[0007] Application Contents

[0008] The purpose of the present disclosure is to overcome the defects of the back-contact battery in the prior art, such as high equipment investment, complex process operation or difficult processing, and high pollution risk, and to provide a preparation method for a back-contact battery with continuous back film plating. The preparation method of the back-contact battery can realize the use of only one set of deposition system, greatly saving equipment costs and simplifying the process. It can effectively prevent pollution during continuous plating while maintaining better battery performance, especially excellent passivation performance, fill factor and battery conversion efficiency.

[0009] To achieve the above objectives, the present disclosure provides a method for preparing a back-contact battery with continuous back-film plating, comprising:

[0010] S01, forming a first semiconductor layer on the back side of the silicon wafer, and performing a first etching opening on the first semiconductor layer to form a second semiconductor opening region;

[0011] S5. Forming a second semiconductor layer and an isolation sacrificial layer in sequence on the back side of the silicon wafer obtained in S01, wherein the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer;

[0012] The second semiconductor layer and the isolation sacrificial layer are deposited in a deposition system by plate-type CVD continuous plating, and the process includes: placing the silicon wafer obtained in S01 on a carrier, first depositing an intrinsic hydrogenated amorphous silicon layer in a first coating chamber, then directly transferring the wafer to a second doping chamber in the current deposition system to continue depositing a second doped silicon layer, then performing a purge operation on the second doping chamber, and after purge, continuing to deposit the isolation sacrificial layer on the outer surface of the carrier and the corresponding film layer thereon in the second doping chamber; the deposition temperature of the intrinsic hydrogenated amorphous silicon layer is controlled at 190-220° C., and the deposition time is controlled at 1-2 minutes, the deposition temperatures of the second doped silicon layer and the isolation sacrificial layer are independently controlled at 150-200° C., and the sum of the deposition times of the second doped silicon layer and the isolation sacrificial layer is controlled at 1-4 minutes;

[0013] S6. forming a front passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer;

[0014] S7, performing a second etching to open the second semiconductor layer and the corresponding isolation sacrificial layer on the back side obtained in S6, to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0015] S8. Single-sided cleaning is performed on the back surface obtained in S7 to remove the isolation sacrificial layer and the wrap-around plating layer on the back surface obtained in S7.

[0016] In some optional embodiments of the present disclosure, the ratio of the deposition temperatures of the intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer is controlled to be 1:0.68-1.05.

[0017] In some optional embodiments of the present disclosure, the isolation sacrificial layer is at least one of silicon nitride, silicon oxynitride and silicon oxide.

[0018] In some optional embodiments of the present disclosure, the conditions for depositing the isolation sacrificial layer include: a pressure of 80-300 Pa and a power supply of 0.2-2 kW.

[0019] In some optional embodiments of the present disclosure, the conditions for depositing the isolation sacrificial layer also include: introducing a mixed gas containing silane, a deposition element gas source and hydrogen, the deposition element gas source includes silicon dioxide or at least one of nitrous oxide and ammonia, the flow rate of silane is 100-1500sccm, the flow rate of the deposition element gas source is 100-1500sccm, and the flow rate of hydrogen is 5000-10000sccm.

[0020] In some optional embodiments of the present disclosure, the deposition system includes a loading system, a preheating chamber, a first coating chamber, a second doping chamber, a cooling chamber and a unloading system; after the carrier carries the silicon wafer, it enters the loading system, the preheating chamber, the first coating chamber, the second doping chamber, the cooling chamber and the unloading system in sequence.

[0021] In some optional embodiments of the present disclosure, the deposition time of the isolation sacrificial layer is 0.5-1.5 minutes, and the deposition time of the second doped silicon layer is 1-2 minutes.

[0022] In some optional embodiments of the present disclosure, the deposition conditions of the intrinsic hydrogenated amorphous silicon layer include: a mass flow rate of silane of 500-2000 sccm, a mass flow rate of hydrogen of 3000-10000 sccm, a pressure of 80-400 Pa, a power supply of 0.5-15 kW, and a time of 1-2 min.

[0023] In some optional embodiments of the present disclosure, the deposition conditions of the second doped silicon layer include: a mass flow rate of silane of 500-2000 sccm, a mass flow rate of borane of 300-1000 sccm, a mass flow rate of hydrogen of 3000-20000 sccm, a pressure of 80-500 Pa, and a power supply of 0.5-20 kW.

[0024] In some optional embodiments of the present disclosure, a thickness ratio of the intrinsic hydrogenated amorphous silicon layer, the second doped silicon layer, and the isolation sacrificial layer is 1:0.75-4.5:0.375-2.

[0025] In some optional embodiments of the present disclosure, the thickness of the intrinsic hydrogenated amorphous silicon layer is 4-8 nm, the thickness of the second doped silicon layer is 6-19 nm, and the thickness of the isolation sacrificial layer is 3-8 nm.

[0026] In some optional embodiments of the present disclosure, the S5 gas washing operation includes a process of repeated inflation and exhaust cycles, wherein inflation is to introduce an inert gas into the second doping chamber, and the number of inflation and exhaust cycles repeated is ≥1.

[0027] Further optionally, the duration of the gas washing operation is 30s-150s, the gas filling time is 5s-15s, and the gas extraction time is until the gas in the second doping chamber is evacuated to a vacuum pressure of 10 -1 Below Pa.

[0028] Further optionally, the flow rate of the inert gas introduced during inflation is 1000 sccm-10000 sccm.

[0029] In some optional embodiments of the present disclosure, in the single-side cleaning described in S8, the corrosion rate of the isolation sacrificial layer is ≥1 nm / s.

[0030] In some optional embodiments of the present disclosure, the absolute value of the difference in corrosion rate between the isolation sacrificial layer and the surrounding plating layer is 0.1-1.8 nm / s, and optionally 0.1-0.5 nm / s.

[0031] In some optional embodiments of the present disclosure, the conditions for the single-side cleaning in S8 include: treating the back side with a mixed solution of hydrofluoric acid and ultrapure water with a mass concentration of 2%-5%, and the treatment time is 2-15 minutes.

[0032] In some optional embodiments of the present disclosure, the first semiconductor layer includes a tunneling silicon oxide layer and a first doped polysilicon layer, and one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type.

[0033] Further optionally, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration is 10 20 cm -3 -10 21 cm -3 .

[0034] Further optionally, the effective doping concentration of the second doped silicon layer is 10 19 cm -3 -10 20 cm -3 .

[0035] In some optional embodiments of the present disclosure, S01, forming a first semiconductor layer on the back side of a silicon wafer, and performing a first etching opening on the first semiconductor layer to form a second semiconductor opening region; comprising:

[0036] S1, provide silicon wafers;

[0037] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer;

[0038] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region;

[0039] S4. Then, texturing and cleaning are performed, and the mask layer on the back of the silicon wafer is optionally removed during texturing and cleaning.

[0040] In some optional embodiments of the present disclosure, the method for preparing the back-contact battery with back film continuous plating further includes:

[0041] S9, depositing a conductive film layer on the back side of the silicon wafer obtained in S8;

[0042] S10, performing a third etching opening on the conductive film layer on the back side obtained in S9 to form an insulating groove isolating the first semiconductor opening region and the second semiconductor opening region;

[0043] S11 , forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S10 . Beneficial effects:

[0044] The present disclosure utilizes the above-mentioned technical solution, particularly a single deposition system (including a loading and unloading system and a coating system) for continuous coating of the intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer. This system is combined with timely purging, deposition of an isolation sacrificial layer, and control of deposition temperature and time. The isolation sacrificial layer is subsequently removed directly during a conventional cleaning step, eliminating the need for an additional etching process. This allows for the use of only one deposition system, significantly saving equipment costs and simplifying the process while maintaining superior battery performance, particularly excellent passivation performance, fill factor, and battery conversion efficiency. The continuous coating system includes two coating chambers: a first coating chamber and a second doping chamber; eliminating the need for two conventional deposition systems. To address the issue of boron source remaining on a substrate (which is reusable) after the second doped silicon layer is deposited on a silicon wafer carrier, potentially contaminating the corresponding intrinsic chamber and the deposited intrinsic layer in the next round of silicon wafers, the present disclosure performs a purge operation on the second doping chamber after the second doped silicon layer is deposited, effectively isolating the doping elements to prevent them from contaminating the subsequently deposited film layers. After purging, an isolation sacrificial layer is deposited in the second doping chamber. The isolation sacrificial layer directly covers the upper surface of the carrier and the film layer of the carrier silicon wafer, which can effectively isolate the doping elements in the second doped silicon layer on the carrier from contaminating the intrinsic hydrogenated amorphous silicon layer subsequently deposited on the carrier silicon wafer, thereby saving equipment and production costs while ensuring the coating effect; greatly saving equipment costs and simplifying the process. The present disclosure also cooperates with controlling the deposition temperature of the coating chamber to ensure a better passivation level, effectively avoiding the problem that the deposition temperature is too high and easily causes H overflow in the film layer, thereby increasing the density of dangling bonds and reducing the passivation function; and cooperates with controlling the deposition time to collaboratively ensure a better passivation level, effectively preventing the coating time from being too long and causing the doping source in the second doped silicon layer to diffuse into the intrinsic hydrogenated amorphous silicon layer, resulting in an increase in the impurity concentration of the intrinsic hydrogenated amorphous silicon layer and an increase in the interface state density, resulting in the failure of the passivation function.

[0045] In S8 of the present disclosure, the back side is cleaned on a single side. Since the film layer on the front side is not resistant to corrosion by the HF cleaning solution and does not need to be cleaned, the back side film layer needs to be cleaned in the corresponding semiconductor opening area due to the etching opening, and the film layer debris remaining in the corresponding semiconductor opening area is removed to keep the corresponding semiconductor opening area clean. Therefore, the single-sided cleaning method can not only protect the front side film layer, but also clean the corresponding semiconductor opening area on the back side, remove the isolation sacrificial layer on the back side and the coating layer around the edge of the silicon wafer (that is, the film layer that is coated on the back side when the front anti-reflection layer is coated).

[0046] Compared with the prior art CN101755072A and CN112267105A, the present disclosure has at least three major differences and advantages:

[0047] 1. After the second doped silicon layer is deposited, an isolation sacrificial layer is deposited on the carrier and its supporting silicon wafer membrane. The isolation sacrificial layer is primarily processed on the movable carrier that supports the silicon wafer to prevent the dopant source on the carrier from contaminating the intrinsic chamber subsequently deposited on the supporting silicon wafer. The degree of processing (such as processing time, deposited film thickness, and power) for depositing the isolation sacrificial layer on the carrier is significantly less than that of the processing chambers in CN101755072A and CN112267105A. This is because the area of ​​the carrier covered by the dopant source is much smaller than the area of ​​the chamber covered by the dopant source, and the area of ​​the carrier covered by the dopant source only accounts for about 1 / 16 of the chamber. Compared with the prior art processing chamber method, the method of depositing the isolation sacrificial layer on the carrier and its supporting silicon wafer membrane in the present disclosure has lower processing costs and a simpler process.

[0048] 2. The present disclosure performs an isolation sacrificial layer coating process on the carrier plate and its carrier film layer in the second doping chamber after the continuous coating process of the intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer is completed (the isolation sacrificial layer mainly covers the boron source in the non-silicon wafer area of ​​the isolation carrier plate to avoid contamination of the intrinsic film layer by the boron source on the carrier plate during the next round of coating). It is necessary to consider not only the isolation pollution source, but also whether the film layers on the silicon wafer are damaged. Therefore, the present disclosure specifically performs a gas washing operation on the second doping chamber before coating the isolation sacrificial layer to effectively isolate the doping pollution source, and cooperates with controlling the deposition temperature and deposition time within the aforementioned appropriate ranges, thereby performing a linkage setting, which can ensure the passivation performance, fill factor and battery conversion efficiency of each film layer while greatly reducing production costs and simplifying the process.

[0049] 3. The present invention performs an isolation sacrificial layer coating treatment on the carrier and its carrier film layer, which can form a protective layer on the second semiconductor layer of the back battery, thereby preventing it from being scratched or contaminated in the process steps S6 and S7, which is beneficial to improving the fill factor and conversion efficiency of the battery. At the same time, the isolation sacrificial layer on the second semiconductor layer is removed together with the conventional step of removing the front side coating layer in S8, so there is no need to add additional process steps.

[0050] In the optional scheme disclosed herein, the corrosion rate of the isolation sacrificial layer is controlled to be ≥1nm / s, and / or is basically equivalent to the corrosion rate of the surrounding plating layer, so as to achieve the purpose of joint removal. At the same time, it is more conducive to ensuring the passivation and conductivity properties, thereby facilitating the improvement of the opening voltage and fill factor, while taking into account the improvement of the battery conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0052] FIG1 is a schematic diagram of a conventional deposition process of the second semiconductor layer in a back contact cell;

[0053] FIG2 is a schematic diagram of the deposition process of the second semiconductor layer in the back contact battery of the present disclosure;

[0054] FIG3 is a schematic diagram of the process flow of the method for preparing a back-contact battery with back film continuous plating disclosed in the present invention.

[0055] Explanation of the accompanying symbols: 1. loading system, 2. preheating chamber, 3. first coating chamber, 4. cooling chamber, 5. unloading system, 6. first carrier, 7. second doping chamber, 8. second carrier, 9. carrier. DETAILED DESCRIPTION

[0056] In this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically specified.

[0057] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0058] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0059] The present disclosure provides a method for preparing a back-contact battery with back film continuous plating, comprising:

[0060] S01, forming a first semiconductor layer on the back side of the silicon wafer, and performing a first etching opening on the first semiconductor layer to form a second semiconductor opening region;

[0061] S5. Forming a second semiconductor layer and an isolation sacrificial layer in sequence on the back side of the silicon wafer obtained in S01, wherein the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer;

[0062] The second semiconductor layer and the isolation sacrificial layer are deposited in a deposition system by plate-type CVD continuous plating, and the process includes: placing the silicon wafer obtained in S01 on a carrier, first depositing an intrinsic hydrogenated amorphous silicon layer in a first coating chamber, then directly transferring the wafer to a second doping chamber in the current deposition system to continue depositing a second doped silicon layer, then performing a purge operation on the second doping chamber, and after purge, continuing to deposit the isolation sacrificial layer on the outer surface of the carrier and the corresponding film layer thereon in the second doping chamber; the deposition temperature of the intrinsic hydrogenated amorphous silicon layer is controlled at 190-220° C., and the deposition time is controlled at 1-2 minutes, the deposition temperatures of the second doped silicon layer and the isolation sacrificial layer are independently controlled at 150-200° C., and the sum of the deposition times of the second doped silicon layer and the isolation sacrificial layer is controlled at 1-4 minutes;

[0063] S6. forming a front passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer;

[0064] S7, performing a second etching to open the second semiconductor layer and the corresponding isolation sacrificial layer on the back side obtained in S6, to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0065] S8. Single-sided cleaning is performed on the back surface obtained in S7 to remove the isolation sacrificial layer and the wrap-around plating layer on the back surface obtained in S7.

[0066] The deposition temperature of the intrinsic hydrogenated amorphous silicon layer is controlled to be 190-220° C., for example, it can be 190° C., 200° C., 210° C., 220° C., or any range between any two points.

[0067] The deposition temperatures of the second doped silicon layer and the isolation sacrificial layer are independently controlled within a range of 150° C. to 200° C., for example, 150° C., 160° C., 170° C., 180° C., 190° C., or 200° C., or any range between any two values. The deposition temperatures of the second doped silicon layer and the isolation sacrificial layer may be the same or different.

[0068] The sum of the deposition times of the second doped silicon layer and the isolation sacrificial layer is controlled within 1-4 minutes, for example, it can be 1 minute, 1.5 minutes, 2 minutes, 2.5 minutes, 3 minutes, 3.5 minutes or 4 minutes, and the range between any two point values.

[0069] In some optional embodiments of the present disclosure, the deposition temperature ratio of the intrinsic hydrogenated amorphous silicon layer to the second doped silicon layer is controlled within a range of 1:0.68-1.05, for example, 1:0.68, 1:0.70, 1:0.73, 1:0.75, 1:0.80, 1:0.83, 1:0.85, 1:0.90, 1:0.93, 1:0.95, 1:1.00, 1:1.02, or 1:1.05, with 1:0.83-0.93 being optional. Using this optional deposition temperature ratio of the intrinsic hydrogenated amorphous silicon layer to the second doped silicon layer can control the overall deposition temperature, further improving the passivation effect of the battery.

[0070] In some optional embodiments of the present disclosure, the isolation sacrificial layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide. Silicon oxide may be silicon dioxide.

[0071] In some optional embodiments of the present disclosure, the conditions for depositing the isolation sacrificial layer include: a pressure of 80-300 Pa and a power supply of 0.2-2 kW. Suitable conditions for depositing the isolation sacrificial layer enable rapid film formation on the battery surface and facilitate control of film properties.

[0072] During the deposition of the isolation sacrificial layer, a corresponding gas source may be introduced according to the target material. In some optional embodiments of the present disclosure, the conditions for depositing the isolation sacrificial layer further include: introducing a mixed gas containing silane, a deposition element gas source, and hydrogen, wherein the deposition element gas source includes silicon dioxide or at least one of nitrous oxide and ammonia, the silane flow rate is 100-1500 sccm, the deposition element gas flow rate is 100-1500 sccm, and the hydrogen flow rate is 5000-10000 sccm.

[0073] It can be understood that the present disclosure states that "first depositing the intrinsic hydrogenated amorphous silicon layer in the first coating chamber, and then directly transferring it to the second doping chamber in the current deposition system to continue depositing the second doped silicon layer" means that after depositing the intrinsic hydrogenated amorphous silicon layer, the cavity is not broken and the carrier is not replaced, but it directly enters the second doping chamber to continue depositing the second doped silicon layer.

[0074] In some optional embodiments of the present disclosure, the deposition system includes a loading system, a preheating chamber, a first coating chamber, a second doping chamber, a cooling chamber, and a discharge system. By configuring the first coating chamber and the second doping chamber within a single deposition system for continuous coating, and by controlling specific key process parameters (including deposition temperature and time), the process can be simplified, costs can be reduced, and battery performance can be guaranteed.

[0075] After the silicon wafer is loaded onto the carrier plate of the present invention, it sequentially enters the loading system, preheating chamber, first coating chamber, second doping chamber, cooling chamber and unloading system to realize the continuous plating process.

[0076] The carrier plate disclosed herein continuously deposits film layers in a deposition system and can be regularly maintained and cleaned.

[0077] In some optional embodiments of the present disclosure, the deposition time of the isolation sacrificial layer is 0.5-1.5 minutes, and the deposition time of the second doped silicon layer is 1-2.5 minutes. Suitable deposition times further effectively reduce the possibility of dopant sources in the second doped silicon layer diffusing into the intrinsic hydrogenated amorphous silicon layer, thereby reducing the passivation function, thereby further improving the passivation performance to a higher level.

[0078] In some optional embodiments of the present disclosure, the deposition conditions of the intrinsic hydrogenated amorphous silicon layer include: a mass flow rate of silane of 500-2000 sccm, a mass flow rate of hydrogen of 3000-10000 sccm, a pressure of 80-400 Pa, a power supply of 0.5-15 kW, and a time of 1-2 min.

[0079] In some optional embodiments of the present disclosure, the deposition conditions of the second doped silicon layer include: a mass flow rate of silane of 500-2000 sccm, a mass flow rate of borane of 300-1000 sccm, a mass flow rate of hydrogen of 3000-20000 sccm, a pressure of 80-500 Pa, and a power supply of 0.5-20 kW.

[0080] The second doped silicon layer may be a doped microcrystalline silicon layer or an amorphous silicon layer.

[0081] The CVD continuous plating described in the present disclosure may be plate-type CVD continuous plating.

[0082] In some optional embodiments of the present disclosure, the thickness ratio of the intrinsic hydrogenated amorphous silicon layer, the second doped silicon layer, and the isolation sacrificial layer is 1:0.75-4.5:0.375-2, optionally 1:0.75-2.50:0.375-1, or optionally 1:0.75-2.30:0.375-0.960. This optimal ratio of specific film thicknesses maintains optimal film performance while providing isolation, further improving overall battery performance.

[0083] In some optional embodiments of the present disclosure, the intrinsic hydrogenated amorphous silicon layer has a thickness of 4-8 nm, optionally 4-7 nm, the second doped silicon layer has a thickness of 6-19 nm, optionally 6-13 nm, and the isolation sacrificial layer has a thickness of 3-8 nm, optionally 3-6 nm. Using layers of appropriate thickness can avoid the risk of film delamination that may occur due to excessive film thickness.

[0084] In some optional embodiments of the present disclosure, the S5 gas washing operation includes a process of repeated inflation and exhaust cycles, wherein inflation is to introduce an inert gas into the second doping chamber, and the number of inflation and exhaust cycles repeated is ≥1.

[0085] Optionally, the duration of the gas washing operation is 30s-150s, optionally 80-150s, the gas filling time is 5s-15s, and the gas extraction time is until the gas in the second doping chamber is pumped to a vacuum pressure of 10 -1 Appropriate purge time can reduce the residual pollution sources during doping and is more conducive to isolation effect.

[0086] Optionally, the flow rate of the inert gas introduced during inflation is 1000 sccm-10000 sccm.

[0087] The inert gas disclosed herein may be, for example, a mixture of one or more inert gases such as nitrogen, argon or neon.

[0088] In some optional embodiments of the present disclosure, during the single-sided cleaning described in S8, the etching rate of the isolation sacrificial layer is ≥1 nm / s, and may be 1-5 nm / s. A suitably high etching rate for the isolation sacrificial layer can achieve the goal of substantially simultaneous removal of the surrounding plating layer, while also being more effective in reducing etching and damage to the functional film layer (non-isolation sacrificial layer) by the corrosive solution.

[0089] The corrosion rate disclosed herein is obtained by measuring the film thickness before and after corrosion using an ellipsometer, and dividing the difference in film thickness before and after corrosion by the corrosion time.

[0090] In some optional embodiments of the present disclosure, the absolute difference in corrosion rate between the isolation sacrificial layer and the surrounding plating layer is in the range of 0.1-1.8 nm / s, or optionally 0.1-0.5 nm / s. A suitably high corrosion rate for the isolation sacrificial layer allows for substantially simultaneous removal of the surrounding plating layer, avoiding increased processing time and costs, while also preventing the corrosive solution from etching and damaging the functional film layer.

[0091] In some optional embodiments of the present disclosure, the conditions for the single-side cleaning in S8 include: treating the back side with a mixed solution of hydrofluoric acid and ultrapure water with a mass concentration of 2%-5%, and the treatment time is 2-15 minutes.

[0092] The corrosion rate of the isolation sacrificial layer is adjusted by adjusting the carbon dioxide doping level and deposition power during the isolation sacrificial layer preparation process. By adjusting the properties of the isolation sacrificial layer to control the corrosion rate, the isolation sacrificial layer is removed along with the conventional cleaning process for removing the plating layer. This avoids unnecessary damage to other functional layers on the back surface caused by adjusting the cleaning process, avoids unnecessary interference in the single-sided cleaning process, and minimizes the impact on the process. The corrosion rate of the plating layer is adjusted by adjusting the deposition power during the preparation of the corresponding semiconductor layer.

[0093] The single-sided cleaning method described in the present disclosure can be achieved, for example, by a conventional chain cleaning process through a chain roller liquid method. The present disclosure has no limitation on this, as long as single-sided cleaning can be achieved.

[0094] In some optional embodiments of the present disclosure, the first semiconductor layer includes a tunneling silicon oxide layer and a first doped polysilicon layer, and one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type.

[0095] Optionally, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration is 10 20 cm -3 -10 21 cm -3 .

[0096] Optionally, the effective doping concentration of the second doped silicon layer is 10 19 cm -3 -10 20 cm -3 .

[0097] In some optional embodiments of the present disclosure, S01, forming a first semiconductor layer on the back side of a silicon wafer, and performing a first etching opening on the first semiconductor layer to form a second semiconductor opening region; comprising:

[0098] S1, provide silicon wafers;

[0099] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer;

[0100] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region;

[0101] S4. Then, texturing and cleaning are performed, and the mask layer on the back of the silicon wafer is optionally removed during texturing and cleaning.

[0102] The silicon wafer disclosed herein may be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer. Optionally, the silicon wafer may be N-type. S1 may include conventional polishing and cleaning steps based on actual needs.

[0103] The type and thickness of the mask layer disclosed herein can refer to prior art. For example, the mask layer can be at least one of silicon nitride, silicon oxide, silicon oxynitride, or nitrogen-containing polysilicon. For example, the thickness of the mask layer is 40-90 nm.

[0104] In the present disclosure, the method for forming the first semiconductor layer and the mask layer can be carried out with reference to the corresponding method in the prior art. For example, in some specific embodiments, the first semiconductor layer and the mask layer can be formed by sequentially depositing and high-temperature annealing in a tubular polysilicon deposition furnace, and the deposition temperature is 400-500°C; the high-temperature annealing process includes: introducing nitrogen gas, the nitrogen flow rate is 5000-15000sccm, the annealing temperature is 850-950°C, the pressure is 1000-10000Pa, and the time is 40-60min.

[0105] Optionally, in some specific embodiments, when depositing the tunneling silicon oxide layer, the flow rate of the nitrous oxide is 8000-12000 sccm, the pressure is 100-200 Pa, the power is 3-20 kW, and the time is 20-100 s.

[0106] Optionally, in some specific embodiments, when depositing the first doped polysilicon layer, the flow rate of silane is 1000-3000 sccm, the flow rate of the mixed gas of hydrogen and the doping element source is 1000-4000 sccm, the flow rate of hydrogen is 7000-9000 sccm, the pressure is 200-800 Pa, the power is 5-20 kW, and the time is 800-1300 s. Optionally, when the doping element source gas is a phosphorus source, the flow rate of the mixed gas is 1000-2500 sccm, and the pressure is controlled at 400-500 Pa; when the doping element source gas is a boron source, the flow rate of the mixed gas is 2000-4000 sccm, and the pressure is controlled at 200-800 Pa.

[0107] Optionally, in some specific embodiments, when depositing the mask layer, the flow rate of silane is 1000-2000 sccm, the flow rate of nitrogen is 2000-5000 sccm, the pressure is 200-300 Pa, the power is 3-20 kW, and the time is 100-300 s.

[0108] In the present disclosure, the first etching opening S3 and the second etching opening S7 can be formed by laser or mask etching, as long as the corresponding semiconductor opening area can be formed. Optionally, the laser can be ultraviolet or green laser with a pulse width of less than 10ns.

[0109] The widths of the first semiconductor opening region and the second semiconductor opening region may refer to the ranges of corresponding semiconductor opening regions in the prior art. For example, the width of the first semiconductor opening region may be 400-800 μm, and the width of the second semiconductor opening region may be 100-250 μm.

[0110] The mask layer in the texturing cleaning described in S4 of the present disclosure can be removed or not removed according to actual needs.

[0111] The conditions for the texturing and cleaning described in S4 of the present disclosure can refer to those in the prior art, including two processes: texturing and cleaning. For example, the texturing conditions include: the texturing time is 8-30min, and the texturing temperature is 75℃-85℃. For example, the texturing liquid used for the texturing cleaning can refer to the texturing liquid in the prior art, for example, the texturing liquid can be a mixture of alkali (such as potassium hydroxide or sodium hydroxide), texturing additives and water, wherein the mass percentage of alkali is 1%-5%, and the mass percentage of texturing additives is 0.5%-1%. Texturing additives can be commercially available. For example, the cleaning can use a conventional cleaning solution, such as an acid solution containing HF, the mass percentage of HF acid is 0.5%-5%, and the mass percentage of deionized water is 95%-99.5%. The cleaning conditions include: the processing temperature is 20℃-30℃, and the removal time is 60-300s.

[0112] The formation method, type, and thickness of the front passivation layer and anti-reflection layer described in S6 of the present disclosure can refer to the existing technology. For example, the formation method can adopt PECVD or hot-wire method. For example, the front passivation layer can include a stack of an intrinsic hydrogenated amorphous silicon layer and a doped amorphous silicon layer, or a stack of an intrinsic hydrogenated amorphous silicon layer and a doped microcrystalline silicon layer. For example, the anti-reflection layer is one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.

[0113] In some optional embodiments of the present disclosure, the method for preparing the back-contact battery with back film continuous plating further includes:

[0114] S9, depositing a conductive film layer on the back side of the silicon wafer obtained in S8;

[0115] S10, performing a third etching opening on the conductive film layer on the back side obtained in S9 to form an insulating groove isolating the first semiconductor opening region and the second semiconductor opening region;

[0116] S11 , forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S10 .

[0117] The conductive film layer described herein can be formed using physical vapor deposition (PVD) or activated plasma deposition (RPD). The material and thickness of the conductive film layer can refer to existing technologies. For example, the thickness of the conductive film layer can be 40-80 nm. For example, the conductive film layer can be made of an indium oxide-based film doped with at least one of tin, tungsten, titanium, and zinc, or a zinc oxide-based film doped with aluminum and / or boron.

[0118] The third etching opening described in the present disclosure can be etched on the back side of the silicon wafer using mask etching or laser etching to form an insulating trench. After etching, the resistance between the first semiconductor layer and the second semiconductor layer is greater than 1 kΩ. The width of the insulating trench can be, for example, 20-100 μm.

[0119] The metal electrodes can be formed by, for example, screen printing technology.

[0120] The embodiments of the present disclosure are described in detail below, which are exemplary and only used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0121] Example 1

[0122] A method for preparing a back-contact battery with back film continuous plating, as shown in FIG3 , comprises:

[0123] S01 includes:

[0124] S1, double-sided polishing of silicon wafers:

[0125] Double-sided polishing and cleaning of N-type single crystal silicon wafers, wherein the silicon wafers are Czochralski single crystal silicon wafers.

[0126] S2. Forming a first semiconductor layer and a mask layer on the back side of the silicon wafer:

[0127] The first semiconductor layer includes a tunneling silicon oxide layer and an N-type first doped polysilicon layer. The mask layer is silicon nitride. The thickness of the tunneling silicon oxide layer is 1.5 nm, the thickness of the first doped polysilicon layer is 100 nm, and the effective doping concentration is 5×10 20 cm -3The thickness of the mask layer is 70nm. The tunneling silicon oxide layer, the first doped polysilicon layer, and the mask layer are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace. The deposition temperature is 450°C. When depositing the tunneling silicon oxide layer, the nitrous oxide flow rate is 8000sccm, the pressure is 150Pa, the power is 10kW, and the time is 40s. When depositing the first doped polysilicon layer, the silane flow rate is 2000sccm, the hydrogen-carrying phosphine (ratio 2% PH3:98% H2) flow rate is 2500sccm, the hydrogen flow rate is 8000sccm, the pressure is 450Pa, the power is 10kW, and the time is 1000s. When depositing silicon nitride, the silane flow rate is 1500sccm, the nitrogen flow rate is 3000sccm, the pressure is 200Pa, the power is 10kW, and the time is 800s. Then, high-temperature annealing is performed. Specifically, nitrogen gas is introduced with a flow rate of 10,000 sccm, an annealing temperature of 900° C., a pressure of 5,000 Pa, and a time of 50 minutes.

[0128] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region;

[0129] The first etching opening is performed by laser, as long as the second semiconductor opening region can be formed. The laser is ultraviolet laser with a pulse width of 5ns. The width of the second semiconductor opening region is 500μm.

[0130] S4, performing texturing and cleaning on the semiconductor opening areas on the front and back sides of the silicon wafer:

[0131] The semiconductor openings on the front and back sides of the silicon wafer were cleaned and texturized using a mixture of potassium hydroxide, a texturizing additive, and water. The potassium hydroxide content was 3% by weight, and the texturizing additive content was 0.5% by weight. The texturizing process lasted 10 minutes and was performed at a temperature of 80°C.

[0132] During the front texturing process, the mask layer on the back of the silicon wafer is also removed at the same time through the final cleaning solution. The cleaning solution used to remove the mask layer is HF acid solution, with a mass percentage of 0.5% HF acid and a mass percentage of 99.5% deionized water. The processing temperature is 25°C and the removal time is 100s.

[0133] S5, forming a second semiconductor layer and an isolation sacrificial layer on the back side of the silicon wafer obtained in S01;

[0134] The second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a P-type second doped silicon layer (specifically, a doped amorphous silicon layer). The second semiconductor layer is achieved by plate-type CVD continuous plating and is deposited in a deposition system. Specifically, as shown in FIG2 , the silicon wafer obtained in S01 is first placed on a carrier 9, and then enters the preheating chamber 2 for preheating via the loading system 1. Thereafter, the silicon wafer enters the first coating chamber 3 for deposition of the intrinsic hydrogenated amorphous silicon layer. After the intrinsic hydrogenated amorphous silicon layer is deposited, the wafer is transferred to the second doping chamber 7 in the original deposition system to continue deposition of the P-type second doped silicon layer without breaking the air or replacing the carrier 9. At the same time, after the second doped silicon layer is deposited, an isolation sacrificial layer is further deposited in the second doping cavity 7. The isolation sacrificial layer is silicon dioxide. The isolation sacrificial layer directly covers the upper surface of the carrier, the silicon wafer and the upper film layer thereof, which can effectively isolate the doping elements on the carrier 9 from contaminating the intrinsic hydrogenated amorphous silicon layer. The thickness of the intrinsic hydrogenated amorphous silicon layer is 7nm, the thickness of the second doped silicon layer is 13nm, and the effective doping concentration is 5.6×10 19 cm -3 , the thickness of the isolation sacrificial layer is 5nm.

[0135] The intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer are deposited in a continuous plating manner. The temperature of the intrinsic hydrogenated amorphous silicon layer is controlled at 200°C, the temperature of the second doped silicon layer is controlled at 180°C, and the process temperature ratio of the intrinsic hydrogenated amorphous silicon layer to the second doped silicon layer should be controlled at 1:0.9; the deposition conditions of the intrinsic hydrogenated amorphous silicon layer include: the mass flow rate of silane is 1000sccm, the mass flow rate of hydrogen is 6000sccm, the pressure is 100Pa, the power supply is 8kW, and the time is 2min; the deposition conditions of the second doped silicon layer include: the mass flow rate of silane is 1000sccm, the mass flow rate of borane is 600sccm, the mass flow rate of hydrogen is 6000sccm, the pressure is 100Pa, the power supply is 10kW, and the time is 2.5min.

[0136] The intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer are deposited in a continuous deposition manner. After the second doped silicon layer is deposited, a purge operation is performed by repeatedly filling and exhausting the gas, and then a layer of isolation sacrificial layer is deposited. The purge time lasts for 100 seconds. The purge operation is to introduce nitrogen into the second doping chamber 7 at a flow rate of 5000 sccm. The purge time is 10 seconds and the exhaust time is to evacuate the gas in the second doping chamber 7 to a vacuum pressure of 10 -1 Pa, the inflation and exhaust cycle washing operation is performed three times; the purpose of the inflation and exhaust cycle washing is to remove the residual doping gas in the second doping cavity 7 and to clean the cavity for the subsequent deposition of the isolation sacrificial layer.

[0137] When depositing the isolation sacrificial layer (which is a silicon dioxide doping source), the temperature is controlled at 180°C, and silane, carbon dioxide and hydrogen gases are introduced into the second doping chamber 7. The flow rate of silane is 1000sccm, the flow rate of carbon dioxide is 800sccm, and the flow rate of hydrogen is 6000sccm. The control pressure is 100Pa, the power supply is 1kW, and the deposition time is 85s.

[0138] S6. forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0139] The front passivation layer and the anti-reflection layer are formed by PECVD. The front passivation layer includes an intrinsic hydrogenated amorphous silicon layer and an N-type doped amorphous silicon layer. The anti-reflection layer is silicon nitride.

[0140] S7, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region;

[0141] The second etching process uses a laser to etch away the second semiconductor layer above the first semiconductor layer, forming a first semiconductor opening region spaced apart from the second semiconductor opening region. The laser is ultraviolet with a pulse width of 2 ns. The width of the formed second semiconductor opening region is 200 μm.

[0142] S8, performing single-side cleaning on the back surface obtained in S7 to remove the isolation sacrificial layer and the wrap-around plating layer on the back surface of the silicon wafer;

[0143] A single-sided cleaning method is used, specifically a chain cleaning process is used to remove the isolation sacrificial layer on the back surface and the plating layer caused by the front anti-reflection layer on a single side by a chain roller liquid method. The back side is treated with a HF acid solution of 5% by mass concentration of hydrofluoric acid (HF) and ultrapure water (DI-Water) for 10 minutes. The isolation sacrificial layer has a corrosion rate of 3nm / s in a 5wt% HF acid solution, and the plating layer has a corrosion rate of 2.8nm / s. Controlling the corrosion rate of the isolation sacrificial layer can ensure a high level of passivation performance and prevent the removal of the isolation sacrificial layer from taking too long, resulting in poor passivation performance.

[0144] S9, depositing a conductive film layer on the back surface of the substrate obtained in S8;

[0145] A transparent conductive film layer is deposited on the back of the silicon wafer using physical vapor deposition (PVD) technology. The transparent conductive film layer has a thickness of 60 nm and is made of a tin-doped indium oxide-based film.

[0146] S10, etching an opening on the back side of the silicon wafer for the third time to form an insulating trench;

[0147] Using mask etching, a third etching opening is made on the back of the silicon wafer to form an insulating trench between the first semiconductor and the second semiconductor. The insulating trench is 50 μm wide, and the resistance between the first semiconductor layer and the second semiconductor layer after etching is greater than 1 kΩ.

[0148] S11, forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer respectively:

[0149] Metal electrodes are respectively formed on the surfaces of the first semiconductor opening area and the second semiconductor opening area on the back side of the silicon wafer by using screen printing technology.

[0150] Example 2

[0151] The method of Example 1 was followed, except that the deposition temperature of the second doped silicon layer was adjusted to 170°C. The ratio of the deposition temperature of the intrinsic hydrogenated amorphous silicon layer to the second doped silicon layer was calculated to be 1:0.85. Under this scheme, the thickness of the second doped silicon layer was 10.5 nm and the effective doping concentration was 4.6×10 19 cm -3 .

[0152] Example 3

[0153] The method of Example 1 was followed, except that the deposition temperature of the second doped silicon layer was adjusted to 190°C. The ratio of the deposition temperature of the intrinsic hydrogenated amorphous silicon layer to the second doped silicon layer was calculated to be 1:0.95. Under this scheme, the thickness of the second doped silicon layer was 15 nm and the effective doping concentration was 6.1×10 19 cm -3 .

[0154] Example 4

[0155] The method of Example 1 was followed, except that the deposition temperature of the intrinsic hydrogenated amorphous silicon layer was adjusted to 220°C, so that the deposition temperature ratio of the intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer was controlled to be 1:0.818. In this solution, the thickness of the intrinsic hydrogenated amorphous silicon layer was 8 nm.

[0156] Example 5

[0157] The method of Example 1 was followed, except that the deposition time of the second doped silicon layer was 135s. Under this scheme, the thickness of the second doped silicon layer was 14nm and the effective doping concentration was 5.5×10 19 cm -3 .

[0158] Example 6

[0159] The method of Example 1 is referred to, except that the thickness of the isolation sacrificial layer is adjusted to 8 nm. The process parameter that needs to be adjusted to meet this thickness is to extend the deposition time of the isolation sacrificial layer by 65%. In this case, the ratio of the thickness of the intrinsic hydrogenated amorphous silicon layer to the isolation sacrificial layer is 1:1.14.

[0160] Example 7

[0161] The method of Example 1 is referred to, except that the thickness of the second doped silicon layer is adjusted to 19 nm. The process parameter that needs to be adjusted to meet this thickness is to extend the deposition time of the second doped silicon layer by 30%. In this case, the thickness ratio of the intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer is calculated to be 1:2.7.

[0162] Example 8

[0163] The method of Example 1 is referred to, except that the corrosion rate of the isolation sacrificial layer is adjusted to 1 nm / s in S8. The process parameters that need to be adjusted to meet this corrosion rate are: reducing the doping flow of carbon dioxide by 60%, and the thickness of the isolation sacrificial layer is 5 nm. In this case, the absolute value of the difference in corrosion rate between the isolation sacrificial layer and the surrounding coating is 1.8 nm / s.

[0164] Example 9

[0165] The method of Example 1 is carried out, except that a conventional heterojunction passivation structure is adopted. Specifically, the first semiconductor layer comprises an intrinsic amorphous silicon layer with a thickness of 6 nm and a first doped amorphous silicon layer (with a thickness of 8 nm and an effective doping concentration of 2×10 20 cm -3 ).

[0166] Example 10

[0167] The method of Example 1 is referred to, except that the key parameters of the scrubbing operation in S5 are different, specifically: the scrubbing time lasts 50 seconds, the number of the inflation and exhaust cyclic scrubbing operations is 1, and the other parameters are the same.

[0168] Comparative Example 1

[0169] The method of Example 1 is referred to, except that, in S5, a conventional method is used to deposit the second semiconductor layer, and no isolation sacrificial layer is deposited. Specifically, S5 includes:

[0170] The intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer (specifically amorphous) are formed by coating separately using two sets of plate-type PECVD deposition systems, as shown in Figure 1. That is, each uses an independent deposition chamber and an independent carrier for holding silicon wafers. That is, the deposition of the intrinsic hydrogenated amorphous silicon layer is carried out in the first deposition system (placed on the first carrier 6 and passed through the loading system 1, preheating chamber 2, first coating chamber 3, cooling chamber 4 and unloading system 5 in sequence), and the deposition of the second doped silicon layer is carried out in the second deposition system (placed on the second carrier 8 and passed through the loading system 1, preheating chamber 2, second doping chamber 7, cooling chamber 4 and unloading system 5 in sequence). The deposition temperatures of the intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer are 210°C and 190°C, respectively. The thickness of the intrinsic hydrogenated amorphous silicon layer is 7nm, the thickness of the second doped silicon layer is 10nm, and the effective doping concentration is 5.6×10 19 cm -3 .

[0171] Comparative Example 2

[0172] The method of Example 1 is referred to, except that no isolation sacrificial layer is deposited in S5, and the isolation sacrificial layer on the back side obtained in S7 does not need to be removed in S8.

[0173] Comparative Example 3

[0174] The method of Example 1 is referred to, except that the deposition temperature of the intrinsic hydrogenated amorphous silicon layer is 180° C. In this solution, the thickness of the intrinsic hydrogenated amorphous silicon layer is 4 nm.

[0175] Comparative Example 4

[0176] The method of Example 1 was followed, except that the deposition time of the second doped silicon layer was 3 min. Under this scheme, the thickness of the second doped silicon layer was 17 nm and the effective doping concentration was 8.3×10 19 cm -3 .

[0177] Comparative Example 5

[0178] The method of Example 1 is followed, except that the deposition time of the intrinsic hydrogenated amorphous silicon layer is 0.53 min. In this solution, the thickness of the intrinsic hydrogenated amorphous silicon layer is 3 nm.

[0179] Comparative Example 6

[0180] The method of Example 1 is referred to, except that no gas scrubbing operation is performed in S5.

[0181] Test Case

[0182] The back-contact cells obtained in the above examples and comparative examples were subjected to performance testing, and the results are shown in Table 1. The performance indicators of each example and comparative example were converted using Example 1 as a reference benchmark. The data for Example 1 is normalized to a reference of 1, and the other examples were converted based on Example 1. For example, the production cost of Comparative Example 1 is divided by the production cost of Example 1, which is 2.1. During the normalization process, the unit of open-circuit voltage (Voc) is V, the unit of fill factor is %, and the unit of cell conversion efficiency is %.

[0183] Table 1

[0184] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present disclosure can realize the use of only one set of deposition systems, greatly saving equipment costs and simplifying the process, effectively preventing pollution during continuous plating, and maintaining better battery performance, especially excellent passivation performance, fill factor and battery conversion efficiency, which is conducive to large-scale production implementation.

[0185] Optionally, according to Examples 1 and 2-10, it can be seen that the use of the optional temperature conditions and doping concentrations disclosed in the present invention in combination with other process parameters can maintain a higher battery conversion efficiency and is more conducive to improving product competitiveness.

[0186] The above describes in detail the optional embodiments of the present disclosure, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure can be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as the contents disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0187] The present disclosure provides a method for preparing a back-contact battery with continuous back-film plating, which can achieve the goal of only sharing one deposition system, greatly saving equipment costs and simplifying the process. It can effectively prevent pollution during continuous plating while maintaining relatively good battery performance, especially excellent passivation performance, fill factor and battery conversion efficiency.

Claims

1. A method for preparing a back contact battery with back film continuous plating, comprising: S01. Forming a first semiconductor layer on the back side of a silicon wafer, and performing a first etching opening on the first semiconductor layer to form a second semiconductor opening region; characterized in that it further comprises: S5, forming a second semiconductor layer and an isolation sacrificial layer in sequence on the back side of the silicon wafer obtained in S01, wherein the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer; The second semiconductor layer and the isolation sacrificial layer are deposited in a deposition system by plate-type CVD continuous plating, and the process includes: placing the silicon wafer obtained in S01 on a carrier, first depositing an intrinsic hydrogenated amorphous silicon layer in a first coating chamber, then directly transferring the wafer to a second doping chamber in the current deposition system to continue depositing a second doped silicon layer, then performing a purge operation on the second doping chamber, and after purge, continuing to deposit the isolation sacrificial layer on the outer surface of the carrier and the corresponding film layer thereon in the second doping chamber; the deposition temperature of the intrinsic hydrogenated amorphous silicon layer is controlled at 190-220° C., and the deposition time is controlled at 1-2 minutes, the deposition temperatures of the second doped silicon layer and the isolation sacrificial layer are independently controlled at 150-200° C., and the sum of the deposition times of the second doped silicon layer and the isolation sacrificial layer is controlled at 1-4 minutes; S6. forming a front passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer; S7, performing a second etching to open the second semiconductor layer and the corresponding isolation sacrificial layer on the back side obtained in S6, to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S8. Single-sided cleaning is performed on the back surface obtained in S7 to remove the isolation sacrificial layer and the wrap-around plating layer on the back surface obtained in S7.

2. The method for preparing a back contact battery with back film continuous plating according to claim 1, characterized in that: The ratio of the deposition temperature of the intrinsic hydrogenated amorphous silicon layer and the second doped silicon layer is controlled at 1:0.68-1.05; and / or, The isolation sacrificial layer is at least one of silicon nitride, silicon oxynitride and silicon oxide.

3. The method for preparing a back contact battery with back film continuous plating according to claim 1 or 2, characterized in that: The conditions for depositing the isolation sacrificial layer include: a pressure of 80-300 Pa and a power supply of 0.2-2 kW; and / or, The conditions for depositing the isolation sacrificial layer also include: introducing a mixed gas containing silane, a deposition element gas source and hydrogen, the deposition element gas source includes silicon dioxide or at least one of nitrous oxide and ammonia, the flow rate of silane is 100-1500sccm, the flow rate of the deposition element gas source is 100-1500sccm, and the flow rate of hydrogen is 5000-10000sccm.

4. The method for preparing a back contact battery with back film continuous plating according to any one of claims 1 to 3, characterized in that: The deposition system includes a loading system, a preheating chamber, a first coating chamber, a second doping chamber, a cooling chamber, and a unloading system; the carrier plate carries the silicon wafer and enters the loading system, the preheating chamber, the first coating chamber, the second doping chamber, the cooling chamber, and the unloading system in sequence; and / or, The deposition time of the isolation sacrificial layer is 0.5-1.5 minutes, and the deposition time of the second doped silicon layer is 1-2.5 minutes.

5. The method for preparing a back contact battery with back film continuous plating according to any one of claims 1 to 4, characterized in that: The deposition conditions of the intrinsic hydrogenated amorphous silicon layer include: a mass flow rate of silane of 500-2000 sccm, a mass flow rate of hydrogen of 3000-10000 sccm, a pressure of 80-400 Pa, a power supply of 0.5-15 kW, and a deposition time of 1-2 min; and / or, The deposition conditions of the second doped silicon layer include: a mass flow rate of silane of 500-2000 sccm, a mass flow rate of borane of 300-1000 sccm, a mass flow rate of hydrogen of 3000-20000 sccm, a pressure of 80-500 Pa, and a power supply of 0.5-20 kW.

6. The method for preparing a back contact battery with back film continuous plating according to any one of claims 1 to 5, characterized in that: The thickness ratio of the intrinsic hydrogenated amorphous silicon layer, the second doped silicon layer and the isolation sacrificial layer is 1:0.75-4.5:0.375-2; and / or, The thickness of the intrinsic hydrogenated amorphous silicon layer is 4-8 nm, the thickness of the second doped silicon layer is 6-19 nm, and the thickness of the isolation sacrificial layer is 3-8 nm.

7. The method for preparing a back contact battery with back film continuous plating according to any one of claims 1 to 6, characterized in that: The gas washing operation S5 includes a process of repeated inflation and exhaust cycles, wherein the inflation is to introduce an inert gas into the second doping chamber, and the number of repeated inflation and exhaust cycles is ≥1.

8. The method for preparing a back contact battery with back film continuous plating according to claim 7, characterized in that: The duration of the gas washing operation is 30s-150s, the gas filling time is 5s-15s, and the gas extraction time is until the gas in the second doping chamber is pumped to a vacuum pressure of 10 -1 Below Pa; and / or, The flow rate of the inert gas introduced during inflation is 1000 sccm-10000 sccm.

9. The method for preparing a back contact battery with back film continuous plating according to claim 1, characterized in that: In the single-sided cleaning described in S8, the corrosion rate of the isolation sacrificial layer is ≥1 nm / s, and / or the absolute value of the difference in corrosion rate between the isolation sacrificial layer and the surrounding plating layer is 0.1-1.8 nm / s.

10. The method for preparing a back contact battery with continuous back film plating according to claim 1 or 9, characterized in that: The conditions for the single-side cleaning in S8 include: treating the back surface with a mixed solution of hydrofluoric acid and ultrapure water with a mass concentration of 2% to 5%, and the treatment time is 2 to 15 minutes.

11. The method for preparing a back contact battery with back film continuous plating according to any one of claims 1 to 10, characterized in that: The first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, wherein one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type; wherein the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration is 10 20 cm -3 -10 21 cm -3 , the effective doping concentration of the second doped silicon layer is 10 19 cm -3 -10 20 cm -3 .

12. The method for preparing a back contact battery with back film continuous plating according to any one of claims 1 to 11, characterized in that: S01, forming a first semiconductor layer on the back side of the silicon wafer, and performing a first etching opening on the first semiconductor layer to form a second semiconductor opening region; comprising: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region; S4, then performing texturing cleaning, and optionally removing the mask layer on the back side of the silicon wafer during texturing cleaning; and / or, The method for preparing the back contact battery with back film continuous plating further includes: S9, depositing a conductive film layer on the back side of the silicon wafer obtained in S8; S10, performing a third etching opening on the conductive film layer on the back side obtained in S9 to form an insulating groove isolating the first semiconductor opening region and the second semiconductor opening region; S11 , forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S10 .

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