Driving backboard, manufacturing method thereof, display panel and display device

Abstract

The invention provides a driving backboard and a manufacturing method thereof, a display panel and a display device, and relates to the technical field of display. The driving backboard comprises a substrate, an active layer, a first gate insulation layer, a first gate metal layer, a dielectric layer and a source-drain metal layer, the active layer comprises a driving channel region of a driving transistor, the first gate metal layer comprises a first conductive part, and the first conductive part and the driving channel region have an overlapping region; the dielectric layer is provided with a first via hole, and the distance between the orthographic projection of the first via hole and the orthographic projection of the driving channel region is smaller than or equal to 0.5 micron; the source-drain metal layer comprises a first connecting piece, and the first connecting piece is connected with the first conductive part through a first via hole. In the embodiment of the invention, by adjusting the plane distance between the first via hole connected with the first conductive part and the driving channel region of the driving transistor, the sub-threshold swing of the driving transistor can be increased, so that the gray scale control capability of the pixel circuit can be improved.

Description

[0001] The present disclosure is a divisional application. The application number of the original application is 202310200220.8, the application date is February 28, 2023, and the name of the invention is “Driving backplane and its manufacturing method, display panel, and display device”. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a driving backplane and a manufacturing method thereof, a display panel, and a display device. Background Art

[0003] With the rapid development of display technology, users have higher and higher requirements for the resolution of display devices. As the resolution of display devices increases and the light-emitting efficiency of light-emitting devices of display devices increases, the pixel current of the pixel circuit that drives the light-emitting devices to emit light continues to decrease, which results in insufficient grayscale control capability of transistors in the pixel circuit, resulting in poor display effect of the display device.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a driving backplane and a manufacturing method thereof, a display panel, and a display device, which can improve the grayscale control capability and thus improve the display effect.

[0006] According to one aspect of the present disclosure, there is provided a driving backplane, the driving backplane comprising a plurality of pixel circuits, the pixel circuits comprising driving transistors, and the driving backplane comprising:

[0007] substrate substrate;

[0008] An active layer, located on one side of the base substrate, and including a driving active portion of the driving transistor, wherein the driving active portion has a driving channel region;

[0009] A first gate insulating layer, located on a side of the active layer away from the substrate and at least covering the driving active portion;

[0010] A first gate metal layer is located on a side of the first gate insulating layer away from the base substrate and includes a first conductive portion, wherein the first conductive portion and the driving channel region have an overlapping area;

[0011] a dielectric layer, located on a side of the first gate metal layer away from the base substrate, and having a first via hole penetrating to the first conductive portion, wherein a distance between an orthographic projection of the first via hole on the base substrate and an orthographic projection of the driving channel region on the base substrate is less than or equal to 0.5 micrometers;

[0012] A source-drain metal layer, located on a side of the dielectric layer away from the substrate, and includes a first connection piece, and the first connection piece is connected to the first conductive portion through the first via hole.

[0013] For the driving backplane according to any one of the present disclosures, a positive projection of the first via hole on the substrate overlaps with a positive projection of the driving channel region on the substrate.

[0014] For the driving backplane according to any one of the present disclosures, a partial edge of a positive projection of the first via hole on the substrate coincides with a partial edge of a positive projection of the driving channel region on the substrate.

[0015] For the driving backplane according to any one of the present disclosures, a center point of a positive projection of the first via hole on the substrate coincides with a midpoint in a width direction of a positive projection of the driving channel region on the substrate.

[0016] For the driving backplane according to any one of the present disclosures, a positive projection of the first via hole on the substrate is circular, and a diameter of the positive projection of the first via hole on the substrate is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

[0017] For the driving backplane according to any one of the present disclosures, a positive projection of the first via hole on the substrate is elliptical or rectangular.

[0018] For the driving backplane according to any one of the present disclosures, the dielectric layer has a plurality of the first via holes, and the first connection piece is connected to the first conductive portion through the plurality of the first via holes.

[0019] For the driving backplane according to any one of the present disclosures, a distance between a positive projection of the plurality of the first via holes on the substrate and a positive projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers.

[0020] For the driving backplane according to any one of the present disclosures, center points of positive projections of the plurality of the first via holes on the substrate all coincide with a midpoint in a width direction of a positive projection of the driving channel region on the substrate.

[0021] According to one aspect of the present disclosure, there is provided a method for manufacturing a driving backplane, the driving backplane includes a plurality of pixel circuits, the pixel circuits include driving transistors, and the method includes:

[0022] Providing a substrate;

[0023] Fabricating a buffer layer on one side of the substrate;

[0024] An active layer is fabricated on a side of the buffer layer facing away from the substrate. The active layer includes a driving active portion of the driving transistor, and the driving active portion has a driving channel region.

[0025] A first gate insulating layer is fabricated on a side of the active layer facing away from the substrate, and the first gate insulating layer covers at least the driving active portion.

[0026] A first gate metal layer is fabricated on a side of the first gate insulating layer facing away from the substrate. The gate metal layer includes a first conductive portion, and there is an overlapping region between the first conductive portion and the driving channel region.

[0027] A dielectric layer is fabricated on a side of the first gate metal layer facing away from the substrate. The dielectric layer has a first via hole penetrating to the first conductive portion, and a distance between a positive projection of the first via hole on the substrate and a positive projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers.

[0028] A source-drain metal layer is fabricated on a side of the dielectric layer facing away from the substrate. The source-drain metal layer includes a first connecting piece, and the first connecting piece passes through the first via hole and is connected to the first conductive portion.

[0029] According to one aspect of the present disclosure, a display panel is provided, including:

[0030] The driving backplane described in the above aspect;

[0031] A light-emitting device, located on a side of the source-drain metal layer facing away from the substrate and connected to the driving transistor.

[0032] According to one aspect of the present disclosure, a display device is provided, including the display panel described in the above aspect.

[0033] The embodiments of the present disclosure at least include the following technical effects:

[0034] In the embodiments of the present disclosure, by adjusting a planar distance between a first via hole connecting the first conductive portion and a driving channel region of the driving transistor (i.e., a distance between a positive projection of the first via hole and a positive projection of the driving channel region), it is convenient to increase a subthreshold swing of the driving transistor, so that it is convenient to improve a gray-scale control ability of a pixel circuit. Furthermore, for a display panel including the driving backplane, a display effect when the display panel displays an image can be improved.

[0035] It should be understood that the above general description and subsequent detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0037] Figure 1 Schematic cross-sectional structure diagram of a driving transistor region of a display panel provided by an embodiment of the present disclosure.

[0038] Figure 2 Another schematic cross-sectional structure diagram of a driving transistor region of a display panel provided by an embodiment of the present disclosure.

[0039] Figure 3 Schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0040] Figure 4 is Figure 1 or Figure 2 Schematic top view structure diagram of a driving transistor shown in.

[0041] Figure 5 Schematic top view structure diagram of a switching transistor provided by an embodiment of the present disclosure.

[0042] Figure 6 Output characteristic curves of a driving transistor and a switching transistor provided by an embodiment of the present disclosure.

[0043] Figure 7 is Figure 1 or Figure 2 Another schematic top view structure diagram of a driving transistor shown in.

[0044] Figure 8 is Figure 1 or Figure 2 Another schematic top view structure diagram of a driving transistor shown in.

[0045] Figure 9 is Figure 1 or Figure 2 Another schematic top view structure diagram of a driving transistor shown in.

[0046] Figure 10 Provided by an embodiment of the present disclosure Figure 4 , Figure 9 Output characteristic curves of the driving transistor shown in.

[0047] Figure 11 is Figure 1 or Figure 2 Another schematic top view structure diagram of a driving transistor shown in.

[0048] Figure 12 For Figure 1 or Figure 2 The following is a top - view structural schematic diagram of another driving transistor shown.

[0049] Reference numerals:

[0050] 100, display panel;

[0051] 10, driving backplane; 20, light - emitting layer;

[0052] 101, substrate; 102, buffer layer; 103, active layer; 104, first gate insulating layer; 105, first gate metal layer; 106, second gate insulating layer; 107, second gate metal layer; 108, dielectric layer; 109, source - drain metal layer; 110, planarization layer;

[0053] 1031, driving active part; 1032, driving channel region; 1033, switching active part; 1034, switching channel region; 1035a, first doping part; 1035b, second doping part;

[0054] 1051, first conductive part; 1052, second conductive part;

[0055] 1081, first via; 1082, second via;

[0056] 1091, first connecting piece; 1092, second connecting piece; 1093a, third connecting piece; 1093b, fourth connecting piece. Detailed implementation manners

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0058] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0059] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0060] In addition, in the drawings, the thicknesses and regions of the respective layers are exaggerated for clarity. It should be understood that when referring to a layer, region, or component "on" another part, it means that it is directly on the other part, or there may be other components in between.

[0061] The transistors involved in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. Taking a transistor as an example, a transistor refers to an element that includes at least three terminals: a control electrode, a first electrode, and a second electrode. The transistor has a channel region between the first electrode and the second electrode, and current can flow through the first electrode, the channel region, and the second electrode. The channel region is the region where the current mainly flows. Among them, the first electrode is the source electrode and the second electrode is the drain electrode, or the first electrode is the drain electrode and the second electrode is the source electrode. In the case of using transistors with opposite polarities or when the current direction changes during the operation of the circuit, etc., the "first electrode" and "second electrode" can be interchanged with each other.

[0062] Figure 1 Schematically shows a partial cross-sectional structure diagram of a display panel 100 provided by an embodiment of the present disclosure. Figure 2 Schematically shows another partial cross-sectional structure diagram of a display panel 100 provided by an embodiment of the present disclosure. As Figure 1 or Figure 2 shown, the display panel 100 includes a driving backplane 10 and a light emitting layer 20.

[0063] Among them, the driving backplane 10 includes a plurality of pixel circuits distributed at intervals, the light-emitting layer 20 includes a plurality of light-emitting devices distributed at intervals, and one pixel circuit is connected to at least one corresponding light-emitting device (for example, one pixel circuit is connected to one corresponding light-emitting device). In this way, the corresponding light-emitting device can be driven by the pixel circuit to emit light, realizing the display of the picture.

[0064] Among them, as Figure 1 or Figure 2 shown, the driving backplane 10 includes a substrate 101 and a driving layer (not shown in the figure), and the driving layer is located between the substrate 101 and the light-emitting layer 20, and the driving layer includes a plurality of pixel circuits.

[0065] In the embodiments of the present disclosure, the material of the substrate 101 can be an inorganic material or an organic material. For example, in some embodiments, the material of the substrate 101 can be glass materials such as soda-lime glass, quartz glass, sapphire glass, etc., or can be metal materials such as stainless steel, aluminum, nickel, etc. In other embodiments, the material of the substrate 101 can be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyethersulfone (PES), polyimide, polyamide, polyacetal, Poly carbonate (PC), Polyethylene terephthalate (PET), Polyethylenenaphthalate (PEN) or a combination thereof.

[0066] Among them, the substrate 101 can be a single-layer structure or a composite of a multi-layer structure. Taking the substrate 101 as a composite of a multi-layer structure as an example, the substrate 101 includes a first polyimide layer, a protective film layer, and a second polyimide layer stacked in sequence in the direction close to the driving layer.

[0067] In the embodiments of the present disclosure, the pixel circuit included in the driving layer can be a 4T2C, 6T1C, 7T1C, etc. circuit, as long as it can drive the light-emitting device to emit light, and the embodiments of the present disclosure do not make special limitations on this. nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitor Cst (represented by the letter "C").

[0068] Among them, the transistors included in the pixel circuit can be thin-film transistors, and the thin-film transistors can be selected from top-gate thin-film transistors, bottom-gate thin-film transistors, or double-gate thin-film transistors; the capacitor can be a bipolar capacitor or a tripolar capacitor. The material of the channel region of the thin-film transistor can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, or other types of semiconductor materials; the thin-film transistor can be an N-type thin-film transistor or a P-type thin-film transistor.

[0069] Among them, at least one driving transistor is included in the multiple transistors of the pixel circuit. For example, in the case of a 4T2C circuit as the pixel circuit, the pixel circuit includes one driving transistor, three switching transistors, and two capacitors; in the case of a 7T1C circuit as the pixel circuit, the pixel circuit includes one driving transistor, six switching transistors, and one capacitor.

[0070] For the 7T1C circuit, as Figure 3 shown, the pixel circuit includes a driving transistor DT, a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, a fourth switching transistor ST4, a fifth switching transistor ST5, a sixth switching transistor ST6, and a capacitor Cst.

[0071] The first pole of the driving transistor DT is electrically connected to the first pole of the first switching transistor ST1 and the first pole of the sixth switching transistor ST6 respectively. The second pole of the driving transistor DT is electrically connected to the second pole of the third switching transistor ST3 and the first pole of the fourth switching transistor ST4 respectively. The control pole of the driving transistor DT is electrically connected to the first pole of the second switching transistor ST2, the first pole of the third switching transistor ST3, and the first electrode plate of the capacitor Cst respectively.

[0072] Among them, the second pole of the first switching transistor ST1 is used to input a data signal, and the control pole of the first switching transistor ST1 is used to input a scanning signal; the second pole of the second switching transistor ST2 is used to input a first initial voltage signal, and the control pole of the second switching transistor ST2 is used to input a reset signal; the control pole of the third switching transistor ST3 is used to input a scanning signal; the second pole of the fourth switching transistor ST4 is electrically connected to the first pole of the fifth switching transistor ST5 and is used to be electrically connected to a light-emitting device. The control pole of the fourth switching transistor ST4 is used to input a light-emitting control signal; the second pole of the fifth switching transistor ST5 is used to input a second initial voltage signal, and the control pole of the fifth switching transistor ST5 is used to input a reset signal; the second pole of the sixth switching transistor ST6 is electrically connected to the second electrode plate of the capacitor Cst and is used to input a power supply signal. The control pole of the sixth switching transistor ST6 is used to input a light-emitting control signal.

[0073] In some embodiments, asFigure 1 or Figure 2 The driving layer includes, in a direction away from the substrate 101, a buffer layer 102, an active layer 103, a gate insulating layer (a first gate insulating layer 104 and / or a second gate insulating layer 106), a gate metal layer (a first gate metal layer 105 and / or a second gate metal layer 107), a dielectric layer 108, a source-drain metal layer 109, and a planarization layer 110, which are stacked in sequence.

[0074] Among them, the active layer 103 can be a polysilicon layer, an oxide thin film layer, or other structural layers, as long as it can form the channel regions of the transistors and the doped portions (having conductivity) on both sides of the channel regions. The embodiments of the present disclosure do not limit this.

[0075] Among them, the gate metal layer and the source-drain metal layer 109 can be a single-layer structure or a multi-layer structure. For example, the gate metal layer includes a first gate metal layer 105 and a second gate metal layer 107, and / or the source-drain metal layer 109 includes a first source-drain metal layer and a second source-drain metal layer. When the gate metal layer is a multi-layer structure and the source-drain metal layer 109 is a multi-layer structure, correspondingly, the number of layers of the gate insulating layer and the planarization layer 110 will also be adjusted accordingly. The present disclosure does not limit this.

[0076] Among them, the gate metal layer includes the conductive portions of the transistors. The conductive portions of the transistors and the channel regions of the corresponding transistors have overlapping regions, so that the overlapping regions of the conductive portions of the transistors with the channel regions form the control electrodes of the transistors. The planarization layer 110 is provided with vias, and a pixel circuit is connected to at least one light-emitting device through the vias on the planarization layer 110.

[0077] In the embodiments of the present disclosure, the multiple light-emitting devices of the light-emitting layer 20 can be divided into multiple light-emitting units, and the multiple light-emitting units are arranged in an array. Each light-emitting unit includes light-emitting devices with different light-emitting colors. For example, a light-emitting unit can include a red light-emitting device that emits red light, a green light-emitting device that emits green light, and a blue light-emitting device that emits blue light; or a light-emitting unit includes a red light-emitting device that emits red light, a green light-emitting device that emits green light, a blue light-emitting device that emits blue light, and a white light-emitting device that emits white light.

[0078] In some embodiments, the light-emitting device is an organic light-emitting diode (OLED), which includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence in a direction away from the substrate 101.

[0079] Among them, the first electrode can be disposed on the side of the driving layer away from the substrate 101 and is connected to the corresponding pixel circuit. The first electrode can be a single-layer structure or a composite of multiple-layer structures. Exemplarily, when the first electrode is a single-layer structure, the first electrode can include a transparent electrode ITO layer; when the first electrode is a composite of multiple-layer structures, the first electrode includes a first transparent electrode layer, a reflective electrode Ag layer, and a second transparent electrode layer stacked in sequence away from the driving layer. The second electrode covers the light-emitting functional layer, and the second electrodes of multiple light-emitting devices can share an electrode layer. The second electrode can be a single-layer structure or a composite of multiple-layer structures. Exemplarily, when the second electrode is a single-layer structure, the second electrode can be a MgAg composite material layer.

[0080] Among them, the light-emitting functional layer at least includes a composite light-emitting layer EML. Taking the first electrode as the anode and the second electrode as the cathode as an example, at this time, holes can be transmitted to the composite light-emitting layer EML through the first electrode, and electrons can be transmitted to the composite light-emitting layer EML through the second electrode. Then, light emission is realized through the recombination of holes and electrons in the composite light-emitting layer EML, and the color of the light emission depends on the material of the composite light-emitting layer EML. In order to improve the transmission effect of holes and electrons and improve the light-emitting effect of the composite light-emitting layer EML, at least one of a hole injection layer HIL, a hole transport layer HTL, and an electron blocking layer EBL is provided on the side of the composite light-emitting layer EML close to the first electrode, and at least one of a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL is provided on the side of the composite light-emitting layer EML close to the second electrode.

[0081] In the embodiments of the present disclosure, the light-emitting layer 20 includes a pixel definition layer. The pixel definition layer is located on the side of the first electrode away from the substrate 101 and is provided with pixel openings corresponding to multiple light-emitting devices one by one. The first electrode includes an exposed area exposed at the corresponding pixel opening and a covered area covered by the pixel definition layer. The exposed area of the first electrode forms the light-emitting area of the corresponding light-emitting device.

[0082] In some embodiments, the display panel 100 further includes functional layers, such as a thin film encapsulation layer, a touch function layer, etc.

[0083] Taking the display panel 100 including a thin film encapsulation layer as an example, the thin film encapsulation layer is located on the side of the light-emitting layer 20 away from the substrate 101 to cover the light-emitting devices included in the light-emitting layer 20, so as to protect the light-emitting devices to avoid erosion of the light-emitting devices by external water and oxygen.

[0084] Among them, the thin film encapsulation layer can include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, avoiding the degradation of materials caused by the intrusion of water and oxygen into the organic light-emitting functional layer; the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers.

[0085] Among them, the display panel 100 has a display area and a peripheral area located outside the display area. The edge of the inorganic encapsulation layer can be located in the peripheral area, and the edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially stacked on the side of the light emitting layer 20 facing away from the substrate 101.

[0086] Taking the display panel 100 including a touch function layer as an example, the touch function layer is located on the side of the thin film encapsulation layer facing away from the substrate 101 to implement touch operations on the display panel 100.

[0087] As Figure 1 and Figure 4 shown, the driving backplane 10 includes: a substrate 101, an active layer 103, a first gate insulating layer 104, a first gate metal layer 105, a dielectric layer 108, and a source-drain metal layer 109. The active layer 103 is located on one side of the substrate 101 and includes a driving active portion 1031 of a driving transistor. The driving active portion 1031 has a driving channel region 1032. The first gate insulating layer 104 is located on the side of the active layer 103 facing away from the substrate 101 and at least covers the driving active portion 1031. The first gate metal layer 105 is located on the side of the first gate insulating layer 104 facing away from the substrate 101 and includes a first conductive portion 1051. There is an overlapping region between the first conductive portion 1051 and the driving channel region 1032. The dielectric layer 108 is located on the side of the first gate metal layer 105 facing away from the substrate 101 and has a first via 1081 penetrating to the first conductive portion 1051. The distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is less than or equal to 0.5 micrometers. The source-drain metal layer 109 is located on the side of the dielectric layer 108 facing away from the substrate 101 and includes a first connecting piece 1091. The first connecting piece 1091 is connected to the first conductive portion 1051 through the first via 1081.

[0088] In the embodiments of the present disclosure, by adjusting the planar distance between the first via 1081 connecting the first conductive portion 1051 and the driving channel region 1032 of the driving transistor (i.e., the distance between the orthographic projection of the first via 1081 and the orthographic projection of the driving channel region 1032), the subthreshold swing of the driving transistor can be increased, so as to facilitate improving the gray scale control ability of the pixel circuit. Furthermore, for the display panel 100 including the driving backplane 10, the display effect when the display panel 100 displays a picture can be improved.

[0089] Among them, the orthographic projections involved in the present disclosure all refer to the orthographic projections on the substrate 101. In the present disclosure, the relationship between the subthreshold swing and the trap capacitance of a transistor is shown by the following formula:

[0090]

[0091] Among them, in the above formula, S refers to the subthreshold swing, k refers to the Boltzmann constant, T refers to the thermodynamic temperature at which the transistor is located, q refers to the electron charge, and C D refers to the trap capacitance of the transistor, and C OX refers to the gate-source capacitance of the transistor.

[0092] It can be seen from the above formula that the subthreshold swing of the transistor increases as the trap capacitance increases. After careful research, the present disclosure finds that by reducing the distance between the orthographic projection of the first via 1081 and the orthographic projection of the driving channel region 1032, the influence of the trap capacitance of the driving transistor on the subthreshold swing of the driving transistor can be improved, and thus the subthreshold swing of the driving transistor can be increased without increasing the trap capacitance, so as to achieve the improvement of the grayscale control ability.

[0093] In the embodiment of the present disclosure, as Figure 4 shown, the driving active part 1031 of the active layer 103 further includes a first doping part 1035a and a second doping part 1035b located on both sides of the driving channel region 1032. At this time, the source-drain metal layer 109 further includes a third connection piece 1093a and a fourth connection piece 1093b. The third connection piece 1093a is connected to the first doping part 1035a through a via, and the fourth connection piece 1093b is connected to the second doping part 1035b through a via.

[0094] Among them, the first doping part 1035a and the second doping part 1035b serve as the source and drain of the driving transistor respectively, which facilitates the connection with other switching transistors in the pixel circuit through the third connection piece 1093a and the fourth connection piece 1093b.

[0095] In the embodiment of the present disclosure, as Figure 5 shown, the active layer 103 further includes a switching active part 1033 of the switching transistor. The switching active part 1033 has a switching channel region 1034, and the first gate insulating layer 104 also covers the switching active part 1033; the first gate metal layer 105 includes a second conductive part 1052, and there is an overlapping region between the second conductive part 1052 and the switching channel region 1034; the dielectric layer 108 has a second via 1082 penetrating to the second conductive part 1052; the source-drain metal layer 109 includes a second connection piece 1092, and the second connection piece 1092 is connected to the second conductive part 1052 through the second via 1082.

[0096] Among them, the number of switch active parts 1033, the number of second conductive parts 1052, and the number of second vias 1082 can all refer to the number of switching transistors included in the pixel circuit, and the switch active parts 1033, the second conductive parts 1052, and the second vias 1082 correspond one by one.

[0097] Optionally, the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switch channel region 1034 on the substrate 101 is less than or equal to 0.5 micrometers. Of course, since the subthreshold swing of the switching transistor has little effect on the light-emitting effect of the light-emitting device when the pixel circuit controls the corresponding light-emitting device to emit light, the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switch channel region 1034 on the substrate 101 can also be set to be greater than or equal to 0.5 micrometers. That is, the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is less than the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switch channel region 1034 on the substrate 101. In this way, the subthreshold swing of the driving transistor is greater than that of the switching transistor, so as to improve the grayscale control ability of the display panel 100. Exemplarily, the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switch channel region 1034 on the substrate 101 is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

[0098] Among them, for the case where the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is less than or equal to 0.5 micrometers, and the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switch channel region 1034 on the substrate 101 is greater than 0.5 micrometers, the output characteristic curves S1 of the driving transistor and S2 of the switching transistor are as Figure 6 shown. It can be seen from the figure that the subthreshold swing of the driving transistor is significantly greater than that of the switching transistor.

[0099] In some embodiments, as Figure 2 shown, the driving backplane 10 further includes a second gate insulating layer 106 and a second gate metal layer 107. The second gate insulating layer 106 and the second gate metal layer 107 are located between the first gate metal layer 105 and the dielectric layer 108, and the second gate insulating layer 106 is located on the side close to the substrate 101.

[0100] Among them, the second gate metal layer 107 includes a third conductive portion, and there is an overlapping area between the orthographic projection of the first conductive portion 1051 on the substrate 101 and the orthographic projection of the third conductive portion on the substrate 101, so as to form two electrodes of the capacitor included in the pixel circuit through the first conductive portion 1051 and the third conductive portion respectively.

[0101] Among them, in addition to penetrating the dielectric layer 108, the first via 1081 also penetrates the second gate insulating layer 106 to ensure the connection between the first connection piece 1091 and the first conductive portion 1051. The second gate metal layer 107 has a through hole, and the edge of the orthographic projection of the through hole on the substrate 101 is located outside the orthographic projection of the first via 1081 on the substrate 101, so as to avoid the situation of connecting with the second gate metal layer 107 when the first connection piece 1091 is connected to the first conductive portion 1051.

[0102] In the embodiment of the present disclosure, the orthographic projection of the first via 1081 on the substrate 101 can be circular, or can be oval, rectangular (such as a rectangle), etc., as long as it can form an interface defect on the dielectric layer 108.

[0103] Among them, according to the above formula, it can be known that the subthreshold swing of the transistor increases with the increase of the trap capacitance, and the larger the area of the orthographic projection of the first via 1081 on the substrate 101, the larger the interface defect on the dielectric layer 108, and then the larger the trap capacitance of the driving transistor, and thus the larger the subthreshold swing of the driving transistor.

[0104] Therefore, in the embodiment of the present disclosure, in addition to reducing the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 to increase the subthreshold swing of the driving transistor, the area of the orthographic projection of the first via 1081 on the substrate 101 can also be adjusted larger compared to the conventional design of the first via 1081 to increase the subthreshold swing of the driving transistor.

[0105] Combined with the above, the dielectric layer 108 has a second via 1082, and the area of the orthographic projection of the second via 1082 is set according to the conventional design. At this time, the area of the orthographic projection of the first via 1081 on the substrate 101 is set with the adjusted design, so that the area of the orthographic projection of the first via 1081 on the substrate 101 is larger than the area of the orthographic projection of the second via 1082 on the substrate 101, and then the subthreshold swing of the driving transistor is larger than the subthreshold swing of the switching transistor, so as to improve the grayscale control ability of the display panel 100.

[0106] Exemplarily, such as Figure 7As shown, the orthographic projection of the first via 1081 on the substrate 101 is adjusted to be oval, so as to increase the area of the orthographic projection of the first via 1081 on the substrate 101 compared with the conventional design of the first via 1081, thereby increasing the subthreshold swing of the driving transistor; or, as Figure 8 shown, the orthographic projection of the first via 1081 on the substrate 101 is adjusted to be rectangular, so as to increase the area of the orthographic projection of the first via 1081 on the substrate 101 compared with the conventional design of the first via 1081, thereby increasing the subthreshold swing of the driving transistor; or, as Figure 4 shown, the orthographic projection of the first via 1081 on the substrate 101 is adjusted to be circular, so as to increase the area of the orthographic projection of the first via 1081 on the substrate 101 compared with the conventional design of the first via 1081, thereby increasing the subthreshold swing of the driving transistor.

[0107] Among them, for the case where the orthographic projection of the first via 1081 on the substrate 101 is circular, the diameter of the orthographic projection of the first via 1081 on the substrate 101 is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

[0108] In some embodiments, there is an overlapping area between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 (that is, the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is zero). In this way, the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is further reduced, so as to improve the influence of the trap capacitance at the interface defect of the dielectric layer 108 on the subthreshold swing of the driving transistor, thereby further increasing the subthreshold swing of the driving transistor.

[0109] Optionally, as Figure 9 shown, a partial edge of the orthographic projection of the first via 1081 on the substrate 101 coincides with a partial edge of the orthographic projection of the driving channel region 1032 on the substrate 101. Or, as Figure 4 shown, the center point of the orthographic projection of the first via 1081 on the substrate 101 coincides with the midpoint of the orthographic projection of the driving channel region 1032 on the substrate 101 in the width direction W.

[0110] Among them, when the center point of the orthographic projection of the first viaduct 1081 on the substrate 101 coincides with the midpoint of the orthographic projection of the driving channel region 1032 in the width direction, the orthographic projection of the first viaduct 1081 on the substrate 101 can extend beyond the orthographic projection of the driving channel region 1032 on the substrate 101 in the width direction of the driving channel region 1032; of course, it can also be that the orthographic projection of the driving channel region 1032 on the substrate 101 extends beyond the orthographic projection of the first viaduct 1081 on the substrate 101 in the width direction of the driving channel region 1032. The embodiments of the present disclosure do not limit this.

[0111] For the structure of the driving transistor as described above, such as Figure 9 shown, the output characteristic curves of the driving transistor are curves S11, S12, and S13 as shown in Figure 10 ; for the structure of the driving transistor as described above, such as Figure 4 shown, the output characteristic curves of the driving transistor are curves S14, S15, and S16 as shown in Figure 10 . From Figure 10 the curves S11, S12, and S13 shown, it can be seen that for the structure of the driving transistor as described above, such as Figure 9 shown, the subthreshold swing of the driving transistor is greater than or equal to 0.4 and less than or equal to 0.7; and from Figure 10 the curves S14, S15, and S16 shown, it can be seen that for the structure of the driving transistor as described above, such as Figure 4 shown, the subthreshold swing of the driving transistor is greater than or equal to 0.5 and less than or equal to 0.8.

[0112] In some embodiments, as shown in Figure 11 or Figure 12 , the dielectric layer 108 has a plurality of first viaducts 1081, and the first connection piece 1091 is connected to the first conductive part 1051 through the plurality of first viaducts 1081. In this way, a plurality of interface defects are formed in the dielectric layer 108 through the plurality of first viaducts 1081, so as to form a plurality of trap capacitances that affect the subthreshold swing of the driving transistor, and further increase the subthreshold swing of the driving transistor to further improve the grayscale control ability of the pixel circuit.

[0113] Among them, for the multiple first vias 1081 of the dielectric layer 108, it can be that the distance between the orthographic projection of some of the multiple first vias 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 is less than or equal to 0.5 micrometers. At this time, the trap capacitance corresponding to this part of the first vias 1081 has a greater impact on the subthreshold swing of the driving transistor. Of course, it can also be that the distances between the orthographic projections of the multiple first vias 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 are all less than or equal to 0.5 micrometers. At this time, the trap capacitances corresponding to the multiple first vias 1081 all have a greater impact on the subthreshold swing of the driving transistor. Exemplarily, as Figure 11 shown, the dielectric layer 108 is formed with three first vias 1081, and partial edges of the orthographic projections of the three first vias 1081 on the substrate 101 coincide with partial edges of the driving channel region 1032.

[0114] Among them, for the multiple first vias 1081 of the dielectric layer 108, it can be that the centers of the orthographic projections of some of the multiple first vias 1081 on the substrate 101 coincide with the midpoint in the width direction of the orthographic projection of the driving channel region 1032. At this time, the trap capacitance corresponding to this part of the first vias 1081 has a greater impact on the subthreshold swing of the driving transistor. Of course, it can also be that the centers of the orthographic projections of the multiple first vias 1081 on the substrate 101 coincide with the midpoint in the width direction of the orthographic projection of the driving channel region 1032 on the substrate 101. At this time, the trap capacitances corresponding to the multiple first vias 1081 all have a greater impact on the subthreshold swing of the driving transistor. Exemplarily, as Figure 12 shown, the dielectric layer 108 is formed with three first vias 1081, and the centers of the orthographic projections of the three first vias 1081 on the substrate 101 coincide with the midpoint in the width direction of the orthographic projection of the driving channel region 1032 on the substrate 101.

[0115] The embodiments of the present disclosure also provide a manufacturing method of a driving backplane. The driving backplane includes multiple pixel circuits, and the pixel circuits include driving transistors. The method includes the following steps S101 to step S107.

[0116] Step S101: Provide a substrate.

[0117] Step S102: Fabricate a buffer layer on one side of the substrate.

[0118] Step S103: Fabricate an active layer on the side of the buffer layer away from the substrate. The active layer includes a first active portion, and the first active portion has a driving channel region.

[0119] Step S104: Fabricate a first gate insulating layer on a side of the active layer facing away from the substrate, where the first gate insulating layer covers at least the first active portion;

[0120] Step S105: Fabricate a first gate metal layer on a side of the first gate insulating layer facing away from the substrate. The gate metal layer includes a first conductive portion. There is an overlapping region between the first conductive portion and the driving channel region, and a control electrode of the driving transistor is formed in a region of the first conductive portion overlapping with the driving channel region;

[0121] Step S106: Fabricate a dielectric layer on a side of the first gate metal layer facing away from the substrate. The dielectric layer has a first via hole penetrating through to the first conductive portion. The distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers;

[0122] Step S107: Fabricate a source-drain metal layer on a side of the dielectric layer facing away from the substrate. The source-drain metal layer includes a first connection piece, and the first connection piece passes through the first via hole and is connected to the first conductive portion.

[0123] In the embodiment of the present disclosure, the driving backplane fabricated through the above steps reduces the distance between the orthographic projection of the first via hole and the orthographic projection of the driving channel region, thereby increasing the subthreshold swing of the driving transistor. In this way, it is convenient to improve the gray-scale control ability of the pixel circuit. Furthermore, for a display panel including this driving backplane, the display effect when the display panel displays an image can be improved.

[0124] The driving backplane fabricated through the above steps is only the most basic structure. For driving backplanes with other structures, optionally, the above fabrication method further includes: before the above step S106, fabricate a second gate insulating layer on a side of the first gate metal layer facing away from the substrate, then fabricate a second gate metal layer on a side of the second gate insulating layer facing away from the substrate, and then fabricate the dielectric layer in the above step S106 on a side of the second gate metal layer facing away from the substrate. At this time, in addition to penetrating the dielectric layer, the first via hole also penetrates the second gate insulating layer.

[0125] Among them, the materials of each film layer and the specific structure of each film layer in the above steps can refer to those described in the above embodiment, and the embodiment of the present disclosure will not elaborate on this. Additionally, in the above step S103, taking the active layer as a polysilicon film layer as an example, an amorphous silicon film layer can be fabricated on a side of the buffer layer facing away from the substrate first, and then the amorphous silicon film layer is laser crystallized to obtain a polysilicon film layer; after the above step S105, it further includes doping positions on both sides of the driving channel region of the driving active portion based on the first conductive portion included in the first gate metal layer to obtain two doped portions as the first pole and the second pole of the driving transistor.

[0126] It should be noted that although the steps of the method for manufacturing the driving backplane in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0127] The embodiments of the present disclosure further provide a display device, which includes the display panel described in the above embodiments. Thus, for the display device including the above display panel, when realizing the picture display, the picture display effect can be improved based on the higher gray scale control ability.

[0128] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A driving backplane, the driving backplane includes a plurality of pixel circuits, and the pixel circuit includes a driving transistor, characterized in that, The driving backplane comprises: substrate substrate; An active layer, located on one side of the base substrate, and including a driving active portion of the driving transistor, wherein the driving active portion has a driving channel region; A first gate insulating layer, located on a side of the active layer away from the substrate and at least covering the driving active portion; A first gate metal layer is located on a side of the first gate insulating layer away from the base substrate and includes a first conductive portion, wherein the first conductive portion and the driving channel region have an overlapping area; a dielectric layer, located on a side of the first gate metal layer away from the base substrate, and having a plurality of first via holes penetrating to the first conductive portion; The source-drain metal layer is located on a side of the dielectric layer away from the substrate, and includes a first connecting piece, wherein the first connecting piece is connected to the first conductive portion through a plurality of the first via holes.

2. The driving backplane according to claim 1, characterized in that, The orthographic projections of the plurality of first via holes on the base substrate all overlap with the orthographic projections of the driving channel region on the base substrate.

3. The driving backplane according to claim 2, wherein Partial edges of the orthographic projections of the plurality of first vias on the base substrate overlap with partial edges of the orthographic projections of the driving channel region on the base substrate.

4. The driving backplane according to claim 1, wherein The orthographic projections of the plurality of first via holes on the base substrate are at least one of an ellipse, a rectangle or a circle.

5. The driving backplane according to any one of claims 1-4, characterized in that, The driving backplane comprises a second gate insulating layer and a second gate metal layer; The second gate insulating layer and the second gate metal layer are located between the first gate metal layer and the dielectric layer, and the second gate insulating layer is located on a side close to the substrate; The second gate metal layer has through holes, and the projection of each of the first via holes on the base substrate is located within the orthographic projection of the through hole on the base substrate, or the orthographic projection edge of the through hole on the base substrate is located outside the orthographic projection of the first via hole on the base substrate.

6. The driving backplane according to claim 5, wherein, The pixel circuit includes a capacitor, and the second gate metal layer includes a third conductive portion; An orthographic projection of the third conductive portion on the base substrate overlaps with an orthographic projection of the first conductive portion on the base substrate, and the first conductive portion and the third conductive portion respectively form two plates of the capacitor.

7. The driving backplane according to any one of claims 1-4, characterized in that, The pixel circuit includes a switching transistor; The active layer includes a switch active portion of the switch transistor, the switch active portion has a switch channel region, the first gate insulating layer also covers the switch active portion, the first gate metal layer includes a second conductive portion, and the second conductive portion and the switch channel region have an overlapping area; The dielectric layer has a second via hole penetrating to the second conductive part, and the source-drain metal layer includes a second connecting piece, and the second connecting piece is connected to the second conductive part through the second via hole.

8. The driving backplane according to claim 7, wherein The orthographic projection distance between each of the first via holes and the driving channel region on the base substrate is smaller than the orthographic projection distance between the second via holes and the switch channel region on the base substrate.

9. The driving backplane according to claim 7, wherein The sum of the orthographic projection areas of the plurality of first via holes on the base substrate is greater than the orthographic projection area of ​​the second via holes on the base substrate.

10. The driving backplane according to any one of claims 1-4, characterized in that, The pixel circuit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a capacitor; A first pole of the driving transistor is electrically connected to a first pole of the first switching transistor and a first pole of the sixth switching transistor respectively. A second pole of the driving transistor is electrically connected to a second pole of the third switching transistor and a first pole of the fourth switching transistor respectively. A control pole of the driving transistor is electrically connected to a first pole of the second switching transistor, a first pole of the third switching transistor, and a first electrode plate of the capacitor respectively; A second pole of the first switching transistor is used for inputting a data signal, and a control pole of the first switching transistor is used for inputting a scanning signal; a second pole of the second switching transistor is used for inputting a first initial voltage signal, and a control pole of the second switching transistor is used for inputting a reset signal; a control pole of the third switching transistor is used for inputting a scanning signal; a second pole of the fourth switching transistor is electrically connected to a first pole of the fifth switching transistor and is used for being electrically connected to a light-emitting device, and a control pole of the fourth switching transistor is used for inputting a light-emitting control signal; a second pole of the fifth switching transistor is used for inputting a second initial voltage signal, and a control pole of the fifth switching transistor is used for inputting a reset signal; a second pole of the sixth switching transistor is electrically connected to a second electrode plate of the capacitor and is used for inputting a power supply signal, and a control pole of the sixth switching transistor is used for inputting a light-emitting control signal.

11. A manufacturing method of a driving backplane, characterized in that, The driving backplane includes a plurality of pixel circuits, and the pixel circuit includes a driving transistor. The method includes: Providing a substrate; Fabricating a buffer layer on one side of the substrate; Fabricating an active layer on a side of the buffer layer facing away from the substrate. The active layer includes a driving active part of the driving transistor, and the driving active part has a driving channel region; Fabricating a first gate insulating layer on a side of the active layer facing away from the substrate, and the first gate insulating layer at least covers the driving active part; Fabricating a first gate metal layer on a side of the first gate insulating layer facing away from the substrate. The first gate metal layer includes a first conductive part, and there is an overlapping region between the first conductive part and the driving channel region; Fabricating a dielectric layer on a side of the first gate metal layer facing away from the substrate, and the dielectric layer has a plurality of first vias penetrating to the first conductive part; Fabricating a source-drain metal layer on a side of the dielectric layer facing away from the substrate. The source-drain metal layer includes a first connection piece, and the first connection piece is connected to the first conductive part through the plurality of first vias.

12. A driving backplane, the driving backplane includes a plurality of pixel circuits, and each pixel circuit includes a driving transistor and at least one switching transistor, characterized in that, The driving backplane includes: A substrate; An active layer, located on one side of the substrate, and including a driving active part of the driving transistor and a switching active part of the switching transistor. The driving active part has a driving channel region, and the switching active part has a switching channel region; A first gate insulating layer, located on a side of the active layer facing away from the substrate, and at least covering the driving active part and the switching active part; A first gate metal layer, located on a side of the first gate insulating layer away from the substrate, and including a first conductive portion and a second conductive portion, wherein an overlapping region exists between the first conductive portion and the driving channel region, and an overlapping region exists between the second conductive portion and the switching channel region; A dielectric layer, located on a side of the first gate metal layer away from the substrate, and having a first via hole penetrating to the first conductive portion and a second via hole penetrating to the second conductive portion, wherein a total area of a positive projection of the first via hole on the substrate is greater than an area of a positive projection of the second via hole on the substrate; A source-drain metal layer, located on a side of the dielectric layer away from the substrate, and including a first connection piece and a second connection piece, wherein the first connection piece is connected to the first conductive portion through the first via hole, and the second connection piece is connected to the second conductive portion through the second via hole.

13. The driving backplane according to claim 12, characterized in that, A positive projection pitch between the first via hole and the driving channel region on the substrate is less than a positive projection pitch between the second via hole and the switching channel region on the substrate.

14. The driving backplane according to claim 13, characterized in that, The positive projection pitch between the first via hole and the driving channel region on the substrate is less than or equal to 0.5 micrometers.

15. The driving backplane according to claim 14, wherein An overlapping region exists between a positive projection of the first via hole on the substrate and a positive projection of the driving channel region on the substrate.

16. The driving backplane according to any one of claims 12-15, characterized in that, The positive projection of the first via hole on the substrate is one of an ellipse, a rectangle or a circle.

17. A manufacturing method of a driving backplane, characterized in that, The driving backplane includes a plurality of pixel circuits, each pixel circuit includes a driving transistor and at least one switching transistor, and the method includes: Providing a substrate; Fabricating a buffer layer on one side of the substrate; Fabricating an active layer on a side of the buffer layer away from the substrate, the active layer including a driving active portion of the driving transistor and a switching active portion of the switching transistor, the driving active portion having a driving channel region, and the switching active portion having a switching channel region; Fabricating a first gate insulating layer on a side of the active layer away from the substrate, the first gate insulating layer at least covering the driving active portion and the switching active portion; Fabricating a first gate metal layer on a side of the first gate insulating layer away from the substrate, the first gate metal layer including a first conductive portion and a second conductive portion, wherein an overlapping region exists between the first conductive portion and the driving channel region, and an overlapping region exists between the second conductive portion and the switching channel region; Fabricating a dielectric layer on a side of the first gate metal layer away from the substrate, the dielectric layer having a first via hole penetrating to the first conductive portion and a second via hole penetrating to the second conductive portion, wherein a total area of a positive projection of the first via hole on the substrate is greater than an area of a positive projection of the second via hole on the substrate; Fabricating a source-drain metal layer on a side of the dielectric layer away from the substrate, the source-drain metal layer including a first connection piece and a second connection piece, wherein the first connection piece is connected to the first conductive portion through the first via hole, and the second connection piece is connected to the second conductive portion through the second via hole.

18. A display panel, characterized in that, Including: The driving backplane according to any one of claims 1-10, or the driving backplane according to any one of claims 12-16; The light-emitting device is located on a side of the source-drain metal layer away from the substrate, and is connected to the driving transistor.

19. A display device, characterized in that, It includes the display panel according to claim 18.

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