Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. A display device includes a substrate, a sub-pixel electrode over the substrate, a pixel defining layer partially over the sub-pixel electrode, an intermediate layer partially over the pixel defining layer and defining a hole exposing at least a portion of the sub-pixel electrode, and an opposing electrode partially over the intermediate layer, a first side surface of the defining hole adjacent to an edge portion of the sub-pixel electrode includes a side surface of the pixel defining layer and a side surface of the intermediate layer.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10-2024-0000490, filed with the Korean Intellectual Property Office on January 2, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] A display device visually displays data. The display device may provide an image by using a light-emitting diode. As the use of the display device has become diversified, various designs have been attempted to improve the quality of the display device. Summary of the Invention

[0005] One or more embodiments include a display device and a method of manufacturing the display device.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments, a display device includes: a substrate; a sub-pixel electrode above the substrate; a pixel defining layer partially above the sub-pixel electrode; an intermediate layer partially above the pixel defining layer, and the intermediate layer defines a hole exposing at least a part of the sub-pixel electrode; and a counter electrode partially above the intermediate layer, wherein a first side surface of the hole adjacent to an edge portion of the sub-pixel electrode includes a side surface of the pixel defining layer and a side surface of the intermediate layer.

[0008] The hole may correspond to a region where the sub-pixel electrode and the counter electrode contact each other.

[0009] The thickness of the side surface of the pixel defining layer may be about or less.

[0010] The thickness of the side surface of the pixel defining layer may be about or more and about or less.

[0011] The length of the hole in a first direction may be about 3 μm or more and about 15 μm or less.

[0012] A second side surface of the hole is spaced apart from the first side surface in the first direction, and the second side surface may include only a side surface of the intermediate layer.

[0013] The second side surface of the hole may not include the surface of the pixel defining layer.

[0014] The intermediate layer may include an emission layer and a functional layer.

[0015] According to one or more embodiments, a method of manufacturing a display device may include: forming a hole by irradiating a laser beam onto a pixel defining layer and an intermediate layer above an upper surface of a sub-pixel electrode; and forming a counter electrode on the sub-pixel electrode, wherein a thickness of a portion of the pixel defining layer above the sub-pixel electrode is about or less.

[0016] The thickness of the portion of the pixel defining layer may be about or greater.

[0017] The formation of the hole may include removing another portion of the pixel defining layer above the sub-pixel electrode and a portion of the intermediate layer above the sub-pixel electrode by irradiating a laser beam.

[0018] The formation of the hole may include concurrently removing another portion of the pixel defining layer above the sub-pixel electrode and a portion of the intermediate layer above the sub-pixel electrode by irradiating a laser beam.

[0019] The hole may correspond to a region where the sub-pixel electrode and the counter electrode contact each other.

[0020] The length of the hole may be about 3 μm or greater and about 15 μm or less.

[0021] The length of the region of the pixel defining layer above the sub-pixel electrode may be about 1 μm or greater.

[0022] The length between an end of the sub-pixel electrode and an end of the pixel defining layer above the sub-pixel electrode may be about 1 μm or greater.

[0023] The intermediate layer may include an emission layer and a functional layer.

[0024] The wavelength of the laser beam may correspond to the ultraviolet region.

[0025] The wavelength of the laser beam may be about 300 nm or greater and about 400 nm or less.

[0026] The intensity of the laser beam may be about 200 mJ / cm 2 or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects of the embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0028] Figure 1is a schematic perspective view of a display device according to one or more embodiments;

[0029] Figure 2 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0030] Figure 3 is a schematic equivalent circuit diagram of any sub-pixel circuit provided in a display device according to one or more embodiments;

[0031] Figure 4 is a schematic cross-sectional view of a display panel according to one or more embodiments;

[0032] Figure 5 is a schematic cross-sectional view of a display panel in a case where at least a part of the pixel defining layer located on the upper surface of the sub-pixel electrode has a thickness exceeding about ; and

[0033] Figure 6A is a schematic cross-sectional view showing a method of manufacturing a display device;

[0034] Figure 6B schematically shows Figure 6A an enlarged view of region A of

[0035] Figure 7 and Figure 8 are schematic cross-sectional views showing a method of manufacturing a display device. DETAILED DESCRIPTION

[0036] Aspects of some embodiments of the present disclosure and methods of implementing these embodiments can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, processes / techniques, elements, and technologies that are redundant, irrelevant to or not related to the description of the embodiments, or not necessary for a full understanding of the aspects of the present disclosure by those of ordinary skill in the art may be omitted. Unless otherwise indicated, throughout the drawings and the written description, the same reference numerals, characters, or combinations thereof represent the same elements, and thus, their repeated description may be omitted.

[0037] The described embodiments can have various modifications and can be implemented in different forms, and should not be construed as limited to the embodiments shown herein. The use of "can", "may", or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and alternatives within the spirit and scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure can be partially or wholly combined with each other, and various interlocks and drives are possible technically. Each embodiment can be implemented independently of each other or can be implemented in association with each other.

[0038] In the drawings, for clarity and / or description purposes, the relative sizes of elements, layers, and regions may be exaggerated. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc.

[0039] In this document, various embodiments are described with reference to cross-sectional views that are schematic diagrams of embodiments and / or intermediate structures. Thus, variations in the shape of the illustration due to, for example, manufacturing techniques and / or tolerances are to be expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes shown of elements, layers, or regions, but should include deviations in shape caused, for example, by manufacturing.

[0040] For example, an implantation region shown as rectangular will generally have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed.

[0041] For ease of explanation, in this document, spatial relative terms such as "under", "below", "beneath", "lower side", "underneath", "above", "upper", and "upper side" may be used to describe the relationship of one element or feature shown in the drawings to another element (or multiple other elements) or another feature (or multiple other features). It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are also intended to cover different orientations during the use or operation of the device. For example, if the device in the drawings is flipped, an element described as "under", "below", or "beneath" another element or feature will then be oriented "above" the said other element or feature. Thus, the example terms "under" and "below" can cover both the upper and lower orientations. The device may be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used in this document should be interpreted accordingly. Similarly, when a first component is described as being disposed "on" a second component, this indicates that the first component is disposed at the upper side or the lower side of the second component based on the direction of gravity, and is not limited to the upper side of the second component.

[0042] In addition, the phrase "in a schematic cross-sectional view" means when observing a schematic cross-section taken by vertically cutting an object / target part from the side. The term "overlap / overlapped with" means that a first object may be located above or below a second object or on the side of the second object, and vice versa. In addition, the term "overlap / overlapped with" may include stacking, facing or being oriented towards, extending throughout, covering or partially covering, or any other suitable terms that will be appreciated and understood by those of ordinary skill in the art. The expression "not overlap / overlapped with" may include meanings such as "separated from", "disposed apart from", or "deviated from" and any other suitable equivalent terms that will be appreciated and understood by those of ordinary skill in the art. The terms "face" and "be oriented towards" may mean that a first object may be directly or indirectly opposite a second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite each other although still facing each other.

[0043] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, the element, layer, region or component can be directly formed on, directly on, directly connected to or directly coupled to the other element, layer, region or component, or can be indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to the other element, layer, region or component, such that there can be one or more intervening elements, layers, regions or components. Additionally, this can be collectively referred to as direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region and / or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region and / or component, the layer, region and / or component can be directly electrically connected or electrically coupled to the other layer, region and / or component, or there can be one or more intervening layers, regions and / or components. One or more intervening components can include switches, resistors and / or capacitors, etc. When describing embodiments, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or coupled to another component or on another component without an intervening component.

[0044] Further, in this specification, when a part of a layer, film, region or plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region or plate, etc. is formed "under" another part, this includes not only the case where the part is "directly" "under" the other part, but also the case where there is another part between the part and the other part. Meanwhile, other expressions describing the relationship between components such as "between", "immediately between" or "adjacent to" and "directly adjacent to" can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0045] For the purposes of the present disclosure, when a phrase such as "at least one of...", "any one of...", or "one or more of..." follows a list of elements, it modifies the entire list of elements, rather than a single element in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the phrase "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any combination and all combinations of one or more of the associated listed items. For example, the phrase "A and / or B" can include A, B, or A and B. Similarly, when phrases such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases precede or follow a list of elements, they modify the entire list of elements, rather than a single element in the list.

[0046] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are only used to distinguish one element, member, component, region, area, layer, section, or part from another element, member, component, region, area, layer, section, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer, or section described below could be termed a second element, component, region, layer, or section. Describing an element as a first element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms "first", "second", etc. may represent "first category (or first group)", "second category (or second group)", etc., respectively.

[0047] In an example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. This also applies to the first direction, second direction, and / or third direction.

[0048] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are also intended to include the plural forms, and the plural forms are also intended to include the singular form. It will also be understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes", and "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0049] When one or more embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0050] As used herein, the terms "substantially", "about", "approximate" and similar terms are used as approximate terms rather than degree terms and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" can include a range of ±5% of the corresponding value. Taking into account the measurements under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and means within an acceptable range of deviation for the particular value determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within a range of ±30%, ±20%, ±10% or ±5% of the stated value. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure".

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which the present disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0052] Figure 1 is a schematic perspective view of a display device according to one or more embodiments.

[0053] The display device according to an embodiment is a device that displays video or still images, and the display device may be a portable electronic device such as a mobile phone, a smartphone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, or an ultra-mobile PC (UMPC). Further, the display device according to an embodiment may also be used as a display screen for various products such as a television, a laptop computer, a monitor, an advertising board, or an Internet of Things (IoT) device. In addition, the display device according to one or more embodiments may be used as a wearable device such as a smartwatch, a watch phone, a glasses-type display, and a head-mounted display (HMD). In addition, the display device according to one or more embodiments may be used as an instrument panel of a vehicle, a central instrument panel of a vehicle, or a central information display (CID) located on the instrument panel, a rearview mirror display that replaces a side mirror of a vehicle, and a display arranged on the back surface of a front seat for entertainment of a passenger on a rear seat of the vehicle.

[0054] Referring to Figure 1 , the display device 1 may have an edge in a first direction and an edge in a second direction. Here, the first direction and the second direction may be directions that cross each other. For example, the first direction and the second direction may form an acute angle with each other. As another example, the first direction and the second direction may form an obtuse angle with each other, or may be orthogonal to each other. Hereinafter, the case where the first direction and the second direction are orthogonal to each other will be mainly described in detail. For example, the first direction may be the x direction or the -x direction, and the second direction may be the y direction or the -y direction. A third direction perpendicular to the first direction and the second direction may be the z direction or the -z direction.

[0055] The display device 1 may include a display area DA and a peripheral area PA outside the display area DA. The display device 1 may provide an image by using light emitted from a plurality of sub-pixels PX arranged in the display area DA. The peripheral area PA is an area outside the display area DA, and may be of a type of a non-display area where no sub-pixels are arranged. The display area DA may be completely surrounded by the peripheral area PA.

[0056] Hereinafter, an organic light-emitting display device will be described as an example of the display device 1 according to one or more embodiments. However, the display device 1 is not limited thereto. As one or more other embodiments, the display device 1 may be a display device such as an inorganic light-emitting display device, an inorganic electroluminescent (EL) display device, or a quantum dot light-emitting device. For example, the emission layer of the display element included in the display device 1 may further include an organic material or an inorganic material. In addition, the display device 1 may further include an emission layer and quantum dots positioned on a path of light emitted by the emission layer.

[0057] Figure 2is a schematic cross-sectional view of a display device according to one or more embodiments. For example, Figure 2 is a schematic cross-sectional view of a display area DA of a display device 1 according to one or more embodiments.

[0058] Referring to Figure 2 , the display device 1 includes a display panel 10 and a touch sensor layer 400 on the display panel 10. The display panel 10 may include a substrate 100, a buffer layer 111, an inorganic insulating layer IIL, an organic insulating layer OIL, a sub-pixel circuit PC, a connection electrode CM, an organic light-emitting diode OLED, a pixel defining layer 118, a spacer, and a encapsulation layer 300. That is, the substrate 100, the buffer layer 111, the inorganic insulating layer IIL, the organic insulating layer OIL, the sub-pixel circuit PC, the connection electrode CM, the organic light-emitting diode OLED, the pixel defining layer 118, the spacer, and the encapsulation layer 300 may be disposed in a display area DA of the display panel 10.

[0059] For example, the substrate 100 may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c, and a second barrier layer 100d. In one or more embodiments, the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d may be sequentially stacked in a thickness direction of the substrate 100.

[0060] At least one of the first base layer 100a and the second base layer 100c may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, triacetyl cellulose, or cellulose acetate propionate.

[0061] The first barrier layer 100b and the second barrier layer 100d are barrier layers configured to reduce or prevent penetration of external foreign substances, and each may be a single layer or multiple layers of an inorganic material including, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), and / or silicon oxynitride (SiO x N y ).

[0062] The buffer layer 111 may be located on the substrate 100 (as used herein, "located on" or "on" may mean "above"). The buffer layer 111 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), or silicon oxide (SiO2), and the buffer layer 111 may include a single layer or multiple layers each including the above inorganic insulating material.

[0063] The inorganic insulating layer IIL may be located on the buffer layer 111. The inorganic insulating layer IIL may include a first inorganic insulating layer 112, a second inorganic insulating layer 113, and a third inorganic insulating layer 114.

[0064] The sub-pixel circuit PC may be arranged in the display area DA. The sub-pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0065] The semiconductor layer Act may be located on the buffer layer 111. The semiconductor layer Act may include polysilicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The semiconductor layer Act may include a channel region, a drain region, and a source region, and the drain region and the source region are respectively arranged on both sides of the channel region.

[0066] The gate electrode GE may be located above the semiconductor layer Act. The gate electrode GE may overlap with the channel region of the semiconductor layer Act. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), etc., and may include a multi-layer or a single layer each containing the above materials.

[0067] The first inorganic insulating layer 112 may be between the semiconductor layer Act and the gate electrode GE. The first inorganic insulating layer 112 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0068] The second inorganic insulating layer 113 may be located on the gate electrode GE. The second inorganic insulating layer 113 may be provided to cover the gate electrode GE. The second inorganic insulating layer 113 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x ). Zinc oxide (ZnOx ) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0069] The upper electrode CE2 of the storage capacitor Cst may be located on the second inorganic insulating layer 113. The upper electrode CE2 may overlap with the gate electrode GE located below the upper electrode CE2. At this time, the overlapping gate electrode GE and upper electrode CE2 and the second inorganic insulating layer 113 therebetween may form the storage capacitor Cst. That is, the gate electrode GE may serve as the lower electrode CE1 of the storage capacitor Cst.

[0070] Thus, the storage capacitor Cst and the thin film transistor TFT may overlap with each other. However, the present disclosure is not limited thereto. For example, the storage capacitor Cst may not overlap with the thin film transistor TFT. That is, the lower electrode CE1 of the storage capacitor Cst is a component separated from the gate electrode GE of the thin film transistor TFT and may be provided to be spaced apart from the gate electrode GE of the thin film transistor TFT.

[0071] The upper electrode CE2 may include Al, platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), Mo, Ti, tungsten (W), and / or Cu, and may include a single layer or multiple layers each containing the above materials.

[0072] The third inorganic insulating layer 114 may be located on the upper electrode CE2. The third inorganic insulating layer 114 may cover the upper electrode CE2. The third inorganic insulating layer 114 may include inorganic insulating materials such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO x ). Zinc oxide (ZnO x ) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2). The third inorganic insulating layer 114 may be a single layer or multiple layers each including the above inorganic insulating materials.

[0073] Each of the drain electrode DE and the source electrode SE may be positioned on the third inorganic insulating layer 114. Each of the drain electrode DE and the source electrode SE may be connected to the semiconductor layer Act through contact holes provided in the first inorganic insulating layer 112, the second inorganic insulating layer 113, and the third inorganic insulating layer 114. Each of the drain electrode DE and the source electrode SE may include a material having good electrical conductivity. Each of the drain electrode DE and the source electrode SE may include a conductive material containing Mo, Al, Cu, Ti, etc., and may include a multi-layer or single-layer each containing the above materials. For example, each of the drain electrode DE and the source electrode SE may include a multi-layer structure of Ti / Al / Ti.

[0074] The organic insulating layer OIL may be located on the inorganic insulating layer IIL. The organic insulating layer OIL may include a first organic insulating layer 115 and a second organic insulating layer 116. Figure 2 It is shown that the organic insulating layer OIL includes two organic insulating layers, but the present disclosure is not limited thereto. For example, the organic insulating layer OIL may further include three or four organic insulating layers.

[0075] The first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include an organic insulating material, for example, polymethyl methacrylate (PMMA), a general commercial polymer such as polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a parylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0076] The connection electrode CM may be located on the first organic insulating layer 115. At this time, the connection electrode CM may be connected to the drain electrode DE through a contact hole in the first organic insulating layer 115, but the present disclosure is not limited thereto. For example, the connection electrode CM may be connected to the source electrode SE. The connection electrode CM may include a material having good electrical conductivity. The connection electrode CM may include a conductive material containing Mo, Al, Cu, Ti, etc., and may include a multi-layer or single-layer containing the above materials. For example, the connection electrode CM may have a multi-layer structure of Ti / Al / Ti.

[0077] The second organic insulating layer 116 may be located on the connection electrode CM. The second organic insulating layer 116 may cover the connection electrode CM. The second organic insulating layer 116 may include the same material or a different material from the first organic insulating layer 115.

[0078] The light-emitting diode may be located on the second organic insulating layer 116. For example, an organic light-emitting diode (OLED) may be located on the second organic insulating layer 116. Alternatively, in one or more embodiments, an inorganic light-emitting diode or the like may also be located on the second organic insulating layer 116.

[0079] The organic light-emitting diode (OLED) may emit red, green, or blue light, or may emit red, green, blue, or white light. The organic light-emitting diode (OLED) may include a sub-pixel electrode 211, an intermediate layer 212, a counter electrode 213, and a capping layer 215.

[0080] The sub-pixel electrode 211 may be located on the second organic insulating layer 116. The sub-pixel electrode 211 may be electrically connected to the connection electrode CM through a contact hole defined in the second organic insulating layer 116. The sub-pixel electrode 211 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In one or more embodiments, the sub-pixel electrode 211 may include a reflective film containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. In one or more embodiments, the sub-pixel electrode 211 may further include a film containing ITO, IZO, ZnO, or In2O3 above and / or below the above reflective film. For example, the sub-pixel electrode 211 may have a multi-layer structure of ITO / Ag / ITO.

[0081] The pixel defining layer 118 having an opening exposing at least a portion of the sub-pixel electrode 211 may be located on the sub-pixel electrode 211. The opening defined in the pixel defining layer 118 may define an emission region of light emitted from the organic light-emitting diode (OLED). For example, the width of the opening may correspond to the width of the emission region.

[0082] The pixel defining layer 118 may include an organic insulating material. Alternatively, the pixel defining layer 118 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the pixel defining layer 118 may include an organic insulating material and an inorganic insulating material. In one or more embodiments, the pixel defining layer 118 may include a light-blocking material. The light-blocking material may include carbon black, carbon nanotubes, a resin or slurry containing a black dye, metal (such as nickel, aluminum, molybdenum, or an alloy thereof) particles, metal oxide (such as chromium oxide) particles, or metal nitride (such as chromium nitride) particles, etc. When the pixel defining layer 118 includes a light-blocking material, the reflection of external light caused by the metal structure located on the lower portion of the pixel defining layer 118 may be reduced.

[0083] The spacer can be located on the pixel defining layer 118. The spacer can include an organic insulating material such as polyimide. Alternatively, the spacer can include an inorganic insulating material such as silicon nitride (SiN x ) or silicon oxide (SiO2), or can include an organic insulating material and an inorganic insulating material.

[0084] In one or more embodiments, the spacer can include the same material as the pixel defining layer 118. In this case, the pixel defining layer 118 and the spacer can be formed together in a masking operation using a halftone mask or the like. Alternatively, the spacer can include a material different from that of the pixel defining layer 118.

[0085] The intermediate layer 212 can include an emission layer. For example, the emission layer can be disposed in the opening of the pixel defining layer 118. The emission layer can include a high molecular weight organic material or a low molecular weight organic material that emits light of a corresponding color.

[0086] The intermediate layer 212 can also include functional layers. The functional layers can include a first functional layer and a second functional layer. The first functional layer can be between the sub-pixel electrode 211 and the emission layer, and the second functional layer can be between the emission layer and the counter electrode 213. However, at least one of the first functional layer and the second functional layer can be omitted. Hereinafter, the case where each of the first functional layer and the second functional layer is disposed will be mainly described in detail.

[0087] The first functional layer can include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer can include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0088] The counter electrode 213 can be located on the intermediate layer 212. The counter electrode 213 can include a conductive material having a low work function. For example, the counter electrode 213 can include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), Ca, or an alloy thereof, etc. Alternatively, the counter electrode 213 can also include a layer including, for example, ITO, IZO, ZnO, or In2O3 above the (semi) transparent layer containing the above materials.

[0089] In one or more embodiments, the capping layer 215 can be located on the counter electrode 213. The capping layer 215 can include an inorganic material (such as lithium fluoride (LiF)) and / or an organic material.

[0090] The encapsulation layer 300 may be located on the organic light-emitting diode (OLED). The encapsulation layer 300 may cover the OLED. The encapsulation layer 300 may be located on the counter electrode 213 and / or the capping layer 215. In one or more embodiments, the encapsulation layer 300 may include at least one inorganic film layer and at least one organic film layer. Figure 2 It is shown that the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 that are sequentially stacked.

[0091] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride. Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or a multi-layer each including one or more of the above materials. The organic encapsulation layer 320 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide, or polyethylene, etc. In one or more embodiments, the organic encapsulation layer 320 may include an acrylate.

[0092] The touch sensor layer 400 may be located on the encapsulation layer 300. The touch sensor layer 400 may include a first touch insulating layer 410, a second touch insulating layer 420, a first conductive layer 430, a third touch insulating layer 440, a second conductive layer 450, and a planarization layer 460.

[0093] In one or more embodiments, the first touch insulating layer 410 may be located on the second inorganic encapsulation layer 330, and the second touch insulating layer 420 may be located on the first touch insulating layer 410. In one or more embodiments, each of the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material and / or an organic insulating material. For example, each of the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0094] In one or more embodiments, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 may be omitted. For example, the first touch insulating layer 410 may be omitted. In this case, the second touch insulating layer 420 may be located on the second inorganic encapsulation layer 330, and the first conductive layer 430 may be located on the second touch insulating layer 420.

[0095] The first conductive layer 430 may be located on the second touch insulating layer 420, and the third touch insulating layer 440 may be located on the first conductive layer 430. In one or more embodiments, the third touch insulating layer 440 may include an inorganic insulating material and / or an organic insulating material. For example, the third touch insulating layer 440 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0096] The second conductive layer 450 may be located on the third touch insulating layer 440. The touch electrodes TE of the touch sensor layer 400 may be provided in a structure where the first conductive layer 430 and the second conductive layer 450 are connected. Alternatively, the touch electrodes TE may be formed on any one of the first conductive layer 430 and the second conductive layer 450, and may include metal lines provided in the corresponding conductive layer. Each of the first conductive layer 430 and the second conductive layer 450 may include at least one of Al, Cu, Ti, Mo, and ITO, and may include a single layer or multiple layers each containing the above materials. For example, each of the first conductive layer 430 and the second conductive layer 450 may have a three-layer structure of a titanium layer / aluminum layer / titanium layer.

[0097] In one or more embodiments, the planarization layer 460 may cover the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0098] Figure 3 is a schematic equivalent circuit diagram of any one sub-pixel circuit provided in a display device according to one or more embodiments.

[0099] Referring to Figure 3 , the sub-pixel circuit PC may include a plurality of thin film transistors and at least one capacitor. In one or more embodiments, the sub-pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a storage capacitor Cst.

[0100] Each of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 may be an oxide semiconductor thin film transistor including a semiconductor layer containing an oxide semiconductor or a silicon semiconductor thin film transistor including a semiconductor layer containing polysilicon. Each thin film transistor may include a first electrode and a second electrode, and according to the type of the thin film transistor, the first electrode may be either a source electrode or a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. In addition, each thin film transistor may include a gate electrode.

[0101] The first thin film transistor T1 may be a driving thin film transistor. The first electrode of the first thin film transistor T1 may be connected to a driving voltage line VDL that supplies a driving power supply voltage ELVDD, and the second electrode of the first thin film transistor T1 may be connected to a pixel electrode of the organic light emitting diode OLED (e.g., Figure 2 the sub-pixel electrode 211). The gate electrode of the first thin film transistor T1 may be connected to the first node N1. The first thin film transistor T1 may control the amount of current flowing through the organic light emitting diode OLED from the driving power supply voltage ELVDD in response to the voltage of the first node N1.

[0102] The second thin film transistor T2 may be a switching thin film transistor. The first electrode of the second thin film transistor T2 may be connected to a data line DL, and the second electrode of the second thin film transistor T2 may be connected to the first node N1. The gate electrode of the second thin film transistor T2 may be connected to a scan line SL. When a scan signal is supplied through the scan line SL, the second thin film transistor T2 may be turned on to electrically connect the data line DL and the first node N1 to each other.

[0103] The third thin film transistor T3 may be an initialization thin film transistor and / or a sensing thin film transistor. The first electrode of the third thin film transistor T3 may be connected to a second node N2, and the second electrode of the third thin film transistor T3 may be connected to an initialization voltage line INL. The gate electrode of the third thin film transistor T3 may be connected to the scan line SL.

[0104] When a scan signal is supplied through the scan line SL, the third thin film transistor T3 may be turned on to electrically connect the initialization voltage line INL and the second node N2 to each other. In some embodiments, the third thin film transistor T3 may be turned on in response to a signal received through the scan line SL, such that an initialization voltage from the initialization voltage line INL may initialize the pixel electrode of the organic light emitting diode OLED.

[0105] In some embodiments, when a scan signal is provided through the scan line SL, the third thin film transistor T3 may be turned on to sense characteristic information of the organic light emitting diode OLED. The third thin film transistor T3 may have both of the above functions as an initialization thin film transistor and as a sensing thin film transistor, or may have any one of the above functions. The initialization operation and the sensing operation of the third thin film transistor T3 may be performed separately or simultaneously. When the third thin film transistor T3 has a function as a sensing thin film transistor, the initialization voltage line INL may be named a sensing line.

[0106] The storage capacitor Cst can be connected between a first node N1 and a second node N2. For example, a first capacitor plate of the storage capacitor Cst can be connected to the gate electrode of the first thin-film transistor T1, and a second capacitor plate of the storage capacitor Cst can be connected to the pixel electrode of the organic light-emitting diode OLED.

[0107] The opposite electrode 213 of the organic light-emitting diode OLED (see Figure 2 ) can be connected to a common voltage line VSL that provides a common power supply voltage ELVSS.

[0108] Although the sub-pixel circuit PC described with reference to Figure 3 includes three thin-film transistors and a storage capacitor, the present disclosure is not limited thereto. In one or more other embodiments, the number of thin-film transistors and the number of storage capacitors can be variously changed according to the design of the sub-pixel circuit PC.

[0109] Figure 4 is a schematic cross-sectional view of a display panel according to one or more embodiments. For example, Figure 4 schematically shows Figure 2 an enlarged view of the second organic insulating layer 116, the sub-pixel electrode 211, the pixel defining layer 118, the intermediate layer 212, and the opposite electrode 213 shown in

[0110] Referring to Figure 4 , the sub-pixel electrode 211 can be located on the second organic insulating layer 116 (as used herein, "located on" can mean "above"). The pixel defining layer 118 can be located on the sub-pixel electrode 211. At least a part of the pixel defining layer 118 can be located on the upper surface of the sub-pixel electrode 211. The intermediate layer 212 can be located on the pixel defining layer 118 and the sub-pixel electrode 211. The intermediate layer 212 can include an emission layer and a functional layer.

[0111] In one or more embodiments, a hole H(CA) exposing at least a part of the sub-pixel electrode 211 can be defined in the intermediate layer 212. The hole H(CA) can be arranged adjacent to an edge portion (or side surface portion) of the sub-pixel electrode 211. Further, the hole H(CA) can be formed by concurrently or substantially simultaneously removing at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211.

[0112] The first side surface S1 in the side surface of the hole H(CA) can be adjacent to the edge portion (or side surface portion) of the sub-pixel electrode 211. Since the hole H(CA) is formed by removing at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211, the first side surface S1 adjacent to the edge portion (or side surface portion) of the sub-pixel electrode 211 of the hole H(CA) can be provided as the side surface 118s of the pixel defining layer 118 and the side surface 212s of the intermediate layer 212.

[0113] The hole H(CA) can be formed by irradiating at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211 with the light irradiated by the laser 30 ( Figure 6A of the laser 30), and concurrently or substantially simultaneously removing the irradiated part of the pixel defining layer 118 and the irradiated part of the intermediate layer 212 by the laser 30. The intensity of the light irradiated by the laser 30 can be about 200 mJ / cm 2 or less. When the intensity of the light irradiated by the laser 30 exceeds about 200 mJ / cm 2 the sub-pixel electrode 211 may burst, and defects may occur in the display device. In addition, the wavelength of the light irradiated by the laser 30 is in the ultraviolet region, and particularly can be about 300 nm or more and about 400 nm or less. The laser 30 that irradiates light with a wavelength in the ultraviolet region can be used to efficiently remove at least a part of the pixel defining layer 118 and at least a part of the intermediate layer 212 without damaging the display panel.

[0114] In one or more embodiments, the thickness of the side surface 118s of the pixel defining layer 118 included in the first side surface S1 of the hole H(CA) can be about or less. For example, the thickness of the side surface 118s of the pixel defining layer 118 included in the first side surface S1 of the hole H(CA) can be about or more and about or less.

[0115] When the laser 30 irradiates light with a wavelength in the ultraviolet region and the intensity of the light is about 200 mJ / cm 2 or less, the thickness of the removable parts of the pixel defining layer 118 and the intermediate layer 212 can be about or less. Since the thickness of the intermediate layer 212 is the thickness of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 can be about or less such that a hole H(CA) can be formed by concurrently or substantially simultaneously removing at least a portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a portion of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211. When the thickness of at least a portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 exceeds approximately , it may not be possible to form the hole H(CA) by concurrently or substantially simultaneously removing a portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and a portion of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211.

[0116] In addition, the reflective film of the sub-pixel electrode 211 may include Ag, and layers including a conductive oxide may be located on the lower and upper portions of the reflective film. When the side surface of the sub-pixel electrode 211 is exposed, since the side surface of the reflective film included in the sub-pixel electrode 211 is exposed, in the manufacturing process of the display panel, the reflective film including Ag may be oxidized and the sub-pixel electrode 211 may be dissolved. To reduce or prevent the possibility of dissolution of the sub-pixel electrode 211, the side surface of the reflective film of the sub-pixel electrode 211 can be covered with the pixel defining layer 118. Since the edge portion (or side surface portion) of the sub-pixel electrode 211 can be covered with the pixel defining layer 118, at least a portion of the pixel defining layer 118 adjacent to the edge portion (or side surface portion) of the sub-pixel electrode 211 can also be located on the upper surface of the sub-pixel electrode 211. Accordingly, the thickness of the portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 can be approximately or greater. When the thickness of the portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 is less than approximately , the side surface of the reflective film of the sub-pixel electrode 211 may not be covered with the pixel defining layer 118, and thus the sub-pixel electrode 211 may be dissolved and defects may occur in the display device.

[0117] The second side surface S2 of the hole H(CA) is spaced apart from the first side surface S1 of the hole H(CA) in a first direction (e.g., the x direction or the -x direction). The second side surface S2 can be provided only as the side surface of the intermediate layer 212. For example, the second side surface S2 of the hole H(CA) may not include the side surface of the pixel defining layer 118. Since the hole H(CA) is formed by removing at least a part of the pixel defining layer 118 adjacent to the edge portion (or side surface portion) of the sub-pixel electrode 211 on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 on the upper surface of the sub-pixel electrode 211, the second side surface S2 of the hole H(CA) may not include the side surface of the pixel defining layer 118 and can be provided only as the side surface of the intermediate layer 212.

[0118] The counter electrode 213 may be located on the intermediate layer 212. Since the hole H(CA) is formed by removing at least a part of the pixel defining layer 118 on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 on the upper surface of the sub-pixel electrode 211, at least a part of the sub-pixel electrode 211 may be exposed through the hole H(CA). Therefore, the sub-pixel electrode 211 and the counter electrode 213 may be in contact with each other in the hole H(CA). In other words, the hole H(CA) may be a region where the sub-pixel electrode 211 and the counter electrode 213 are in contact with each other. A common power supply voltage ELVSS may be applied to the sub-pixel electrode 211. In the case of a large display, when power is applied to the sub-pixel circuit PC (see Figure 3 ), an increase in resistance caused by the thin counter electrode 213 may cause a voltage drop (IR drop) phenomenon. By bringing the counter electrode 213 and the sub-pixel electrode 211 to which the common power supply voltage ELVSS is applied into contact with each other, an increase in resistance caused by the thin counter electrode 213 can be compensated, and the reliability of the display device can be ensured.

[0119] The length of the hole H(CA) in the first direction may be about 3 μm or greater and about 15 μm or less. In other words, the length of the region where the sub-pixel electrode 211 and the counter electrode 213 are in contact with each other in the first direction (e.g., the x-direction or the -x direction) may be about 3 μm or greater and about 15 μm or less. The hole H(CA) can be formed by irradiating light to at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211 via a laser and removing the irradiated part of the pixel defining layer 118 and the irradiated part of the intermediate layer 212. When at least a part of the pixel defining layer 118 and at least a part of the intermediate layer 212 are removed by a laser beam, the length of the hole H(CA) that can be formed by the laser beam in the first direction (e.g., the x-direction or the -x direction) may be about 15 μm or less. Further, when the length of the region where the sub-pixel electrode 211 and the counter electrode 213 are in contact with each other in the first direction (e.g., the x-direction or the -x direction) is less than about 3 μm, the region where the sub-pixel electrode 211 and the counter electrode 213 are in contact with each other may be insufficient to compensate for the increase in resistance due to the thin counter electrode 213, and thus may cause defects in the display device.

[0120] Figure 5 is a schematic cross-sectional view of a display panel in the case where the thickness of at least a part of the pixel defining layer located on the upper surface of the sub-pixel electrode exceeds about . Figure 5 is a diagram for describing a comparative example of the effects of one or more embodiments corresponding to Figure 4 .

[0121] Referring to Figure 5 , when the thickness of at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 exceeds about , the hole H(CA) can be formed by removing at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211, and the counter electrode 213 can be located on the sub-pixel electrode 211, and thus, the sub-pixel electrode 211 and the counter electrode 213 can be in contact with each other in the hole H(CA). Since the region where the sub-pixel electrode 211 and the counter electrode 213 are in contact with each other is formed in the region where at least a part of the sub-pixel electrode 211 is exposed by the opening OP of the pixel defining layer 118, it may be difficult to compensate for the increase in resistance of the display device while maintaining the emission region and high resolution of the display device by bringing the counter electrode 213 and the sub-pixel electrode 211 to which the common power supply voltage ELVSS is applied into contact with each other in the hole H(CA).

[0122] Referring to Figure 4, in one or more embodiments, the thickness of at least a portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 may be about or less, such that a hole H(CA) can be formed by irradiating with a laser beam and concurrently or substantially simultaneously removing at least a portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a portion of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211. For example, as Figure 4 shown, since the hole H(CA) is formed in the region 211a (e.g., the region corresponding to the entire upper surface of the sub-pixel electrode 211) up to the portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211, rather than in the region where the sub-pixel electrode 211 is exposed by the opening OP of the pixel defining layer 118 (see Figure 5 ), to ensure the region where the counter electrode 213 and the sub-pixel electrode 211 to which the common power supply voltage ELVSS is applied are in contact with each other, the increase in the resistance of the display device can be compensated while maintaining the emission region and high resolution of the display device, and thus the reliability and quality of the display device can be improved.

[0123] Figure 6A , Figure 7 and Figure 8 are schematic cross-sectional views showing a method of manufacturing a display device. Figure 6B Schematically shows Figure 6A an enlarged view of region A of

[0124] Referring to Figure 6A , Figure 6B , Figure 7 and Figure 8 , the sub-pixel electrode 211 may be located on the second organic insulating layer 116. The pixel defining layer 118 may be located on the sub-pixel electrode 211. The intermediate layer 212 may be located on the sub-pixel electrode 211 and the pixel defining layer 118. The intermediate layer 212 may include an emission layer and a functional layer.

[0125] At least a portion of the pixel defining layer 118 and at least a portion of the intermediate layer 212 may be located on the upper surface of the sub-pixel electrode 211. The hole H(CA) can be formed by irradiating a laser beam to at least a portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a portion of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211 via the laser 30. For example, the hole H(CA) can be formed by concurrently or substantially simultaneously removing a portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and a portion of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211 by the light emitted from the laser 30.

[0126] The intensity of the light irradiated by the laser 30 can be about 200 mJ / cm 2 or less. When the intensity of the light irradiated by the laser 30 exceeds about 200 mJ / cm 2 , the sub-pixel electrode 211 may burst, and defects may occur in the display device. In addition, the wavelength of the light irradiated by the laser 30 is a wavelength in the ultraviolet region, and can be, for example, about 300 nm or more and about 400 nm or less. The laser 30 that irradiates light having a wavelength in the ultraviolet region can be used to efficiently remove at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211 without damaging the lower part of the display panel.

[0127] In one or more embodiments, the thickness t2 of at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 can be about or less. For example, the thickness t2 of the part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 can be about or more and about or less.

[0128] When the laser 30 irradiates light having a wavelength in the ultraviolet region and the intensity of the light is about 200 mJ / cm 2 or less, the thickness of the part of the pixel defining layer 118 and the intermediate layer 212 that can be removed can be about Because the thickness of the intermediate layer 212 is about So the thickness t2 of at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 can be about or less to form the hole H(CA) by concurrently or substantially simultaneously removing at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211 with the laser 30. When the thickness t2 of at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 exceeds about , it may not be possible to form the hole H(CA) by concurrently or substantially simultaneously removing at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211.

[0129] The reflective film of the sub-pixel electrode 211 may include Ag, and a layer including a conductive oxide may be located on the lower and upper portions of the reflective film. When the side surface of the sub-pixel electrode 211 is exposed, since the side surface of the reflective film included in the sub-pixel electrode 211 is exposed, in the manufacturing process of the display panel, the reflective film including Ag may be oxidized, and the sub-pixel electrode 211 may be dissolved. To reduce or prevent the possibility of dissolution of the sub-pixel electrode 211, the side surface of the reflective film of the sub-pixel electrode 211 may be covered with the pixel defining layer 118. Since the edge portion (or side surface portion) of the sub-pixel electrode 211 may be covered with the pixel defining layer 118, at least a part of the pixel defining layer 118 adjacent to the edge portion (or side surface portion) of the sub-pixel electrode 211 may also be located on the upper surface of the sub-pixel electrode 211. Therefore, the thickness t2 of the portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 may be about or greater. When the thickness t2 of the portion of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 is less than about , the side surface of the sub-pixel electrode 211 may not be covered with the pixel defining layer 118, and thus, the sub-pixel electrode 211 may be dissolved and may cause defects in the display device.

[0130] In one or more embodiments, the length t1 in the first direction (e.g., the x direction or the -x direction) of the region where the pixel defining layer 118 is located on the sub-pixel electrode 211 may be about 1 μm or greater. In other words, the length t1 in the first direction (e.g., the x direction or the -x direction) between the end of the sub-pixel electrode 211 and the end of the pixel defining layer 118 above the upper surface of the sub-pixel electrode 211 may be about 1 μm or greater. When the length t1 in the first direction (e.g., the x direction or the -x direction) of the region where the pixel defining layer 118 is located on the sub-pixel electrode 211 is less than about 1 μm, as described above, the side surface of the sub-pixel electrode 211 may not be covered with the pixel defining layer 118, and thus, the sub-pixel electrode 211 may be dissolved in the manufacturing process of the display device and may cause defects in the display device.

[0131] At least a part of the sub-pixel electrode 211 may be exposed by a hole H(CA) defined in at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211. The counter electrode 213 may be located on the sub-pixel electrode 211, and the hole H(CA) may be a region where the sub-pixel electrode 211 and the counter electrode 213 are in contact with each other. The common power supply voltage ELVSS may be applied to the sub-pixel electrode 211. In the case of a large display, when power is applied to the sub-pixel circuit PC (seeFigure 3 ) When the relative electrode 213 is thin, an increase in resistance caused by the thin relative electrode 213 may lead to a voltage drop (IR drop) phenomenon. By bringing the relative electrode 213 and the sub-pixel electrode 211 to which a common power supply voltage ELVSS is applied into contact with each other, an increase in resistance caused by the thin relative electrode 213 can be compensated for, and the reliability of the display device can be ensured.

[0132] The length of the hole H(CA) in the first direction (e.g., the x direction or the -x direction) may be about 3 μm or more and about 15 μm or less. For example, the length of the region where the sub-pixel electrode 211 and the relative electrode 213 are in contact with each other in the hole H(CA) in the first direction (e.g., the x direction or the -x direction) may be about 3 μm or more and about 15 μm or less. The hole H(CA) can be formed by irradiating light to at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211 via the laser 30, and removing the irradiated part of the pixel defining layer 118 and the irradiated part of the intermediate layer 212. When at least a part of the pixel defining layer 118 and at least a part of the intermediate layer 212 are removed by the laser 30, the length of the hole H(CA) that can be formed by the laser 30 in the first direction (e.g., the x direction or the -x direction) may be about 15 μm or less. In addition, when the length of the region where the sub-pixel electrode 211 and the relative electrode 213 are in contact with each other in the first direction (e.g., the x direction or the -x direction) is less than about 3 μm, the region where the sub-pixel electrode 211 and the relative electrode 213 are in contact with each other may be insufficient to compensate for an increase in resistance caused by the thin relative electrode 213, and thus may cause defects in the display device.

[0133] In one or more embodiments, the thickness of at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 may be about or less, such that the hole H(CA) can be formed by irradiating with the laser 30 and concurrently or substantially simultaneously removing at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 and at least a part of the intermediate layer 212 located on the upper surface of the sub-pixel electrode 211. Compared with the case where the thickness of at least a part of the pixel defining layer 118 located on the upper surface of the sub-pixel electrode 211 exceeds about By electrically connecting the relative electrode 213 and the sub-pixel electrode 211 to which a common power supply voltage ELVSS is applied, a voltage drop phenomenon of the display device can be reduced or prevented while maintaining the emission region and high resolution of the display device, and thus the quality and reliability of the display device can be improved.

[0134] According to the above, a display device with improved reliability and quality and a method of manufacturing the display device can be implemented. The scope of the present disclosure is not limited by these effects.

[0135] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of aspects in each embodiment should generally be considered as available for other similar aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims and the functional equivalents of the claims to be included therein.

Claims

1. A display device, wherein, The display device includes: a substrate; a sub-pixel electrode, above the substrate; a pixel defining layer, partially above the sub-pixel electrode; an intermediate layer, partially above the pixel defining layer, and the intermediate layer defines a hole exposing at least a part of the sub-pixel electrode; and a counter electrode, partially above the intermediate layer, wherein a first side surface of the hole adjacent to an edge portion of the sub-pixel electrode includes a side surface of the pixel defining layer and a side surface of the intermediate layer.

2. The display device according to claim 1, wherein The hole corresponds to a region where the sub-pixel electrode and the counter electrode contact each other.

3. The display device according to claim 1, wherein The thickness of the side surface of the pixel defining layer is or less.

4. The display device according to claim 1, wherein The thickness of the side surface of the pixel defining layer is or greater and or less.

5. The display device according to claim 1, wherein, A length of the hole in a first direction is 3 μm or more and 15 μm or less.

6. The display device according to claim 5, wherein, A second side surface of the hole is spaced apart from the first side surface in the first direction, and the second side surface includes only a side surface of the intermediate layer.

7. The display device according to claim 6, wherein, The second side surface of the hole does not include a surface of the pixel defining layer.

8. The display device according to claim 1, wherein, The intermediate layer includes an emission layer and a functional layer.

9. A method of manufacturing a display device, wherein, The method includes: forming a hole by irradiating a laser beam onto the pixel defining layer and the intermediate layer above an upper surface of the sub-pixel electrode; and forming a counter electrode on the sub-pixel electrode, Wherein, the thickness of a part of the pixel defining layer above the sub-pixel electrode is or less.

10. The method according to claim 9, wherein, The thickness of the portion of the pixel defining layer is or greater.

11. The method according to claim 9, wherein, wherein the forming of the hole includes removing another part of the pixel defining layer above the sub-pixel electrode and a part of the intermediate layer above the sub-pixel electrode by irradiating the laser beam.

12. The method according to claim 9, wherein The forming of the hole includes concurrently removing another part of the pixel defining layer above the sub-pixel electrode and a part of the intermediate layer above the sub-pixel electrode by irradiating the laser beam.

13. The method according to claim 9, wherein, The hole corresponds to a region where the sub-pixel electrode and the counter electrode contact each other.

14. The method according to claim 9, wherein, A length of the hole is 3 μm or more and 15 μm or less.

15. The method according to claim 9, wherein A length of a region of the pixel defining layer above the sub-pixel electrode is 1 μm or more.

16. The method according to claim 9, wherein, A length between an end of the sub-pixel electrode and an end of the pixel defining layer above the sub-pixel electrode is 1 μm or more.

17. The method according to claim 9, wherein, The intermediate layer includes an emission layer and a functional layer.

18. The method according to claim 9, wherein, A wavelength of the laser beam corresponds to an ultraviolet region.

19. The method according to claim 9, wherein, The wavelength of the laser beam is 300 nm or more and 400 nm or less.

20. The method according to claim 9, wherein, The intensity of the laser beam is 200 mJ / cm 2 or less.

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