Preparation method of variable resistance type memory and variable resistance type memory

Abstract

The invention relates to the field of semiconductor device preparation, and provides a variable resistance type memory preparation method and a variable resistance type memory, and the method comprises the steps: depositing a first dielectric layer on a substrate; depositing a bottom electrode layer in the bottom electrode through hole; a resistive layer is deposited on the first dielectric layer and the bottom electrode layer, the resistive layer is made of aluminum nitride, a top electrode layer is deposited on the resistive layer, a dielectric mask layer is deposited on the top electrode layer, and a photoresist layer is deposited on the dielectric mask layer; etching the dielectric mask layer and the top electrode layer; the resistive layer is etched; a protective film layer is deposited, a second dielectric layer is deposited on the protective film layer, and a metal groove is formed in the dielectric layer. In order to solve the defects of too high internal voltage and too slow inversion speed of an existing variable resistance type memory, the scheme of the invention is based on a specific process, and aluminum nitride is used for preparing a resistance change layer, so that the problems can be effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular, to a method for manufacturing a resistive random access memory and a resistive random access memory. Background Art

[0002] A resistive random access memory (RRAM) is a new type of non-volatile memory, which has properties such as low power consumption and high-speed rewriting, and thus is widely used in the semiconductor field.

[0003] However, the existing resistive random access memories still have defects that the internal voltage is too high during operation, which may damage the internal components of the memory, affect data reading and writing, and increase power consumption. In addition, the inversion speed of the existing memory from one state to another is too slow, affecting the data reading and writing speed and the overall performance, and cannot meet the needs of users. Summary of the Invention

[0004] The present invention provides a method for manufacturing a resistive random access memory and a resistive random access memory, so as to solve the defects that the internal voltage of the existing resistive random access memory is too high and the inversion speed is too slow. The solution of the present application is based on a specific process and uses aluminum nitride to prepare a resistive change layer, which can effectively solve the above problems.

[0005] The present invention provides a method for manufacturing a resistive random access memory, including:

[0006] Depositing a first dielectric layer on a substrate, wherein a metal via is provided on the substrate, a bottom electrode via is provided on the first dielectric layer, and the position of the bottom electrode via corresponds to the position of the metal via;

[0007] Depositing a bottom electrode layer in the bottom electrode via;

[0008] Depositing a resistive change layer on the first dielectric layer and the bottom electrode layer, the material of the resistive change layer includes aluminum nitride, depositing a top electrode layer on the resistive change layer, depositing a dielectric mask layer on the top electrode layer, and depositing a photoresist layer on the dielectric mask layer;

[0009] Etching the dielectric mask layer and the top electrode layer;

[0010] Etching the resistive change layer;

[0011] Depositing a protective film layer, and depositing a second dielectric layer on the protective film layer, and a metal groove is provided on the dielectric layer.

[0012] According to the method for manufacturing a variable resistive memory provided by the present invention, after etching the photoresist layer and the dielectric mask layer and before etching the resistive change layer, the method further includes:

[0013] Depositing an etching protection film layer on the resistive change layer, the dielectric mask layer, and the photoresist layer.

[0014] According to the method for manufacturing a variable resistive memory provided by the present invention, the etching of the resistive change layer includes:

[0015] Generating a second mask layer based on the dielectric mask layer, the top electrode layer, and the etching protection film layer;

[0016] Applying the second mask layer to etch the resistive change layer.

[0017] According to the method for manufacturing a variable resistive memory provided by the present invention, when applying the second mask layer to etch the resistive change layer, the etching method includes any one or more of ion beam etching and reactive ion etching.

[0018] According to the method for manufacturing a variable resistive memory provided by the present invention, the etching of the resistive change layer includes:

[0019] Over-etching the resistive change layer, and the over-etching amount is 10 to 50 nanometers.

[0020] According to the method for manufacturing a variable resistive memory provided by the present invention, the depositing of the bottom electrode layer in the bottom electrode through hole includes:

[0021] Depositing a bottom electrode material on the first dielectric layer, and the bottom electrode material includes any one or more of tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride;

[0022] Removing the bottom electrode material outside the bottom electrode through hole by applying a chemical mechanical polishing method to form the bottom electrode layer in the bottom electrode through hole.

[0023] According to the method for manufacturing a variable resistive memory provided by the present invention, the method for depositing the bottom electrode layer in the bottom electrode through hole includes physical vapor deposition.

[0024] According to the method for manufacturing a variable resistive memory provided by the present invention, the material of the resistive change layer includes any one or more of scandium element, titanium element, strontium element, yttrium element, lanthanum element, and barium element, and aluminum nitride.

[0025] According to the method for manufacturing a variable resistive memory provided by the present invention, the substrate is a complementary metal oxide semiconductor structure.

[0026] The present invention also provides a variable resistive memory, which is prepared by using the variable resistive memory preparation method described in any of the above embodiments, and at least includes a substrate, a bottom electrode layer, a resistive change layer, a top electrode layer, and a protective film layer. The material of the resistive change layer includes aluminum nitride.

[0027] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the variable resistive memory preparation method described in any of the above is implemented.

[0028] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the variable resistive memory preparation method described in any of the above is implemented.

[0029] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the variable resistive memory preparation method described in any of the above is implemented.

[0030] The variable resistive memory preparation method provided by the present invention can be applied to the preparation of an aluminum nitride-based variable resistive memory. The aluminum nitride-based variable resistive memory applies aluminum nitride in the resistive change layer. Based on the resistive change characteristics of aluminum nitride, the resistive change layer applying aluminum nitride can make the prepared variable resistive memory reduce voltage and increase the inversion speed. However, at the same time, it will also cause the resistive change layer to be difficult to be etched by conventional halogen gases. Based on this, in the solution of the present application, a new preparation method is provided. By providing a through hole communicating with the bottom electrode in the first dielectric layer, and a through hole communicating with the top electrode in the second dielectric layer and the protective film layer at the top, the bottom electrode and the top electrode can achieve current conduction and signal transmission. In addition, the preparation method of the present solution can maximize the protection of the device sidewall through multi-step etching with a protective film, and can effectively avoid that the etching by-products of conventional halogen gases are non-volatile and are likely to deposit on the device sidewall to form a short-circuit channel and a metal pollution source, thereby solving the problem that the resistive change layer is difficult to be etched by conventional halogen gases. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0032] Figure 1 It is one of the flow diagrams of the variable resistive memory preparation method provided by the embodiment of the present invention.

[0033] Figure 2 is one of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0034] Figure 3 is the second of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0035] Figure 4 is the third of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0036] Figure 5 is the fourth of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0037] Figure 6 is the fifth of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0038] Figure 7 is the sixth of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0039] Figure 8 is the seventh of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0040] Figure 9 is the eighth of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0041] Figure 10 is the ninth of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0042] Figure 11 is the tenth of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0043] Figure 12 is the eleventh of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0044] Figure 13 is the twelfth of the schematic structural diagrams of the variable resistive memory provided by the embodiments of the present invention;

[0045] Wherein:

[0046] 1 - Substrate; 2 - Metal via; 3 - First dielectric layer; 4 - Bottom electrode layer;

[0047] 5 - Resistive switching layer; 6 - Top electrode layer; 7 - Protective film layer; 8 - Metal groove

[0048] 9 - Second dielectric layer; 10 - Dielectric mask layer; 11 - Photoresist layer;

[0049] 12 - Etched protective film layer. Detailed implementation manners

[0050] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0051] Figure 1 It is one of the flow schematic diagrams of the method for manufacturing a variable resistive memory provided by an embodiment of the present invention.

[0052] Figure 2 It is one of the structural schematic diagrams of the variable resistive memory provided by an embodiment of the present invention.

[0053] As Figure 1 shown, this embodiment provides a method for manufacturing a variable resistive memory, and the structure of the manufactured variable resistive memory is as Figure 2 shown. The method includes:[[]]

[0054] Step 101, as Figure 3 , Figure 4 and Figure 5 shown, deposit a first dielectric layer 3 on a substrate 1. A metal via 2 is provided on the substrate 1, and a bottom electrode via is provided in the first dielectric layer 3. The position of the bottom electrode via corresponds to the position of the metal via 2.

[0055] The substrate 1 in this embodiment may be a wafer substrate 1, which may carry driving transistors and bottom metal connections and vias. The driving transistor is a core power control element. Generally, the driving transistor includes a drain, a source, a gate, and an insulating layer. During application, by applying a positive voltage to the gate, an electric field effect can be induced, and then a conductive channel can be constructed between the source and the drain to achieve precise control of the current flow direction. During implementation, the driving transistor may be an FDSOI driving transistor, a FinFET driving transistor, a GAA type driving transistor, and an HKMG / Poly SiON type driving transistor, etc.

[0056] The material of the first dielectric layer 3 may be silicon nitride, silicon oxide, or the like.

[0057] Step 102, as Figure 6 and Figure 7 shown, deposit a bottom electrode layer 4 in the bottom electrode via.

[0058] The significance of the bottom electrode vias of the first dielectric layer 3 deposited in the above step 101 corresponding to the metal vias 2 of the substrate 1 is that it can connect the bottom electrode to the metal parts of other external structures to achieve current conduction and change of the resistance state, so as to store and read data. For example, the bottom electrode can be connected to the metal structures such as metal oxide films, bit lines, word lines, and complementary resistive memory elements outside the memory.

[0059] Step 103, as Figure 8 shown, deposit a resistive switching layer 5 on the first dielectric layer 3 and the bottom electrode layer 4. The material of the resistive switching layer 5 includes aluminum nitride. Deposit a top electrode layer 6 on the resistive switching layer 5, deposit a dielectric mask layer on the top electrode layer 6, and deposit a photoresist layer 11 on the dielectric mask layer;

[0060] The resistance of the resistive switching layer 5 can change under certain specific circumstances. For example, the resistance value decreases at high temperatures to achieve the resistive switching function. In this embodiment, by adding aluminum nitride to the preparation material of the resistive switching layer 5, since aluminum nitride is a compound semiconductor material, under high temperature conditions, the resistivity of aluminum nitride may be significantly reduced. For example, when the temperature exceeds 300 degrees Celsius, the resistivity of aluminum nitride may decrease by three orders of magnitude. This resistive switching characteristic gives it unique advantages as the material of the resistive switching layer 5. In addition, aluminum nitride also has a response mechanism under the action of an electric field. For example, electrons inside aluminum nitride will be excited under the action of an electric field to form an electron conduction channel, making the current pass through the material more easily, resulting in a change in the resistance state. And there may be trap energy levels inside aluminum nitride, and the trap energy levels can capture or release electrons under the action of an electric field. During this process, the resistance state of aluminum nitride can be rapidly changed. The grain boundaries of aluminum nitride may also change under the action of an electric field, thus affecting the resistance state. In summary, by adding aluminum nitride to the resistive switching layer 5 in this embodiment, the resistance value of the resistive switching layer 5 can be rapidly changed, that is, the beneficial effect of improving the inversion speed and further improving the read / write speed can be achieved.

[0061] On the other hand, in this embodiment, a top electrode layer 6, a dielectric mask layer, and a photoresist layer 11 are sequentially deposited on the resistive switching layer 5 made of aluminum nitride. The dielectric mask layer can be a dielectric hard mask. The process of depositing the dielectric mask layer can be realized by chemical vapor deposition (CVD). The material of the dielectric mask layer 10 can include any one or a combination of SiOx, SiON, SiNx, and SiC. In practice, the thickness of the dielectric mask layer can be 50 nanometers to 150 nanometers, preferably 100 nanometers. During application, the image of the photoresist can be first transferred onto the dielectric mask layer 10, and then the pattern can be etched onto the resistive switching layer 5 through the dielectric mask layer.

[0062] Step 104, as Figure 9 and Figure 10 shown, etch the dielectric mask layer and the top electrode layer 6;

[0063] In this step, reactive ion etching (RIE) or ion beam etching (IBE) can be used to etch the dielectric mask layer and the top electrode layer 6. Among them, RIE refers to forming plasma by exciting gas molecules through a high-frequency electric field in a vacuum environment. The high-energy ions in the plasma are vertically incident on the sample surface under the action of the electric field, and physical bombardment and chemical reactions occur on the sample surface to achieve precise etching of the material surface. IBE refers to accelerating Ar ions from the ion source to impact the wafer surface, directly knocking out the atoms on the material surface from the lattice to remove the material and achieve etching of the material. In practical applications, both the RIE process and the IBE process have their respective advantages. For example, RIE can achieve a high degree of anisotropic etching, that is, the etching mainly occurs in the direction perpendicular to the sample surface, and the lateral etching is very small. IBE has good anisotropy, thus minimizing the undercut of the underlying material during the etching process.

[0064] In implementation, a columnar hard mask can be formed after etching. The dielectric mask layer can be fully depleted or partially remaining, and finally preferably forms a circle, or can also be an ellipse.

[0065] In implementation, before etching the photoresist layer 11 and the dielectric mask layer, device patterning can be carried out in advance to form a circular array on the device surface. The arrangement of the circular array can be determined according to the storage density and size of the variable resistive memory. Specifically, through technical means such as exposure and development, a specific area of the photoresist layer 11 can be exposed. Then, after removing the photoresist in the exposed area, a specific pattern can be formed on the photoresist layer 11. After that, etching the photoresist layer 11 can transfer the specific pattern to the mask layer to form a hard mask pattern. After removing the excess photoresist, the completed hard mask pattern can be left. Then, further, the pattern of the hard mask can be transferred to the top electrode layer 6 by etching. For example, if wet etching is used, under appropriate etching conditions, the top electrode material can be selectively removed according to the pattern of the hard mask. If dry etching is used, the high-energy ions in the plasma can be used to physically bombard and chemically react with the top electrode layer 6 to achieve the transfer of the hard mask pattern to the top electrode layer 6. In practical applications, after the top electrode etching is completed, the remaining hard mask material can be removed by chemical mechanical polishing.

[0066] Step 105, etch the resistive switching layer 5;

[0067] In this embodiment, a protective etching layer 12 can be deposited on the resistive switching layer 5 first. The protective etching layer 12 can prevent the resistive switching layer 5 from being contaminated by metal sputtering from the top electrode. That is, the protective etching layer 12 mainly serves to protect the resistive switching layer 5.

[0068] In practical applications, a high selectivity process can be selected when etching the resistive switching layer 5 to retain the protective etching layer 12 as much as possible. The high selectivity process means that under the same etching conditions, the etching rate of the material to be etched is higher than that of the protective layer. Using the high selectivity process in this embodiment can accurately etch the resistive switching layer 5 during the etching process.

[0069] Step 106, as Figure 12 and Figure 13 shown, deposit a protective layer and deposit a second dielectric layer 9 on the protective layer. Metal grooves are provided on the dielectric layer.

[0070] The material of the second dielectric layer 9 can be the same as that of the first dielectric layer 3, such as silicon nitride or silicon oxide. The second dielectric layer 9 can act as an inter-metal isolation dielectric layer.

[0071] In practical applications, the material of the protective layer can be non-conductive silicon oxide, silicon nitride, aluminum oxide, etc. The thickness of the protective layer can be 5 nanometers to 20 nanometers.

[0072] The protective layer in this embodiment is mainly a protective film layer, which is used to reduce the wear and damage of the fabricated variable resistive memory during use, and isolate water vapor, oxygen, hydrogen, etc., to improve the reliability of the device.

[0073] As Figure 1 shown, the metal grooves 8 provided on the second dielectric layer 9 can connect the top electrode to the metal parts of other external structures to achieve current conduction and change of the resistance state, so as to store and read data. For example, the top electrode can be connected to the metal structures such as metal oxide films, bit lines, word lines, and complementary resistive memory elements outside the memory.

[0074] In an exemplary embodiment, as Figure 11 shown, after etching the photoresist layer 11 and the dielectric mask layer and before etching the resistive switching layer 5, it further includes:

[0075] Deposit a protective etching layer 12 on the resistive switching layer 5, the dielectric mask layer, and the photoresist layer 11.

[0076] The material of the protective etching layer 12 can also be non-conductive silicon oxide, silicon nitride, aluminum oxide, etc.

[0077] In an exemplary embodiment, etching the resistive layer 5 includes:

[0078] Generating a second mask layer based on the dielectric mask layer, the top electrode layer 6, and the etching protection film layer 12;

[0079] The second mask layer is used to etch the resistive layer 5 .

[0080] In an exemplary embodiment, when the second mask layer is used to etch the resistive layer 5 , the etching method includes any one or more of ion beam etching and reactive ion etching.

[0081] In an exemplary embodiment, etching the resistive layer 5 includes:

[0082] The resistive layer 5 is over-etched, and the amount of over-etching is 10 to 50 nanometers.

[0083] Over-etching refers to an additional etching step performed during the etching process to remove the remaining material after the main etching is completed. The purpose of over-etching is, on the one hand, to remove the remaining material after the main etching to ensure the flatness and cleanliness of the resistive layer 5, and on the other hand, to avoid short circuits or other defects between the remaining materials, thereby improving the overall performance of the prepared variable resistive memory.

[0084] In this embodiment, over-etching can be performed using an etching method consistent with the main etching method, such as ion beam etching or reactive ion etching. The amount of over-etching refers to the depth of the over-etching. In this embodiment, the amount of over-etching can be 10 nanometers to 50 nanometers, preferably 30 nanometers.

[0085] In an exemplary embodiment, the depositing of the bottom electrode layer 4 in the bottom electrode through hole comprises:

[0086] Depositing a bottom electrode material on the first dielectric layer 3, wherein the bottom electrode material includes any one or more of tungsten, titanium, tantalum, tungsten nitride, titanium nitride and tantalum nitride;

[0087] The bottom electrode material outside the bottom electrode through hole is removed by chemical mechanical polishing to form the bottom electrode layer 4 in the bottom electrode through hole.

[0088] The deposition method in this embodiment is mainly intended to deposit a bottom electrode in the bottom electrode through hole. Low-cost and high-efficiency bottom electrode deposition can be achieved by first depositing a large area of ​​bottom electrode material on the first dielectric layer 3 and then removing excess material.

[0089] In implementation, not only can the material of the bottom electrode include any one or more of tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride, but the material used for the top electrode of the variable resistive memory of this solution can also include any one or more of tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride.

[0090] In an exemplary embodiment, the method of depositing the bottom electrode layer 4 in the bottom electrode via hole includes physical vapor deposition.

[0091] In an exemplary embodiment, the material of the resistive change layer 5 includes any one or more of scandium element, titanium element, strontium element, yttrium element, lanthanum element, and barium element, as well as aluminum nitride.

[0092] In implementation, the material of the resistive change layer 5 can be Al 1-x (X) x N or Al 1-x XY x N, where x = 2% - 60%, preferably 10% - 50%, X and Y are selected from Sc, Ti, Sr, Y, La, or Ba, that is, scandium element, titanium element, strontium element, yttrium element, lanthanum element, and barium element, preferably scandium element. The thickness of the resistive change layer 5 can be 10 nm - 50 nm, preferably 30 nm - 50 nm, and further preferably can be 40 nanometers. In this embodiment, by doping the above-mentioned relatively inert metal materials in the aluminum nitride material, the resistive change property of the resistive change layer 5 can be further improved, the inversion speed can be increased, and thus the data reading and writing efficiency of the prepared variable resistive memory can be improved.

[0093] In an exemplary embodiment, the substrate 1 is a complementary metal oxide semiconductor structure.

[0094] Complementary Metal - Oxide - Semiconductor (CMOS) can be based on MOSFET technology. MOSFET acts as a switch or an amplifier, controlling the current flow between the source and the drain according to the amount of voltage applied. MOSFET uses a semiconductor material that conducts electricity under specific conditions and does not conduct electricity under other conditions. CMOS consists of two parts, PMOS and NMOS, which cooperate with each other to form an efficient complementary pair. When the input voltage of the logic circuit changes, the conductivity of PMOS and NMOS also changes, thereby achieving precise control of the output level.

[0095] This application also provides a variable resistive memory prepared by using the variable resistive memory preparation method described in any of the above embodiments. As Figure 2 shown, it at least includes a substrate, a bottom electrode layer, a resistive change layer, a top electrode layer, and a protective film layer, and the material of the resistive change layer includes aluminum nitride.

[0096] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements any one of the above variable resistive memory preparation methods.

[0097] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements any one of the above variable resistive memory preparation methods.

[0098] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements any one of the above variable resistive memory preparation methods.

[0099] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solutions, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiments.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.

Claims

1. A method for preparing a variable resistor type memory, characterized in that, Comprising: Depositing a first dielectric layer on a substrate, wherein a metal via hole is provided on the substrate, a bottom electrode via hole is provided in the first dielectric layer, and the position of the bottom electrode via hole corresponds to the position of the metal via hole; Depositing a bottom electrode layer in the bottom electrode via hole; Depositing a resistive change layer on the first dielectric layer and the bottom electrode layer, the material of the resistive change layer includes aluminum nitride, depositing a top electrode layer on the resistive change layer, depositing a dielectric mask layer on the top electrode layer, and depositing a photoresist layer on the dielectric mask layer; Etching the dielectric mask layer and the top electrode layer; Etching the resistive change layer; Depositing a protective film layer, and depositing a second dielectric layer on the protective film layer, wherein a metal groove is provided on the dielectric layer.

2. The method for preparing a variable resistor type memory according to claim 1, wherein, After etching the photoresist layer and the dielectric mask layer and before etching the resistive change layer, further comprising: Depositing an etching protective film layer on the resistive change layer, the dielectric mask layer and the photoresist layer.

3. The method for manufacturing a variable resistor type memory according to claim 2, characterized in that, The etching of the resistive change layer includes: Generating a second mask layer based on the dielectric mask layer, the top electrode layer, and the etching protective film layer; Etching the resistive change layer by applying the second mask layer.

4. The method for manufacturing a variable resistor type memory according to claim 3, wherein, When etching the resistive change layer by applying the second mask layer, the etching method includes any one or more of ion beam etching and reactive ion etching.

5. The method for preparing a variable resistor type memory according to any one of claims 1-4, characterized in that, The etching of the resistive change layer includes: Over-etching the resistive change layer, and the over-etching amount is 10 to 50 nanometers.

6. The method for manufacturing a variable resistor type memory according to claim 1, wherein, The depositing of the bottom electrode layer in the bottom electrode via hole includes: Depositing a bottom electrode material on the first dielectric layer, and the bottom electrode material includes any one or more of tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride; Removing the bottom electrode material outside the bottom electrode via hole by using a chemical mechanical polishing method to form the bottom electrode layer in the bottom electrode via hole.

7. The method for manufacturing a variable resistor type memory according to claim 1, wherein The method for depositing the bottom electrode layer in the bottom electrode via hole includes physical vapor deposition.

8. The method for manufacturing a variable resistor type memory according to claim 1, characterized in that, The material of the resistive change layer includes any one or more of scandium element, titanium element, strontium element, yttrium element, lanthanum element, and barium element, and aluminum nitride.

9. The method for manufacturing a variable resistor type memory according to claim 1, wherein The substrate is a complementary metal oxide semiconductor structure.

10. A variable resistor type memory, characterized in that, Prepared by using the variable resistive memory preparation method according to any one of claims 1-9, at least including a substrate, a bottom electrode layer, a resistive change layer, a top electrode layer, and a protective film layer, and the material of the resistive change layer includes aluminum nitride.

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