Light-controlled multistage storage memristor and preparation method thereof

Abstract

The invention provides a multi-stage storage memristor device based on light regulation and control, which comprises an upper electrode and a lower electrode, and further comprises a heterostructure positioned between the upper electrode and the lower electrode, and the heterostructure comprises an n-type metal oxide semiconductor film layer and a heavily doped p-type silicon semiconductor layer from top to bottom in sequence. The multi-stage memory memristor is successfully constructed by using a heterostructure, and the regulation and control of the resistance of the device by an optical signal are realized, so that the multi-stage memory characteristic is realized in a single device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor information devices, and mainly relates to a multi-level storage memristive device based on optical regulation and a preparation method thereof. Background Art

[0002] Multi-level cell storage technology is an advanced storage technology, which is of great significance in the field of microelectronics. It can effectively improve the storage density and reduce the storage cost, so it has attracted much attention from researchers and the industrial community. A multi-level storage device can be simply understood as a device that can store multiple charge states. Traditional storage technologies usually store a binary bit (0 or 1) in a single storage cell for data storage, while multi-level cell storage technology allows the storage cell to store multiple charge states, which can represent more data.

[0003] A memristor has the dual characteristics of "memory" and "resistance", and it is also considered to be the fourth basic electronic device in addition to resistors, inductors, and capacitors. Due to its simple structure, low power consumption, fast switching speed, high storage density, etc., it is expected to replace "flash memory" as the next-generation new non-volatile memory. And multi-level storage can greatly increase its storage density without increasing the process complexity, so it has received extensive attention from researchers. At present, the research on multi-level storage based on memristors is still in its infancy, mainly by controlling the magnitude of the limiting current to adjust the resistance value of the low-resistance state, and then realizing multi-level storage. And each resistance value regulation requires re-adjusting the magnitude of the limiting current, which is extremely inconvenient to operate. Therefore, it is of great significance to design and prepare a more flexible and convenient optically regulated multi-level storage device and study the regulation characteristics of the light wavelength on the resistance value.

[0004] The research on optically regulated multi-level storage devices also has some difficulties. First, it is necessary to determine the structure and materials of the device to ensure that the device can have multi-level storage characteristics under light stimulation; second, it is necessary to study the physical model of the multi-level storage device so that it can be accurately regulated under light stimulation; finally, it is also necessary to determine the manufacturing process problems to ensure that the prepared device has good stability and reliability. Summary of the Invention

[0005] The present invention provides a multi-level storage memristive device based on optical regulation and a preparation method thereof, which can greatly improve the flexibility of regulation between different resistance values.

[0006] According to an embodiment of the present invention, a multi-level storage memristive device based on optical regulation includes an upper electrode and a lower electrode, and further includes a heterostructure located between the upper electrode and the lower electrode. The heterostructure is sequentially an n-type metal oxide semiconductor thin film layer and a heavily doped p-type silicon semiconductor layer from top to bottom.

[0007] Preferably, the thickness of the heavily doped p-type silicon semiconductor substrate layer is 0.5 mm, and the resistivity is 0.002 Ω·cm.

[0008] Preferably, the n-type metal oxide semiconductor layer is a ZnO thin film with a thickness of 50 - 100 nm.

[0009] Preferably, the upper electrode is an inert metal Ni with a thickness of 50 - 100 nm.

[0010] Preferably, the lower electrode is metal Al, and the thickness of the lower electrode is 50 - 100 nm.

[0011] The present invention also provides an embodiment, a preparation method of a multi-level storage memristive device based on optical regulation, comprising the following steps:

[0012] Step 1, clean the heavily doped p-type silicon substrate layer to ensure that the surface is clean and free of impurities;

[0013] Step 2, deposit upward on the surface of the silicon substrate by magnetron sputtering to finally obtain a metal oxide semiconductor layer;

[0014] Step 3, use spin coating, exposure, development, and sputtering techniques to prepare a metal upper electrode on the n-type semiconductor layer.

[0015] Step 4, use spin coating, exposure, development, and sputtering techniques to prepare a metal lower electrode on the p-type semiconductor layer.

[0016] The specific conditions of magnetron sputtering in Step 2 are: the sputtering gas is high-purity argon and high-purity oxygen, the gas ratio is argon: oxygen = 5:15, the RF sputtering power is 80 W, the background vacuum is lower than 2.0×10 -4 Pa, and the growth pressure is 3 Pa.

[0017] The specific conditions of magnetron sputtering in Step 3 are: the sputtering gas is high-purity argon, the DC sputtering power is 60 W, the background vacuum is lower than 8.0×10 -4 Pa, and the growth pressure is 1.5 Pa.

[0018] The specific conditions of magnetron sputtering in Step 4 are: the sputtering gas is high-purity argon, the DC sputtering power is 60 W, the background vacuum is lower than 8.0×10 -4 Pa, and the growth pressure is 1.5 Pa.

[0019] Preferably, the sputtering target in Step 2 is a ZnO ceramic target, the sputtering target in Step 3 is a Ni target, and the sputtering target in Step 4 is an Al target.

[0020] Preferably, the temperature of magnetron sputtering in Step 2 is room temperature, the temperature of magnetron sputtering in Step 3 is room temperature, and the temperature of magnetron sputtering in Step 4 is 500 °C.

[0021] Preferably, step three is a Ni thin film, which is distributed in a square array and has a size of 100×100 μm.

[0022] Preferably, step four is an Al thin film, which is distributed in a square array and has a size of 100×100 μm.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. By constructing a p + -Si / n-ZnO heterostructure device, the modulation of the width / height of the potential barrier region of the device is realized by using the excitation of the optical field, and then the regulation of the high-resistance state resistance of the device can be completed to achieve multi-level storage characteristics.

[0025] 2. A physical model of interface potential barrier width modulation is proposed to explain the regulation mechanism of light illumination on the device resistance.

[0026] 3. Compared with the traditional multi-level storage scheme, the present invention designs and prepares a more flexible and convenient light-regulated multi-level storage device. Description of the Drawings

[0027] Figure 1 The I-V curve of the device of the present invention under different illuminations.

[0028] Figure 2 The resistance conversion process of the device of the present invention under different illuminations.

[0029] Figure 3 The retention behavior of the device of the present invention under different illuminations, showing multi-level storage characteristics.

[0030] Figure 4 The schematic diagram of the conversion of different resistance states of the device of the present invention under different illuminations. Detailed Embodiments

[0031] Embodiment

[0032] This embodiment includes a memory device, which includes an upper electrode and a lower electrode, and further includes a heterostructure located between the upper electrode and the lower electrode. The heterostructure includes an n-type metal oxide semiconductor thin film layer and a heavily doped p-type silicon semiconductor layer from top to bottom in sequence.

[0033] First, the lower electrode selects Al metal, which is easier to form an ohmic contact with the p-type Si wafer. The p-type semiconductor is a heavily doped p-type Si wafer. The n-type oxide semiconductor layer selects a ZnO thin film, and the upper electrode selects an inert Ni metal.

[0034] Device fabrication process:

[0035] Select p + -Si wafers were ultrasonically cleaned with acetone, absolute ethanol and deionized water, and then dried with nitrogen and used as substrates. A ZnO thin film with a thickness of 80 nm was grown on the p + -Si substrate by magnetron sputtering. Then, a Ni metal thin film with a thickness of 100 nm was grown on the ZnO thin film as the upper electrode by magnetron sputtering, and an Al metal thin film with a thickness of 100 nm was grown on the p + -Si substrate as the lower electrode.

[0036] Specifically, the specific preparation conditions of the ZnO thin film are as follows: background vacuum: less than 2.0×10 -4 Pa; sputtering gas: high-purity argon and high-purity oxygen, gas ratio of argon: oxygen = 18:2; growth pressure 3 Pa; RF sputtering power: 80 W; sputtering target: ZnO ceramic target; substrate temperature: room temperature.

[0037] The specific preparation conditions of the Ni metal thin film are as follows: background vacuum: less than 8.0×10 -4 Pa; sputtering gas: high-purity argon (Ar); growth pressure 0.6 Pa; DC sputtering power: 60 W; sputtering target: Ni target; substrate temperature: room temperature. The shape is distributed in a square array and the size is 100×100 μm.

[0038] The specific preparation conditions of the Al metal thin film are as follows: background vacuum: less than 8.0×10 -4 Pa; sputtering gas: high-purity argon (Ar); growth pressure 0.6 Pa; DC sputtering power: 60 W; sputtering target: Al target; substrate temperature: 500 °C. The shape is distributed in a square array and the size is 100×100 μm.

[0039] The specific working principle is as follows:

[0040] For the p + -Si / ZnO / Al heterostructure device, due to the difference in the Fermi levels of p + -Si and ZnO, a potential barrier region is formed at the p + -Si / ZnO interface, and the width / height of the potential barrier region determines the value of the device resistance. When an external voltage is applied to the device, under the action of a strong external electric field, a conductive filament composed of oxygen vacancies will be formed in the ZnO, converting the device into a low-resistance state; when an external bias voltage is applied, the conductive filament will also break due to the Joule heat effect, converting the device back into a high-resistance state. Our previous work has demonstrated that p +The conductive filaments at the -Si / ZnO interface are more prone to breakage. Therefore, under different light irradiations, the difference in the number of photo-generated carriers will cause the width / height of the potential barrier region of the device to change, resulting in different high-resistance state resistances. Furthermore, the modulation of the high-resistance state by different illuminations is achieved, that is, a photo-modulated multi-level storage memristive device.

[0041] The following experiments were carried out using the fabricated device:

[0042] Figure 1 Shows the I-V curves of the original p + -Si / ZnO / Al heterostructure device under different light irradiations with a scanning voltage from -5V to 5V. All three curves exhibit rectifying characteristics, indicating the presence of a pn junction. In the dark state, the device has the minimum current value. Under illumination, the device current value increases, and the device has the maximum current value under full-wavelength illumination.

[0043] When the device is in the dark and under different light irradiation conditions, the device has resistive switching characteristics, as Figure 2 shown. It is found that the device has relatively similar turn-on voltages, turn-off voltages, and low resistance values, but there are obvious differences in the high resistance values of the device. In the dark state, the device has the maximum high-resistance state resistance. Under illumination, the high-resistance state resistance of the device decreases, and the device has the minimum resistance value under full-wavelength illumination.

[0044] Figure 3 Shows the distribution diagrams of the high and low resistance states of the device under different test environments. It can be seen that the device has similar low resistance state values under different test environments, but the high resistance state values change more significantly. In the dark state, the device has the maximum high-resistance state resistance. Under illumination, the high-resistance state resistance of the device decreases, and the device has the minimum resistance value under full-wavelength illumination. This indicates that the device realizes multi-level storage under light modulation.

[0045] Figure 4 Shows the schematic diagram of realizing multi-level storage under illumination. Due to the difference in the Fermi levels of p + -Si and ZnO, a potential barrier region will be formed at the p + -Si / ZnO interface. When a forward bias is applied to the device, conductive filaments will be formed in ZnO, and the device is converted to the low-resistance state, as Figure 4 (a) shown. When the voltage is applied to the device again, due to the thermal effect, the conductive filaments are more likely to break at the p + -Si / ZnO interface, and the device is converted to the high-resistance state, as Figure 4 (b) shown. Different illumination conditions can modulate the potential barrier at the p + -Si / ZnO interface, as Figure 4As shown in (c), under the illumination of 360 nm light, the electrons captured by V O will be excited, and V O 2+ (V O →V O 2+ + 2e - ) will be formed on the interface, thereby reducing the width of the barrier region and resulting in a decrease in the high-resistance state resistance of the device; as Figure 4 shown in (d), under full illumination, the electrons captured by V O will be further excited, further reducing the width of the barrier region and resulting in a further decrease in the high-resistance state resistance of the device. Therefore, the device realizes multi-level resistance conversion under different illuminations.

Claims

1. A multi-level storage memristive device based on optical regulation, characterized in that, It includes an upper electrode and a lower electrode, and also includes a heterostructure located between the upper electrode and the lower electrode. The heterostructure is composed of an n-type metal oxide semiconductor thin film layer and a heavily doped p-type silicon semiconductor layer from top to bottom in sequence.

2. The multi-level storage memristive device based on optical regulation according to claim 1, wherein The thickness of the heavily doped p-type silicon semiconductor substrate layer is 0.5 mm, and the resistivity is 0.002 Ω·cm.

3. The multi-level storage memristive device based on optical regulation according to claim 1, characterized in that, The n-type metal oxide semiconductor layer is a ZnO thin film with a thickness of 50 - 100 nm.

4. The optically regulated multi-level storage memristive device according to claim 1, characterized in that, The upper electrode is an inert metal Ni with a thickness of 50 - 100 nm.

5. The multi-level storage memristive device based on optical regulation according to claim 1, wherein The lower electrode is made of metal Al. To achieve ohmic contact with the p + -Si substrate, its thickness is 50 - 100 nm.

6. A preparation method of a multi-level storage memristive device based on optical regulation, characterized in that, It includes the following steps: Step 1: Clean the heavily doped p-type silicon substrate layer to ensure that the surface is clean and free of impurities. Step 2: Use magnetron sputtering to deposit upward on the surface of the silicon substrate to finally obtain a metal oxide semiconductor layer. Step 3: Use spin coating, exposure, development, and sputtering techniques to prepare a metal upper electrode on the n-type semiconductor layer. Step 4: Use spin coating, exposure, development, and sputtering techniques to prepare a metal lower electrode on the p-type semiconductor layer.

7. The preparation method of the multi-level storage memristive device based on optical regulation according to claim 6, wherein, The specific conditions of magnetron sputtering in the second step are as follows: the sputtering gases are high-purity argon and high-purity oxygen, the gas ratio is argon: oxygen = 5:15, the radio frequency sputtering power is 80 W, the background vacuum is lower than 2.0×10 -4 Pa, and the growth pressure is 3 Pa. The specific conditions of magnetron sputtering in the third step are as follows: the sputtering gas is high-purity argon, the DC sputtering power is 60 W, the background vacuum is lower than 8.0×10 - 4 Pa, and the growth pressure is 1.5 Pa. The specific conditions of magnetron sputtering in the fourth step are as follows: the sputtering gas is high-purity argon, the DC sputtering power is 60 W, the background vacuum is lower than 8.0×10 -4 Pa, and the growth pressure is 1.5 Pa.

8. The preparation method of the multi-level storage memristive device based on optical regulation according to claim 6, characterized in that, The sputtering target in Step 2 is a ZnO ceramic target, the sputtering target in Step 3 is a Ni target, and the sputtering target in Step 4 is an Al target.

9. The preparation method of the multi-level storage memristive device based on optical regulation according to claim 6, characterized in that, The temperature of magnetron sputtering in Step 2 and Step 3 is room temperature, and the temperature of magnetron sputtering in Step 4 is 500 °C.

10. The preparation method of the multi-level storage memristive device based on optical regulation according to claim 6, wherein, The metal thin film layer in Step 3 is a Ni thin film, which is distributed in a rectangular array with a size of 100×100 μm; the metal thin film layer in Step 4 is an Al thin film, which is distributed in a rectangular array with a size of 100×100 μm.

Images