Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate (10), a circuit layer (20) and a shading layer (30). The circuit layer (20) includes a detection circuit (50), a scanning signal line (61), a first output signal line (62), a second output signal line (63), and a data signal line (64). The detection circuit (50) comprises a first sub-detection circuit (51) and a second sub-detection circuit (52), the first sub-detection circuit (51) comprises at least one first transistor (70), and the second sub-detection circuit (52) comprises at least one second transistor (80). Grid electrodes (83) of the first transistor (70) and the second transistor (80) are respectively connected with a scanning signal line (61), first poles (81) of the first transistor (70) and the second transistor (80) are respectively connected with a data signal line (64), a second pole (72) of the first transistor (70) is connected with a first output signal line (62), and a second pole (82) of the second transistor (80) is connected with a second output signal line (63). The shading layer (30) is provided with a hollow portion, the orthographic projection of the channel region of the first transistor (70) on the substrate (10) is covered by the orthographic projection of the shading layer (30) on the substrate (10), and the orthographic projection of the channel region of the second transistor (80) on the substrate (10) falls within the orthographic projection of the hollow portion on the substrate (10).

Description

Display substrate and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, display devices such as mobile phones, laptops, and televisions have become necessities in people's work and life. Liquid crystal display devices have become the mainstream display device due to their advantages such as high brightness, vivid colors, and wide viewing angle.

[0003] Summary of the Invention

[0004] The present application provides a display substrate and a display device.

[0005] According to a first aspect of an embodiment of the present application, a display substrate is provided. The display substrate includes:

[0006] substrate;

[0007] a circuit layer located on the substrate, the circuit layer comprising at least one group of detection circuits, scan signal lines, first output signal lines, second output signal lines, and data signal lines, the detection circuit comprising a first sub-detection circuit and a second sub-detection circuit, the first sub-detection circuit comprising at least one first transistor, the second sub-detection circuit comprising at least one second transistor; the first transistor and the second transistor respectively comprising a gate, a first electrode, and a second electrode; the gate of the first transistor and the gate of the second transistor are respectively connected to the scan signal lines, the first electrode of the first transistor and the first electrode of the second transistor are respectively connected to the data signal lines, the second electrode of the first transistor is connected to the first output signal line, and the second electrode of the second transistor is connected to the second output signal line;

[0008] A light-shielding layer is located on a side of the circuit layer away from the substrate, and the light-shielding layer is provided with a hollow portion. The orthographic projection of the channel region of the first transistor on the substrate is covered by the orthographic projection of the light-shielding layer on the substrate, and the orthographic projection of the channel region of the second transistor on the substrate falls within the orthographic projection of the hollow portion on the substrate.

[0009] In one embodiment, the display substrate includes a display area and a peripheral area located on at least one side of the display area; the detection circuit and each signal line connected to the detection circuit are located in the peripheral area;

[0010] The display substrate further includes at least one pin area located in the peripheral area. The pin area is provided with a plurality of pins. The plurality of pins include a plurality of first pins. Signal lines connected to the detection circuit are connected to the first pins.

[0011] In one embodiment, the display substrate further includes a liquid crystal layer located between the circuit layer and the light-shielding layer, the liquid crystal layer including a plurality of liquid crystal molecules; the display substrate further includes at least one row of first sub-pixels located between the detection circuit and the display area, the first sub-pixels including liquid crystal molecules, and the long axis direction of the liquid crystal molecules of the first sub-pixels is perpendicular to the surface of the substrate.

[0012] In one embodiment, the display substrate includes a first electrode layer and a second electrode layer, one of the first electrode layer and the second electrode layer is a pixel electrode layer, and the other is a common electrode layer; the first electrode layer includes a plurality of electrode structures located in the display area, a plurality of electrode blocks located in the peripheral area, and a connecting portion located in the peripheral area, and at least two adjacent electrode blocks located in the same row are electrically connected through the connecting portion; at least one of the signal lines connected to the detection circuit includes the connecting portion and the at least two electrode blocks connected through the connecting portion.

[0013] In one embodiment, the display substrate further includes a liquid crystal layer located between the circuit layer and the light-shielding layer, the liquid crystal layer including a plurality of liquid crystal molecules; the display substrate further includes at least one row of first sub-pixels located between the detection circuit and the display area, the first sub-pixels including liquid crystal molecules, the long axis direction of the liquid crystal molecules of the first sub-pixels being perpendicular to the surface of the substrate; the first sub-pixels including the electrode block.

[0014] In one embodiment, the display substrate further includes a metal layer, which is located between the substrate and the first electrode layer; the metal layer includes a connecting line located in the peripheral area, one end of the connecting line is electrically connected to the signal line including the electrode block, and the other end of the connecting line is used to be electrically connected to the driving chip.

[0015] In one embodiment, a row of electrode blocks is provided on one side of the detection circuit facing the display area and on the other side of the detection circuit away from the display area; in a row of electrode blocks on one side of the detection circuit, at least two electrically connected electrode blocks serve as the first output signal line, and / or at least two electrically connected electrode blocks serve as the second output signal line; in a row of electrode blocks on the other side of the detection circuit, the scanning signal line includes at least two electrically connected electrode blocks. In one embodiment, the shape and area of ​​the electrode blocks are the same as those of the electrode structure, and the spacing between adjacent electrode blocks is the same as the spacing between adjacent electrode structures.

[0016] In one embodiment, the pin area is further provided with a plurality of second pins, and the display substrate further includes a driving signal line extending from the display area to the peripheral area and connected to the second pin; the second electrode layer is a common electrode layer and is located between the first electrode layer and the driving signal line; the second electrode layer is partially located in the peripheral area, and the portion of the second electrode layer located in the peripheral area is electrically connected to the portion located in the display area; the orthographic projection of the portion of the driving signal line located in the peripheral area on the substrate falls within the orthographic projection of the portion of the second electrode layer in the peripheral area on the substrate.

[0017] In one embodiment, the display substrate further includes a common voltage signal line arranged around the display area, the peripheral area includes a first sub-peripheral area, the detection circuit is located in the first sub-peripheral area; the detection circuit is located between the display area and the common voltage signal line.

[0018] In one embodiment, in the same detection circuit, the first sub-detection circuit and the second sub-detection circuit are arranged adjacent to each other; the gate of each first transistor and the gate of each second transistor are connected to the same scanning signal line, and / or the first electrode of each first transistor and the first electrode of each second transistor are connected to the same data signal line.

[0019] In one embodiment, the peripheral area includes a first sub-peripheral area located on one side of the display area; the detection circuit and the pin area are both located in the first sub-peripheral area, and the pin area is located on a side of the detection circuit away from the display area; and the transistors in the same detection circuit are arranged along an extension direction of the first sub-peripheral area;

[0020] The pin area is also provided with a plurality of second pins, and the display substrate also includes a plurality of driving signal lines extending from the display area to the first sub-peripheral area and connected to the second pins; in the same pin area, the plurality of second pins are located between two adjacent first pins; each signal line connected to the same detection circuit is connected to the first pin of the same pin area, and the first pins located on both sides of the plurality of second pins are respectively connected to the signal line; the orthographic projection of a partial section of the signal line connected to each transistor of the same detection circuit on the substrate overlaps with the orthographic projection of the driving signal line on the substrate, and the partial section and the driving signal line are located on different conductive layers.

[0021] In one embodiment, the number of the pin areas located in the first sub-peripheral area is equal to the number of the detection circuits.

[0022] In one embodiment, the peripheral area includes a first sub-peripheral area located on one side of the display area; the detection circuit and the pin area are located in the first sub-peripheral area, and the pin area is located on a side of the detection circuit away from the display area;

[0023] The pin area is also provided with a plurality of second pins, and the display substrate also includes a driving signal line extending from the display area to the first sub-peripheral area and connected to the second pins; in each of the pin areas, the plurality of second pins are arranged adjacent to each other, and the first pin is provided on the side of the plurality of second pins adjacent to the detection circuit; each signal line connected to the same detection circuit is connected to the first pins of the two pin areas adjacent to the detection circuit.

[0024] In one embodiment, the number of the pin areas located in the first sub-peripheral area is M, the number of the detection circuits is N, and M=N+1.

[0025] In one embodiment, the peripheral area includes at least two sub-peripheral areas located on different sides of the display area, the pin area is located in one of the sub-peripheral areas, and the detection circuit is located in the other sub-peripheral area;

[0026] In the same detection circuit, the first transistor and the second transistor are connected to the same scanning signal line and the data signal line, and the signal lines connected to the same detection circuit are connected to the same pin area.

[0027] In one embodiment, the detection circuit and the pin area are located on two opposite sides of the display area; or, the detection circuit and the pin area are located on two adjacent sides of the display area.

[0028] In one embodiment, the display substrate includes a first substrate and a second substrate disposed opposite to each other, the first substrate including the substrate and the circuit layer, and the second substrate including the light-shielding layer; the circuit layer including a first conductive layer, an active layer located on a side of the first conductive layer away from the substrate, and a second conductive layer located on a side of the active layer away from the substrate; the active layer including the channel region; an orthographic projection of one of the hollow portions on the substrate covering a channel region of one of the first transistors within an orthographic projection on the substrate;

[0029] The design length and design width of the channel region respectively satisfy the following formulas:

[0030] In the formula, L1 is the design length of the hollow area, W1 is the design length of the channel area; L2 is the design length of the hollow area, W2 is the design width of the channel area; Tol is the process error when the light shielding layer is patterned to form the hollow area; OL is the alignment error between the active layer and the first conductive layer; n is the number of alignments between the active layer and the first conductive layer, n=1 when the active layer and the first conductive layer are directly aligned, and n=2 when the active layer and the first conductive layer are both aligned with other film layers; TP is the alignment error between the first substrate and the second substrate.

[0031] In one embodiment, in the same detection circuit, the number of the first transistors and the number of the second transistors are both plural. In the same detection circuit, the first transistors are connected in parallel, and the second transistors are connected in parallel.

[0032] In one embodiment, in the same detection circuit, the number of the first transistors is the same as the number of the second transistors.

[0033] In one embodiment, in the same detection circuit, the first transistor and the second transistor are arranged along a row direction.

[0034] According to a second aspect of an embodiment of the present application, a display device is provided, comprising the above-mentioned display substrate.

[0035] In the display substrate and display device provided by the embodiments of the present application, if the orthographic projection of the first transistor of the first sub-detection circuit on the substrate is covered by the orthographic projection of the light-shielding layer on the substrate, ambient light incident on the display substrate cannot be incident on the channel of the first transistor, and the magnitude of the current output by the first output signal line is not affected by the ambient light; if the orthographic projection of the channel of the second transistor of the second sub-detection circuit on the substrate is not covered by the orthographic projection of the light-shielding layer on the substrate, ambient light incident on the display substrate can be incident on the channel region of the second transistor and affect the output current of the second transistor, thereby affecting the magnitude of the current output by the second output signal line. It can be seen that the intensity of the external ambient light can be determined based on the difference between the current output by the first output signal line and the current output by the second output signal line, so that the brightness of the backlight source can be adjusted according to the intensity of the ambient light, which helps to reduce the power consumption of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a partial cross-sectional view of a display substrate provided by an exemplary embodiment of the present application;

[0037] FIG2 is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present application;

[0038] FIG3 is a circuit diagram of a display device in which a display substrate is provided according to an exemplary embodiment of the present application;

[0039] FIG4 is a schematic structural diagram of a display substrate provided by another exemplary embodiment of the present application;

[0040] FIG5 is a schematic structural diagram of a display substrate provided by yet another exemplary embodiment of the present application;

[0041] FIG6 is a schematic structural diagram of a display substrate provided by another exemplary embodiment of the present application;

[0042] FIG7 is a schematic diagram of a partial structure of a peripheral area of ​​a display substrate provided by an exemplary embodiment of the present application;

[0043] FIG8 is a schematic diagram showing the connection between the detection circuit and the pin area in the display substrate shown in FIG2 ;

[0044] FIG9 is a schematic structural diagram of a detection circuit of a display substrate provided by another exemplary embodiment of the present application;

[0045] FIG10 is a schematic diagram showing the connection between the detection circuit and the pin area in the display substrate shown in FIG4 ;

[0046] FIG11 is a schematic diagram of a partial structure of a peripheral area of ​​a display substrate provided by an exemplary embodiment of the present application;

[0047] FIG12 is a schematic diagram of a partial structure of a portion of a first electrode layer located in a peripheral area of ​​a display substrate provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0048] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0049] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0050] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0051] The embodiments of the present application provide a display substrate and a display device. The display substrate and the display device in the embodiments of the present application are described in detail below with reference to the accompanying drawings. The features of the following embodiments may complement or be combined with each other unless they conflict.

[0052] The present invention provides a display substrate. As shown in FIG1 , the display substrate includes a substrate 10, a circuit layer 20, and a light shielding layer 30. The circuit layer 20 is located on the substrate 10. The light shielding layer 30 is located on a side of the circuit layer 20 away from the substrate 10.

[0053] As shown in Figures 2 and 3, the circuit layer 20 includes at least one detection circuit 50, a scan signal line 61, a first output signal line 62, a second output signal line 63, and a data signal line 64. The detection circuit includes a first sub-detection circuit 51 and a second sub-detection circuit 52. The first sub-detection circuit 51 includes at least one first transistor 70, and the second sub-detection circuit 52 includes at least one second transistor 80. The first transistor 70 includes a gate 73, a first electrode 71, and a second electrode 72; the second transistor 80 includes a gate 83, a first electrode 81, and a second electrode 82. The gate 73 of the first transistor 70 and the gate 83 of the second transistor 80 are respectively connected to the scan signal line 61, the first electrode 71 of the first transistor 70 and the first electrode 81 of the second transistor 80 are respectively connected to the data signal line 64, the second electrode 72 of the first transistor 70 is connected to the first output signal line 62, and the second electrode 82 of the second transistor 80 is connected to the second output signal line 63.

[0054] Referring to Figure 9, the light-shielding layer 30 is provided with a plurality of hollow portions 31, the orthographic projection of the channel region of the first transistor 70 on the substrate 10 is covered by the orthographic projection of the light-shielding layer 30 on the substrate 10, and the orthographic projection of the channel region of the second transistor 80 on the substrate 10 falls within the orthographic projection of the hollow region on the substrate 10.

[0055] In the display substrate provided by the embodiment of the present application, the orthographic projection of the first transistor of the first sub-detection circuit on the substrate is covered by the orthographic projection of the light-shielding layer on the substrate, so that the ambient light incident on the display substrate cannot be incident on the channel of the first transistor, and the magnitude of the current output by the first output signal line is not affected by the ambient light; and the orthographic projection of the channel of the second transistor of the second sub-detection circuit on the substrate is not covered by the orthographic projection of the light-shielding layer on the substrate, so that the ambient light incident on the display substrate can be incident on the channel region of the second transistor and affect the output current of the second transistor, thereby affecting the magnitude of the current output by the second output signal line. It can be seen that the intensity of the external ambient light can be determined based on the difference between the current output by the first output signal line and the current output by the second output signal line, so that the brightness of the backlight source can be adjusted according to the intensity of the ambient light, which helps to reduce the power consumption of the display substrate.

[0056] In one embodiment, as shown in FIG3 , the display device on which the display substrate is located includes a first current detection circuit 65, a second current detection circuit 66, and a control circuit 67. The first current detection circuit 65 is connected to the output end of the first output signal line 62, the second current detection circuit 66 is connected to the output end of the second output signal line 63, and the control circuit 67 is connected to the first current detection circuit 65 and the second current detection circuit 66, respectively. The first current detection circuit 65 detects the magnitude of the current output by the first output signal line 62 and outputs it to the control circuit 66; the second current detection circuit 66 detects the magnitude of the current output by the second output signal line 63 and outputs it to the control circuit 67. The control circuit 67 can determine the ambient light intensity based on the difference between the magnitude of the current output by the first current output signal line 62 and the magnitude of the current output by the second current output signal line 63, and adjust the brightness of the backlight source based on the ambient light intensity.

[0057] In one embodiment, as shown in FIG1 , the display substrate includes a first substrate 110 and a second substrate 120 disposed opposite each other, and a liquid crystal layer 42 and a sealant 43 located between the first substrate 110 and the second substrate 120. The first substrate 110 includes the substrate 10 and the circuit layer 20, with the circuit layer 20 located on the side of the substrate 10 facing the second substrate 120. The second substrate 120 includes a substrate 41 and a light shielding layer 30 located on the side of the substrate 41 facing the first substrate 110. The sealant 43 is disposed around the liquid crystal layer 42, adhering the first substrate 110 and the second substrate 120 together via the sealant 43. The liquid crystal layer 42 includes a plurality of liquid crystal molecules 421.

[0058] In one embodiment, the substrate 10 and the substrate 41 may both be flexible substrates or rigid substrates. The substrates 10 and 41 have high light transmittance to reduce light loss when light emitted by the backlight passes through them. The flexible substrate material may include one or more of polyimide, polyethylene terephthalate, polycarbonate, and organic resin materials. The organic resin material may include epoxy resin, triazine, silicone resin, or polyimide. Rigid substrates include any of glass substrates, quartz substrates, and sapphire substrates.

[0059] In one embodiment, the display substrate further includes a first electrode layer and a second electrode layer, one of the first electrode layer and the second electrode layer is a pixel electrode layer, and the other is a common electrode layer. The display substrate may be an ADS (Advanced Super Dimension Switch) display substrate. The ADS display substrate has a fast response speed, and the display screen has bright colors and high saturation. In the ADS display substrate, the pixel electrode layer and the common electrode layer are located on the same side of the liquid crystal layer. For example, the common electrode layer and the pixel electrode layer are both located on the first substrate 110, and are located on the side of the substrate 10 facing the second substrate 120, and the pixel electrode layer and the common electrode layer are arranged opposite to each other.

[0060] In one embodiment, the pixel electrode layer includes a plurality of strip-shaped pixel electrodes, the common electrode layer may be a plate-shaped electrode, and each pixel electrode, the portion of the common electrode layer facing the pixel electrode, and the liquid crystal molecules facing the pixel electrode form a sub-pixel.

[0061] In another embodiment, the pixel electrode layer includes a plurality of strip-shaped pixel electrodes, and the common electrode layer includes a plurality of strip-shaped common electrodes. The pixel electrodes and the common electrodes may extend in the same direction. The pixel electrodes and the strip-shaped common electrodes may correspond one to one, and each pixel electrode, the common electrode corresponding to the pixel electrode, and the liquid crystal molecules located between the pixel electrode and the common electrode form a sub-pixel.

[0062] In one embodiment, the circuit layer 20 may include a plurality of pixel circuits, each corresponding to a sub-pixel, and each pixel circuit drives a corresponding sub-pixel. The pixel circuit may include a plurality of thin film transistors. The pixel circuit may also include a capacitor.

[0063] In one embodiment, the circuit layer 20 includes a first conductive layer, an active film layer located on a side of the first conductive layer away from the substrate, and a second conductive layer located on a side of the active film layer away from the substrate 10. The gate of the first transistor 70 and the gate of the second transistor 80 may be located in the first conductive layer. The first transistor 70 includes an active layer 74 located in the active film layer (see Figure 9), and the second transistor 80 includes an active layer 84 located in the active film layer (see Figure 9). The active layer of each transistor includes a channel region. The first electrode 71 of the first transistor 70, the second electrode 72 of the first transistor 70, the first electrode 81 of the second transistor 80, and the second electrode 82 of the second transistor 80 are respectively located in the second conductive layer. The materials of the first conductive layer and the second conductive layer can both be metal.

[0064] In one embodiment, one of the first and second electrodes is a source electrode, and the other is a drain electrode. The first transistor 70 and the second transistor 80 can be N-type transistors or P-type transistors. The embodiment shown in FIG3 is illustrated by taking the first transistor 70 and the second transistor 80 as an example in which both the first transistor 70 and the second transistor 80 are N-type transistors.

[0065] In some embodiments, the orthographic projection of the light shielding layer 30 on the substrate 10 covers the orthographic projection of the active layer of the first transistor 70 on the substrate 10. Furthermore, the orthographic projection of the light shielding layer 30 on the substrate 10 covers the entire area of ​​the orthographic projection of the first transistor 70 on the substrate 10. This configuration can prevent the metal structure of the first transistor 70 from reflecting light and affecting the display effect of the display substrate.

[0066] In some embodiments, the orthographic projections of the active layers of the second transistors 80 on the substrate 10 may all be located within the orthographic projections of the hollow portions of a light-shielding layer 30 on the substrate 10. The active layers of the second transistors may correspond one to one to the hollow portions, and the orthographic projections of the active layers of the second transistors on the substrate 10 are located within the orthographic projections of the corresponding hollow portions on the substrate 10. By configuring the detection circuit to include a first sub-detection circuit 51 and a second sub-detection circuit 52, the channel region of the first transistor of the first sub-detection circuit is covered by the light-shielding layer, and the channel region of the second transistor of the second sub-detection circuit 52 is not covered by the light-shielding layer, then the ambient light intensity determined based on the difference between the currents output by the first sub-detection circuit and the second sub-detection circuit can improve the accuracy of the determined ambient light intensity relative to a solution in which the detection circuit only includes the second sub-detection circuit.

[0067] In one embodiment, an orthographic projection of one of the hollow portions on the substrate covers an orthographic projection of a channel region of the first transistor on the substrate;

[0068] The design length and design width of the hollow area satisfy the following formula:

[0069] In the formula, L1 is the design length of the hollow area, W1 is the design length of the channel area; L2 is the design length of the hollow area, W2 is the design width of the channel area; Tol is the process error when the light shielding layer is patterned to form the hollow area; OL is the alignment error between the active layer and the first conductive layer; n is the number of alignments between the active layer and the first conductive layer, n=1 when the active layer and the first conductive layer are directly aligned, and n=2 when the active layer and the first conductive layer are both aligned with other film layers; TP is the alignment error between the first substrate and the second substrate.

[0070] The active layer is located on the side of the first conductive layer away from the substrate. If the first conductive layer is used as an alignment mark when preparing the active layer, that is, the active layer and the first conductive layer are directly aligned, then the number of alignments between the active layer and the first conductive layer is n=1; if the first electrode layer is located between the first conductive layer and the substrate, the first electrode layer is used as an alignment mark when preparing the first conductive layer and the active layer, then the number of alignments between the active layer and the first conductive layer is n=2.

[0071] The designed length L1 and the designed width L2 of the hollow area satisfy the above formula, so that the orthographic projection of the channel area of ​​each second transistor on the substrate 10 falls within the orthographic projection of a hollow area on the substrate 10, ensuring that the channel area of ​​the second transistor can receive sufficient light.

[0072] In one embodiment, as shown in Figures 2, 4, and 6, the display substrate includes a display area 101 and a peripheral area 102 located on at least one side of the display area 101. In the embodiments shown in Figures 2, 4, and 6, the peripheral area 102 surrounds the display area 101. The peripheral area 102 includes a first sub-peripheral area 1021, a second sub-peripheral area 1022, a third sub-peripheral area 1023, and a fourth sub-peripheral area 1024. The first sub-peripheral area 1021 is disposed opposite the second sub-peripheral area 1022, and the third sub-peripheral area 1023 is disposed opposite the fourth sub-peripheral area 1024.

[0073] In one embodiment, the detection circuit 50 and the signal lines connected to the detection circuit 50 are all located in the peripheral area 102. The signal lines connected to the detection circuit 50 include the detection circuit 50, the scan signal line 61, the first output signal line 62, the second output signal line 63, and the data signal line 64. With this arrangement, the detection circuit 50 and the signal lines connected to the detection circuit 50 do not occupy space in the display area 101 and do not affect the arrangement of pixel circuits and signal lines in the display area 101.

[0074] In one embodiment, as shown in Figures 2, 4, and 6, the display substrate further includes at least one pin region 90 located in the peripheral region. The pin region 90 is provided with a plurality of pins 701. As shown in Figure 7, the plurality of pins includes a plurality of first pins 91 and a plurality of second pins 92. The pin region 90 may be located in the first sub-peripheral region 1021.

[0075] In one embodiment, as shown in FIG7 , the display substrate further includes a common voltage signal line 94 located on a side of the detection circuit 50 away from the display area 101 . The common voltage signal line 94 is connected to a pin in the pin area to transmit the common voltage signal provided by the driver chip to the common electrode in the display area.

[0076] In one embodiment, the detection circuit 50 is located between the display area and the common voltage signal line 94 .

[0077] In one embodiment, as shown in FIG7 , the display substrate further includes a plurality of diodes 95 and an electrostatic discharge signal line 98 located on a side of the common voltage signal line 94 away from the display area 101. Each driving signal line 68 is connected to the electrostatic discharge signal line 98 via a diode 95. The electrostatic discharge signal line and the common electrode can be connected to the same electrical signal.

[0078] In one embodiment, as shown in FIG8 , the display substrate further includes a plurality of drive signal lines 68 extending from the display area 101 to the peripheral area 102. The signal lines connected to the detection circuit 50 are connected to the first pin 91. Specifically, the scan signal line 61, the first output signal line 62, the second output signal line 63, and the data signal line 64 are connected to the first pin 91, respectively, with different signal lines connected to different first pins 91. The second pin 92 is connected to the drive signal line 68. The drive signal line 68 may be a data signal line for providing a data signal to the pixel circuit. The drive signal line 68 may be located in the second conductive layer.

[0079] In one embodiment, as shown in Figures 2 and 4, each of the detection circuits 50 and each of the pin areas 90 are located in the same sub-peripheral area, and the pin area 90 is located on the side of the detection circuit 50 away from the display area 101. Placing the detection circuit 50 and the pin area 90 in the same sub-peripheral area can make the distance between each detection circuit 50 and the first pin 91 closer, so that the length of the signal line between the detection circuit 50 and the first pin 91 is shorter, which helps to simplify the wiring complexity of the display substrate. Placing the pin area 90 on the side of the detection circuit 50 away from the display area 101 facilitates the connection of the pin 701 of the pin area 90 to the circuit board. In the embodiments shown in Figures 2 and 5, each of the detection circuits 50 and each of the pin areas 90 are located in the first sub-peripheral area 1021.

[0080] In one embodiment, as shown in Figures 5 and 6, the detection circuit 50 and the pin area 90 are located in different sub-peripheral areas. In this way, the space of each sub-peripheral area can be fully utilized, avoiding the problem that the detection circuit 50 and the pin area 90 are located in the same sub-peripheral area, resulting in a larger width of the sub-peripheral area. In the embodiment shown in Figure 5, the detection circuit 50 is located in the second sub-peripheral area 1022, and the pin area 90 is located in the first sub-peripheral area 1021, that is, the detection circuit 50 and the pin area 90 are located on opposite sides of the display area 101. In the embodiment shown in Figure 6, the detection circuit 50 is located in the third sub-peripheral area 1023 and the fourth sub-peripheral area 1024, and the pin area 90 is located in the first sub-peripheral area 1021, that is, the detection circuit 50 and the pin area 90 are located on adjacent sides of the display area 101.

[0081] Furthermore, in the same detection circuit 50, the first transistor 70 and the second transistor 80 are connected to the same scanning signal line 61 and the data signal line 64, and each signal line connected to the same detection circuit 50 is connected to the same pin area 90. Each signal line connected to the detection circuit 50 can be connected to the pin area 90 adjacent thereto.

[0082] In one embodiment, as shown in Figures 2, 4, and 6, the display substrate includes multiple detection circuits 50. With this configuration, the control circuit determines an ambient light intensity based on the current signal output by each detection circuit 50, then determines an average ambient light intensity based on all ambient light intensities. This average ambient light intensity is used as the ambient light intensity to adjust the backlight brightness. This improves the accuracy of the determined ambient light intensity.

[0083] In one embodiment, as shown in FIG3 , the first sub-detection circuit 51 includes a plurality of first transistors 70 connected in parallel, and the second sub-detection circuit 52 includes a plurality of second transistors 80 connected in parallel. This allows the current signals output by the first output signal line 62 and the second output signal line 63 to be larger, thereby reducing the impact of current loss during current signal transmission on current signal accuracy.

[0084] In one embodiment, in the same detection circuit, the number of first transistors 70 in the first sub-detection circuit 51 is the same as the number of second transistors 80 in the second sub-detection circuit 52. In this way, the ambient light intensity can be directly determined based on the difference between the current signal output by the second output signal line and the current signal output by the second output signal line. In other embodiments, in the same detection circuit, the number of first transistors 70 in the first sub-detection circuit 51 and the number of second transistors 80 in the second sub-detection circuit 52 can be different. For example, the number of first transistors 70 in the first sub-detection circuit 51 is X, and the number of second transistors 80 in the second sub-detection circuit 52 is Y, where X≠Y. In this embodiment, the current signal output by the second output signal line can be divided by Y to calculate the average value of the current signal output by each second transistor 80. The average value of the current signal output by the second transistor 80 is then multiplied by X to obtain a current correction value. The ambient light intensity can be determined based on the difference between the current correction value and the current signal output by the first output signal line.

[0085] In one embodiment, the first sub-detection circuit 51 and the second sub-detection circuit 52 are disposed adjacent to each other in the same detection circuit 50. Thus, each first transistor 70 and each second transistor 80 in the same detection circuit 50 can be connected to the same scan signal line and / or the same data signal line, thereby simplifying the wiring of the display substrate.

[0086] In one embodiment, as shown in Figures 7 and 9, in the same detection circuit 50, the gate electrode 73 of each first transistor 70 is connected to the same scanning signal line 61, the first electrode 71 of each first transistor 70 is connected to the same data signal line 64, and the second electrode 72 of each first transistor 70 is connected to the same first output signal line 62. This arrangement helps reduce the number of signal lines in the display substrate and simplifies the wiring of the display substrate.

[0087] In one embodiment, as shown in FIG9 , in the same detection circuit 50, the gate electrode 83 of each second transistor 80 is connected to the same scan signal line 61, the first electrode 81 of each second transistor 80 is connected to the same data signal line 64, and the second electrode 82 of each second transistor 80 is connected to the same second output signal line 63. Such an arrangement helps to reduce the number of signal lines in the display substrate and simplify the wiring of the display substrate. It should be noted that, in the embodiment shown in FIG9 , only a few first transistors 70 and second transistors 80 are illustrated in the same detection circuit. In practice, the number of first transistors 70 and second transistors 80 included in the detection circuit is much larger than the number shown in the figure. For example, the number of first transistors 70 and second transistors 80 in the same detection circuit can be 100.

[0088] 9 , the gate 73 of each first transistor 70 and the gate 83 of each second transistor 80 are connected to the same scanning signal line 61, and / or the first electrode 71 of each first transistor 70 and the first electrode 81 of each second transistor 80 are connected to the same data signal line 64. That is, in the same detection circuit 50, the gate of each first transistor 70 and the gate of each second transistor 80 are connected to the same scanning signal line 61, and the first electrode 71 of the first transistor 70 and the first electrode of the second transistor 80 are connected to different data signal lines 64; or, in the same detection circuit 50, the gate of the first transistor 70 and the gate of the second transistor 80 are connected to different scanning signal lines 61, and the first electrode 71 of the first transistor 70 and the first electrode of the second transistor 80 are connected to the same data signal line 64; or, in the same detection circuit 50, the gate of each first transistor 70 and the gate of each second transistor 80 are connected to the same scanning signal line 61, and the first electrode 71 of the first transistor 70 and the first electrode of the second transistor 80 are connected to the same data signal line 64. This arrangement reduces the number of signal lines connected to the detection circuit 50, thereby reducing the number of first pins 91 in the pin region 90 and simplifying the structural complexity of the display substrate. When the gate 73 of each first transistor 70 and the gate 83 of each second transistor 80 are connected to the same scanning signal line 61, and the first electrode 71 of each first transistor 70 and the first electrode 81 of each second transistor 80 are connected to the same data signal line 64, the number of signal lines connected to the detection circuit 50 can be minimized, effectively reducing the number of first pins 91 in the pin region 90.

[0089] In one embodiment, as shown in FIG. 9 , in the detection circuit 50 , the first transistor 70 and the second transistor 80 are arranged along a row direction.

[0090] In one embodiment, as shown in FIG9 , in the same detection circuit 50 , each first transistor 70 and each second transistor 80 are located in the same row, and each first transistor 70 is arranged adjacent to each other, and each second transistor 80 is arranged adjacent to each other. That is, all the first transistors 70 are located on the same side of each second transistor 80. The gate 73 of each first transistor 70 and the gate 83 of each second transistor 80 are connected to the same scan signal line 61, the first electrode 71 of each first transistor 70 and the first electrode 81 of each second transistor 80 are connected to the same data signal line 64, the second electrode 72 of each first transistor 70 is connected to the same first output signal line 62, and the second electrode 82 of each second transistor 80 is connected to the same second output signal line 63. The first output signal line 62 and the second output signal line 63 can be located in the same conductive layer, for example, the first output signal line 62 and the second output signal line 63 can both be located in the second conductive layer.

[0091] In other embodiments, in the same detection circuit 50, each first transistor 70 and each second transistor 80 are located in the same row, and the first transistors 70 and the second transistors 80 are arranged alternately. Alternatively, in the same detection circuit 50, each first transistor 70 is arranged adjacent to each other and located in the same row; each second transistor 80 is arranged adjacent to each other and located in the same row; and the first transistor 70 and the second transistor 80 are located in different rows.

[0092] In one embodiment, the arrangement direction of the transistors in the detection circuit 50 is the same as the extension direction of the sub-peripheral area in which they are located. This helps to reduce the width of the sub-peripheral area. For example, the detection circuit 50 is located in the first sub-peripheral area 1021, the first transistors 70 in the detection circuit 50 are arranged along the row direction, the second transistors 80 in the detection circuit 50 are arranged along the row direction, and the first sub-peripheral area 1021 extends along the row direction; the first transistors 70 and the second transistors 80 can be located in the same row or in different rows. For example, the detection circuit 50 is located in the third sub-peripheral area 1023, the first transistors 70 in the detection circuit 50 are arranged along the column direction, the second transistors 80 in the detection circuit 50 are arranged along the column direction, and the third sub-peripheral area 1023 extends along the column direction; the first transistors 70 and the second transistors 80 can be located in the same column or in different columns.

[0093] In one embodiment, as shown in Figures 2 and 4, the detection circuit 50 and the pin area 90 are both located in the first sub-peripheral area 1021, and the transistors of the same detection circuit 50 are arranged along the extension direction of the first peripheral area 1021. As shown in Figure 8, the multiple second pins 92 of the same pin area 90 are arranged adjacent to each other, and the multiple second pins 92 are located between two adjacent first pins 91. That is, in the same pin area 90, the multiple second pins 92 are arranged adjacent to each other and are located in the middle area of ​​the pin area 90, and the first pins 91 are distributed in the two edge areas of the pin area 90, and the two edge areas are located on opposite sides of the middle area. As shown in Figure 8, in the same pin area 90, the multiple pins 92 are arranged adjacent to each other, and the first pin 91 is provided on the side of the multiple second pins 92 adjacent to the detection circuit.

[0094] In one embodiment, as shown in FIG7 , each signal line connected to the same detection circuit 50 is connected to the first pin 91 of the same pin area 90, and the first pins 91 on both sides of the plurality of second pins 92 are respectively connected to the signal line; the orthographic projection of a portion of the signal line connected to each transistor of the same detection circuit 50 on the substrate 10 overlaps with the orthographic projection of the drive signal line 68 on the substrate 10, and the portion and the drive signal line 68 are located on different conductive layers. The signal line connected to each transistor of the same detection circuit 50 means that the signal line is connected to all transistors in the same detection circuit 50, and the signal line can be a data signal line 64 or a scan signal line 61. Because the transistors in the same detection circuit are arranged along the extension direction of the first sub-peripheral area 1021, and the first pins 91 are respectively provided on both sides of the multiple second pins 92 of the same pin area 90, when the transistors in the detection circuit 50 are connected to the same scan signal line 61, if the drive signal line 68 and the scan signal line 61 are arranged on the same layer, the drive signal line 68 and the scan signal line 61 will intersect; when the transistors in the detection circuit 50 are connected to the same data signal line 64, if the drive signal line 68 and the data signal line 64 are arranged on the same layer, the drive signal line 68 and the data signal line 64 will intersect. By arranging the said partial sections of the signal lines respectively connected to the transistors in the same detection circuit 50 on different layers from the drive signal line 64, the short circuit problem caused by the crossing of the signal lines can be avoided. In some embodiments, the scan signal line 61 and the data signal line 64 can be located in the first conductive layer, and the drive signal line 68 can be located in the second conductive layer.

[0095] Furthermore, as shown in FIG. 7 , the number of the pin areas 90 located in the first sub-peripheral area is equal to the number of the detection circuits 50 .

[0096] In one embodiment, the connection relationship between the signal lines connected to the detection circuit and the pins of the pin area in the display substrate shown in FIG4 is shown in FIG10 . In each pin area 90, the plurality of second pins 92 are arranged adjacent to each other, and the first pin 91 is provided on the side of the plurality of second pins 92 adjacent to the detection circuit 50. The signal line connected to the same detection circuit 50 is connected to the first pin 91 of the two pin areas 90 adjacent to the detection circuit 50, and the first pin 91 of the pin area 90 is connected to the signal line of the adjacent detection circuit. Because the signal line connected to the same detection circuit 50 is connected to the first pin 91 of the two pin areas 90 adjacent to the detection circuit 50, and is connected to the first pin 91 of the pin area 90 adjacent to the detection circuit 50, the drive signal line 68 connected to the second pin 92 and the signal line connected to the detection circuit will not cross even if they are located on the same conductive layer, making the routing of the signal line connected to the detection circuit more flexible. The signal lines connected to the detection circuit and the drive signal line 68 can be located on the same conductive layer or on different conductive layers. In some embodiments, the scan signal lines 61 may be located in a first conductive layer, and the drive signal lines 68 , the first output signal lines 62 , the second output signal lines 63 , and the data signal lines 64 may all be located in the same conductive layer.

[0097] 4 , the number of the pin areas 90 located in the first sub-peripheral area 1021 is M, the number of the detection circuits 50 is N, and M=N+1. In the embodiment shown in FIG4 , M=5 and N=4.

[0098] In one embodiment, the sub-pixels of the display substrate include a first sub-pixel located in the peripheral area and a second sub-pixel located in the display area of ​​the display substrate. The second sub-pixel in the display area is used to display images. At least one row of first sub-pixels is provided between the detection circuit 50 and the display area 101. The first sub-pixels include liquid crystal molecules, and the long axis direction of the liquid crystal molecules of the first sub-pixels is perpendicular to the surface of the substrate 10. Since the long axis direction of the liquid crystal molecules of the first sub-pixels is perpendicular to the surface of the first substrate 10, the first sub-pixels are not used to display images. In this way, when the light emitted by the backlight source is incident on the display substrate, the boundary of the incident area can be located on the side of the second sub-pixel facing the display area, thereby preventing the light emitted by the backlight source from being incident on the channel area of ​​the second transistor 80. In some embodiments, the long axis direction of the liquid crystal molecules of the first sub-pixel can be perpendicular to the surface of the first substrate 10 by controlling the electrical signal output by the pixel circuit to the pixel electrode of the first sub-pixel. In some embodiments, as shown in FIG7 , the pixel electrode 93 and the detection circuit 50 of the first sub-pixel are respectively located in the first sub-peripheral area 1021. Each row of first sub-pixels includes a plurality of first sub-pixels arranged along the extending direction of the first sub-peripheral area 1021. The display substrate may include, for example, multiple rows of first sub-pixels or only one row of first sub-pixels.

[0099] In one embodiment, as shown in Figures 11 and 12, the first electrode layer 810 includes a plurality of electrode blocks 96 located in the peripheral region and a connecting portion 97 located in the peripheral region. At least two adjacent electrode blocks 96 located in the same row are electrically connected via the connecting portion 97. At least one signal line connected to the detection circuit includes the connecting portion 97 and the at least two electrode blocks 96 connected via the connecting portion 97. In this configuration, the electrode blocks 96 and the connecting portion 97 located in the peripheral region of the first electrode layer 810 serve as signal lines connected to the detection circuit. Compared to a solution in which the signal line is located in the first conductive layer or the second conductive layer, this reduces the number of wiring connections in the first conductive layer and the second conductive layer, thereby increasing the flexibility of the wiring configuration of the first conductive layer and the second conductive layer.

[0100] In one embodiment, the display substrate further includes a metal layer positioned between the substrate and the first electrode layer 810. The metal layer includes a connecting wire positioned in the peripheral region, one end of the connecting wire being electrically connected to a signal wire comprising the electrode block, and the other end of the connecting wire being electrically connected to a driver chip. This configuration reduces the resistance of the connecting wire. The metal layer may be a first conductive layer.

[0101] In one embodiment, a row of electrode blocks 96 is respectively provided on the side of the detection circuit facing the display area and the side of the detection circuit away from the display area. In a row of electrode blocks 96 located on one side of the detection circuit, at least two electrically connected electrode blocks serve as the first output signal line, and / or, at least two electrically connected electrode blocks serve as the second output signal line. In a row of electrode blocks located on the other side of the detection circuit, at least two electrically connected electrode blocks serve as the data signal line. As shown in Figure 12, the electrode blocks 96 in one row of the electrode blocks 96 are connected by a connecting portion 97 to serve as a data signal line 64, and the electrode blocks 96 in another row of the electrode blocks 96 are connected by a connecting portion 97 to serve as a second output signal line 63.

[0102] In one embodiment, the first sub-pixel includes the electrode block 96. The electrode block 96 can be the pixel electrode of the first sub-pixel. With this configuration, the electrode block 96 forming the signal line can be reused as the pixel electrode of the first sub-pixel. This can reduce the width of the peripheral area compared to a solution in which the electrode block forming the signal line and the pixel electrode of the first sub-pixel are separate electrode blocks.

[0103] In one embodiment, the first electrode layer further includes an electrode structure located in the display area, and the electrode structure is a pixel electrode of the second sub-pixel. The shape and area of ​​the electrode block 96 are the same as those of the electrode structure, and the spacing between adjacent electrode structures is the same as the spacing between adjacent electrode blocks 96. In this way, the arrangement of the electrode block 96 can improve the uniformity of the size of the electrode structure located in the display area. In some embodiments, the first electrode layer is a pixel electrode layer, and the electrode structure is also a pixel electrode. In another embodiment, the first electrode is a common electrode layer, and the electrode structure is also a common electrode bar.

[0104] In one embodiment, the second electrode layer is a common electrode layer and is located between the first electrode layer and the drive signal line. A portion of the second electrode layer is located in the peripheral area, and the portion of the second electrode layer located in the peripheral area is electrically connected to the portion located in the display area. The orthographic projection of the portion of the drive signal line located in the peripheral area on the substrate falls within the orthographic projection of the portion of the second electrode layer located in the peripheral area on the substrate. With this configuration, the portion of the second electrode layer located in the peripheral area can shield signal crosstalk between the drive signal line and the electrode block.

[0105] The present application also provides a method for preparing a display substrate. The method comprises the following steps:

[0106] First, a first substrate and a second substrate are formed; the first substrate includes a substrate and a circuit layer located on one side of the substrate; the second substrate includes a substrate and a light shielding layer located on one side of the substrate.

[0107] Subsequently, a sealing glue is provided on one of the first substrate and the second substrate, and a liquid crystal layer is provided on the other substrate. The first substrate and the second substrate are assembled so that the first substrate and the second substrate are bonded together by the sealing glue, and the sealing glue surrounds the liquid crystal layer.

[0108] In one embodiment, the preparation process of the first substrate may include the following steps:

[0109] First, a first conductive layer is formed on a substrate, wherein the first conductive layer includes a gate of a first transistor and a gate of a second transistor;

[0110] Subsequently, a gate insulating layer is formed on a side of the first conductive layer away from the substrate;

[0111] Subsequently, an active film layer is formed on a side of the gate insulating layer away from the substrate, wherein the active film layer includes an active layer of the first transistor and an active layer of the second transistor;

[0112] Subsequently, an interlayer dielectric layer is formed on a side of the active film layer away from the substrate, and a plurality of through holes are formed penetrating the interlayer dielectric layer;

[0113] Subsequently, a second conductive layer is formed on a side of the interlayer dielectric layer away from the substrate, the second conductive layer including a first electrode and a second electrode of the first transistor, and a first electrode and a second electrode of the second transistor, the first electrode and the second electrode of the first transistor being electrically connected to the active layer of the first transistor via a through hole penetrating the interlayer dielectric layer, and the first electrode and the second electrode of the second transistor being electrically connected to the active layer of the second transistor via a through hole penetrating the interlayer dielectric layer;

[0114] Subsequently, a planarization layer is formed on a side of the second conductive layer away from the substrate;

[0115] Subsequently, a first electrode layer is formed on a side of the planarization layer away from the substrate, wherein the first electrode layer includes an electrode structure located in the display area and an electrode block located in the peripheral area;

[0116] Subsequently, a passivation layer is formed on a side of the planarization layer away from the substrate;

[0117] Subsequently, a second electrode layer is formed on a side of the passivation layer away from the substrate.

[0118] An embodiment of the present application further provides a display device, which includes the display substrate described in any of the above embodiments.

[0119] In one embodiment, the display substrate further includes a backlight source, and the backlight source is located on a side of the first substrate away from the second substrate.

[0120] In one embodiment, the display device further includes a flexible circuit board and a driving chip. The flexible circuit board is electrically connected to the pins of the pin area, and the driving chip is electrically connected to the flexible circuit board.

[0121] In one embodiment, the display device further includes a first current detection circuit, a second current detection circuit, and a control circuit, wherein the first current detection circuit and the second current detection circuit may be disposed on a flexible printed circuit board. The control circuit may be a control chip.

[0122] In some embodiments, the display device further includes a housing, and the display substrate is embedded in the housing.

[0123] The display device provided in the embodiments of the present application may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0124] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0125] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0126] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display substrate, characterized in that: The display substrate comprises: substrate; A circuit layer located on the substrate, the circuit layer comprising at least one group of detection circuits, scanning signal lines, first output signal lines, second output signal lines and data signal lines, the detection circuit comprising a first sub-detection circuit and a second sub-detection circuit, the first sub-detection circuit comprising at least one first transistor, the second sub-detection circuit comprising at least one second transistor; the first transistor and the second transistor respectively comprise a gate, a first electrode and a second electrode; the gate of the first transistor and the gate of the second transistor are respectively connected to the scanning signal line, the first electrode of the first transistor and the first electrode of the second transistor are respectively connected to the data signal line, the second electrode of the first transistor is connected to the first output signal line, and the second electrode of the second transistor is connected to the second output signal line; A light-shielding layer is located on a side of the circuit layer away from the substrate, the light-shielding layer is provided with a hollow portion, the orthographic projection of the channel region of the first transistor on the substrate is covered by the orthographic projection of the light-shielding layer on the substrate, and the orthographic projection of the channel region of the second transistor on the substrate falls within the orthographic projection of the hollow portion on the substrate.

2. The display substrate according to claim 1, characterized in that: The display substrate comprises a display area and a peripheral area located at least on one side of the display area; the detection circuit and each signal line connected to the detection circuit are located in the peripheral area; The display substrate further comprises at least one pin region located in the peripheral region, the pin region is provided with a plurality of pins, the plurality of pins comprises a plurality of first pins, and the signal lines connected to the detection circuit are connected to the first pins.

3. The display substrate according to claim 2, characterized in that: The display substrate also includes a liquid crystal layer located between the circuit layer and the light-shielding layer, and the liquid crystal layer includes a plurality of liquid crystal molecules; the display substrate also includes at least one row of first sub-pixels located between the detection circuit and the display area, and the first sub-pixels include liquid crystal molecules, and the long axis direction of the liquid crystal molecules of the first sub-pixels is perpendicular to the surface of the substrate.

4. The display substrate according to claim 2, characterized in that: The display substrate includes a first electrode layer and a second electrode layer, one of the first electrode layer and the second electrode layer is a pixel electrode layer, and the other is a common electrode layer; the first electrode layer includes a plurality of electrode structures located in the display area, a plurality of electrode blocks located in the peripheral area, and a connecting portion located in the peripheral area, and at least two electrode blocks located in the same row and adjacent to each other are electrically connected through the connecting portion; at least one of the signal lines connected to the detection circuit includes the connecting portion and the at least two electrode blocks connected through the connecting portion.

5. The display substrate according to claim 4, characterized in that: The display substrate also includes a liquid crystal layer located between the circuit layer and the light-shielding layer, and the liquid crystal layer includes a plurality of liquid crystal molecules; the display substrate also includes at least one row of first sub-pixels located between the detection circuit and the display area, and the first sub-pixels include liquid crystal molecules, and the long axis direction of the liquid crystal molecules of the first sub-pixels is perpendicular to the surface of the substrate; the first sub-pixels include the electrode block.

6. The display substrate according to claim 4, characterized in that: The display substrate also includes a metal layer, which is located between the substrate and the first electrode layer; the metal layer includes a connecting line located in the peripheral area, one end of the connecting line is electrically connected to the signal line including the electrode block, and the other end of the connecting line is used to be electrically connected to the driving chip.

7. The display substrate according to claim 4, characterized in that: A row of electrode blocks is respectively provided on a side of the detection circuit facing the display area and a side of the detection circuit away from the display area; in a row of electrode blocks located on one side of the detection circuit, at least two electrically connected electrode blocks serve as the first output signal line, and / or, at least two electrically connected electrode blocks serve as the second output signal line; in a row of electrode blocks located on the other side of the detection circuit, the scanning signal line includes at least two electrically connected electrode blocks.

8. The display substrate according to claim 4, characterized in that: The shape and area of ​​the electrode block are the same as those of the electrode structure, and the spacing between adjacent electrode blocks is the same as the spacing between adjacent electrode structures.

9. The display substrate according to claim 4, characterized in that: The pin area is further provided with a plurality of second pins, and the display substrate further comprises a driving signal line extending from the display area to the peripheral area and connected to the second pins; the second electrode layer is a common electrode layer and is located between the first electrode layer and the driving signal line; a portion of the second electrode layer is located in the peripheral area, and a portion of the second electrode layer located in the peripheral area is electrically connected to a portion located in the display area; The orthographic projection of the portion of the driving signal line located in the peripheral area on the substrate falls within the orthographic projection of the portion of the second electrode layer located in the peripheral area on the substrate.

10. The display substrate according to claim 2, characterized in that: The display substrate further includes a common voltage signal line surrounding the display area. The peripheral area includes a first sub-peripheral area. The detection circuit is located in the first sub-peripheral area. The detection circuit is located between the display area and the common voltage signal line.

11. The display substrate according to claim 2, characterized in that: In the same detection circuit, the first sub-detection circuit is arranged adjacent to the second sub-detection circuit; the gate of each of the first transistors and the gate of each of the second transistors are connected to the same scanning signal line, and / or the first electrode of each of the first transistors and the first electrode of each of the second transistors are connected to the same data signal line.

12. The display substrate according to claim 11, characterized in that: The peripheral area includes a first sub-peripheral area located at one side of the display area; the detection circuit and the pin area are both located in the first sub-peripheral area, and the pin area is located at a side of the detection circuit away from the display area; and each transistor in the same detection circuit is arranged along the extension direction of the first sub-peripheral area; The pin area is also provided with a plurality of second pins, and the display substrate also includes a plurality of driving signal lines extending from the display area to the first sub-peripheral area and connected to the second pins; in the same pin area, the plurality of second pins are located between two adjacent first pins; each signal line connected to the same detection circuit is connected to the first pin of the same pin area, and the first pins located on both sides of the plurality of second pins are respectively connected to the signal line; the orthographic projection of a partial section of the signal line connected to each transistor of the same detection circuit on the substrate overlaps with the orthographic projection of the driving signal line on the substrate, and the partial section and the driving signal line are located on different conductive layers.

13. The display substrate according to claim 12, characterized in that: The number of the pin regions located in the first sub-peripheral region is equal to the number of the detection circuits.

14. The display substrate according to claim 11, characterized in that: The peripheral area includes a first sub-peripheral area located at one side of the display area; the detection circuit and the pin area are located in the first sub-peripheral area, and the pin area is located at a side of the detection circuit away from the display area; The pin area is also provided with a plurality of second pins, and the display substrate also includes a driving signal line extending from the display area to the first sub-peripheral area and connected to the second pins; in each of the pin areas, the plurality of second pins are arranged adjacent to each other, and the first pin is provided on the side of the plurality of second pins adjacent to the detection circuit; each signal line connected to the same detection circuit is connected to the first pins of two of the pin areas adjacent to the detection circuit.

15. The display substrate according to claim 14, characterized in that: The number of the pin regions located in the first sub-peripheral region is M, the number of the detection circuits is N, and M=N+1.

16. The display substrate according to claim 2, characterized in that: The peripheral area includes at least two sub-peripheral areas located on different sides of the display area, the pin area is located in one of the sub-peripheral areas, and the detection circuit is located in the other sub-peripheral area; In the same detection circuit, the first transistor and the second transistor are connected to the same scanning signal line and the data signal line, and the signal lines connected to the same detection circuit are connected to the same pin area.

17. The display substrate according to claim 16, characterized in that: The detection circuit and the pin area are located at two opposite sides of the display area; or, the detection circuit and the pin area are located at two adjacent sides of the display area.

18. The display substrate according to claim 1, characterized in that: The display substrate comprises a first substrate and a second substrate arranged opposite to each other, the first substrate comprises the substrate and the circuit layer, and the second substrate comprises the light shielding layer; the circuit layer comprises a first conductive layer, an active layer located on a side of the first conductive layer away from the substrate, and a second conductive layer located on a side of the active layer away from the substrate; the active layer comprises the channel region; an orthographic projection of one of the hollow portions on the substrate covers a channel region of one of the first transistors within an orthographic projection on the substrate; The design length and design width of the channel region satisfy the following formulas respectively: In the formula, L1 is the design length of the hollow area, W1 is the design length of the channel area; L2 is the design width of the hollow area, W2 is the design length of the channel area; Tol is the process error when the light shielding layer is patterned to form the hollow area; OL is the alignment error between the active layer and the first conductive layer; n is the number of alignments between the active layer and the first conductive layer, n=1 when the active layer is directly aligned with the first conductive layer, and n=2 when the active layer and the first conductive layer are both aligned with other film layers; TP is the alignment error between the first substrate and the second substrate.

19. The display substrate according to claim 1, characterized in that: In the same detection circuit, the number of the first transistors and the number of the second transistors are both plural. In the same detection circuit, the first transistors are connected in parallel, and the second transistors are connected in parallel.

20. The display substrate according to claim 19, characterized in that: In the same detection circuit, the number of the first transistors is the same as the number of the second transistors.

21. The display substrate according to claim 19, characterized in that: In the same detection circuit, the first transistor and the second transistor are arranged along a row direction.

22. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 21.

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