Audio switch with turn-off assist with digital interface
By introducing the first transistor and the shutdown auxiliary transistor into the USB-C interface, the gate voltage of the audio transmission transistor is controlled, and the capacitive load sensitivity problem caused by sharing the audio signal source and high-speed digital signaling is solved, and audio transmission with low complexity and low power consumption is achieved, and high bit error rate is reduced.
Patent Information
- Application Number
- CN202380081175.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-11-30
- Filing Date
- 2023-11-22
- Publication Date
- 2025-07-04
AI Technical Summary
In USB-C interfaces, sharing of audio signal sources and high-speed digital signaling may lead to capacitive load sensitivity problems between the audio interface and high-speed digital signaling, resulting in high bit error rates and increased design complexity.
By introducing a first transistor and a shutdown auxiliary transistor into the integrated circuit, the gate voltage of the audio transmission transistor is controlled using resistors and switches, keeping it off in high-speed data operation mode, avoiding the always on of the negative voltage source, reducing power consumption and design complexity.
Effectively isolate capacitive loads in audio interfaces and high-speed data operation modes, reduce high bit error rates, simplify design and reduce power consumption.
Smart Images
Figure CN120266399A_ABST
Abstract
Description
Technical Field
[0001] This application claims the priority and benefit of U.S. Patent Application No. 18 / 072,603, filed on November 30, 2022, the disclosure of which is hereby incorporated by reference in its entirety as set forth below and for all applicable purposes. Technical Field
[0003] This application relates to digital interface switches, and more particularly to improved switches between audio sources and digital interfaces. Background Art
[0004] A common type of digital interface for implementing digital communication between devices is the Universal Serial Bus (USB) interface. There are various types of USB protocols, such as the USB Type-C (USB-C) interface found on smartphones and other digital devices. For example, a smartphone can typically dock with other devices (such as a car or a battery charger (e.g., using the Android Auto system)) through its USB-C port or interface. To minimize the number of ports on a smartphone, another use of the USB-C port is to couple to headphones. In this way, the device does not need to include a separate headphone jack but can be coupled through its USB-C port. Thus, the USB-C port can provide an audio signal to headphones in an audio operation mode or high-speed digital data to some other device in a high-speed data operation mode. This sharing of the audio interface with high-speed digital signaling can be problematic due to the relatively large capacitance of the audio signal source and the associated audio switch. Summary of the Invention
[0005] According to one aspect of the present disclosure, there is provided an integrated circuit including: integrated circuit terminals; an audio transmission transistor having a first drain / source terminal coupled to the integrated circuit terminals; and a first transistor having a first drain / source terminal coupled to the gate of the audio transmission transistor and a second drain / source terminal coupled to the integrated circuit terminals.
[0006] According to another aspect of the present disclosure, there is provided a method of controlling an audio transmission transistor, the method including: during a high-speed data operation mode: coupling the gate of the audio transmission transistor to ground through a resistor; driving a high-speed data signal through an integrated circuit terminal coupled to the audio transmission transistor to charge the integrated circuit terminal with a negative voltage; and coupling the negative voltage through a first transistor coupled between the integrated circuit terminal and the gate of the audio transmission transistor to maintain the audio transmission transistor off during the high-speed data operation mode.
[0007] According to yet another aspect of the present disclosure,
[0008] An integrated circuit is provided that includes: an integrated circuit terminal; an audio source for an audio signal; an audio transmission transistor coupled between the audio source and the integrated circuit terminal; a resistor coupled to ground; a first switch configured to couple the gate of the audio transmission transistor to ground through the resistor during a high-speed data operation mode of the integrated circuit; and a component for coupling negative charge on the integrated circuit terminal to the gate of the audio transmission transistor during the high-speed data operation mode.
[0009] These and other advantageous features can be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 is a high-level block diagram of an integrated circuit including an audio transmission transistor turn-off circuit according to one aspect of the present disclosure.
[0011] Figure 2 is according to one aspect of the present disclosure Figure 1 circuit diagram of the audio transmission transistor turn-off circuit of the integrated circuit.
[0012] Figure 3 is a flowchart of a method for controlling an audio transmission transistor according to one aspect of the present disclosure.
[0013] Figure 4 Illustrates some example electronic devices including an audio transmission transistor turn-off circuit according to one aspect of the present disclosure.
[0014] The specific implementation and its advantages of the present disclosure can be best understood by referring to the following detailed description. It should be understood that like reference numerals are used to identify like elements illustrated in one or more of the drawings. DETAILED DESCRIPTION
[0015] In Figure 1 an integrated circuit 100 is shown, where the integrated circuit terminal DX is used for both an audio operation mode and a high-speed data operation mode. In the following example detailed implementation, the high-speed data operation mode is a USB operation mode, such as a USB-C operation mode, but it should be understood that any suitable high-speed data operation mode can be utilized herein. The USB interface of the integrated circuit 100 includes a data positive (DP) terminal and a data negative (DN) terminal. The DP and DN terminals can also be designated as pins. An external device, such as a user's headset (not illustrated), is coupled to the DP and DN terminals through a USB plug 105.
[0016] In a high-speed data operation mode, a controller (not shown) in integrated circuit 100 closes data switch S1 to couple a data positive input (DPin) signal to the DP terminal. Similarly, the controller closes data switch S3 to couple a data negative input (DNin) signal to the DN terminal. During an audio operation mode, the controller closes audio switch S2 such that a headphone right (HPHR) signal from audio source 110 can be coupled to the DP terminal through switch S2. In the same manner, the controller closes audio switch S4 such that a headphone left (HPHL) signal from audio source 110 can be coupled to the DN terminal through switch S4. During the audio operation mode, data switches S1 and S3 are open. Similarly, audio switches S2 and S4 are open during the high-speed operation mode.
[0017] The data rate in the USB-C protocol for the high-speed data operation mode can be well over one billion bits per second. Such high-speed data transfer is sensitive to the capacitive load of the DP and DN terminals. For example, the DP and DN terminals are typically protected by electrostatic discharge (ESD) diodes, which can capacitively load each of the terminals with dozens of picofarads. Ideally, the closing of audio switches S2 and S4 isolates the DP and DN terminals from any capacitive load from audio source 110. However, audio switches S2 and S4 are typically constructed of n-type metal oxide semiconductor (NMOS) audio transmission transistors. An audio signal such as HPHR or HPHL can oscillate between a positive voltage and a negative voltage. Thus, the direction of the current through the audio transmission transistor can be either toward the integrated circuit terminal or from the integrated circuit terminal. Accordingly, which is the drain of the audio transmission transistor and which is the source of the audio transmission transistor will vary depending on the polarity of the audio signal. Thus, the following discussion will refer to the drain / source terminals of the audio transmission transistor since each such terminal can serve as both a drain and a source. The first drain / source terminal of the audio transmission transistor is coupled to its corresponding terminal, while the second drain / source terminal of the audio transmission transistor is coupled to audio source 110. The USB specification requires that the system be able to support a negative common-mode voltage. Thus, the DP and DN terminals can swing to a negative voltage. If the gate of the transmission transistor is only grounded during the high-speed data operation mode to turn it off, then in the case where the integrated circuit terminal coupled to the transmission transistor is discharged to a negative voltage, the gate-source voltage of the transmission transistor will thus be positive. The resulting gate-source voltage can exceed the threshold voltage of the transmission transistor or be close enough to the threshold voltage such that the transmission transistor becomes conductive or at least slightly conductive. Then, as symbolically illustrated by capacitor C, the corresponding integrated circuit terminal (DP or DN terminal) of the transmission transistor is capacitively loaded by audio source 110. Given the sensitivity of the high-speed data operation mode to the capacitive load of the DP and DN terminals, grounding of the transmission transistor gate can result in an unacceptable high bit error rate.
[0018] To prevent the audio source 110 from capacitively loading the DP and DN terminals during high-speed data operation mode, the gates of the transfer transistors forming the audio switches S2 and S4 can be charged with a negative voltage such as from a -1.8V voltage source (not illustrated). Thus, even when the DN terminal and the DP terminal are negatively discharged by high-speed data signaling, the transfer transistors remain off during high-speed data operation mode. However, the negative voltage source is typically a switched power supply, which consumes power and semiconductor die space and increases design complexity. This negative voltage source is turned on not only during high-speed data operation mode but also during audio operation mode. Disclosed herein is an audio transfer transistor turn-off circuit for an integrated circuit 100 that eliminates the need for such always-on negative voltage source.
[0019] Figure 2 An example audio transfer transistor turn-off circuit 200 is shown in more detail in. The data terminal DP / N is a general representation of the integrated circuit terminals DP or DN. The audio NMOS transfer transistor M1 has a first source / drain terminal coupled to the data terminal. The second source / drain terminal of the transfer transistor M1 is coupled to the audio source 110 ( Figure 1 shown in). In the circuit 200, the audio source is represented by its capacitance C. The audio signal HPRL / L is a general representation of the HPHR or HPHL audio signal. During audio operation mode, a controller (not illustrated) controls the switch S5 to select the switched linearizer 205 coupled to the gate of the audio transfer transistor through the switch S5. The switched linearizer 205 turns on the audio transfer transistor M1 such that the audio signal HPHR / L can be linearly transferred to the DP / N terminal through the audio transfer transistor M1. The switch S5 is also represented as the first switch herein.
[0020] During the high-speed data operation mode, the controller controls switch S5 to alternatively select the terminals of resistor R, and the remaining terminals of this resistor are coupled to ground. Thus, the gate of transistor M1 is coupled to ground through switch S5 and resistor R. However, when a negative voltage data signal conducts through the DP / N terminals, the gate voltage of transistor M1 is not grounded, as will be further explained herein. The integrated circuit terminals DP / N are coupled to a data source (not illustrated) that provides a data input signal (e.g., DPin or DNin as previously discussed) through at least one data transmission transistor 210. Depending on the binary value of the data input signal, the integrated circuit terminals DP / N can be negatively charged during the high-speed data operation mode. To advantageously use this negative voltage of the integrated circuit terminals DP / N to also negatively charge the gate of the audio transmission transistor M1, the turn-off assist NMOS transistor M3 has a first drain / source terminal coupled to the integrated circuit terminals DP / N and a second drain / source terminal coupled to the gate of the audio transmission transistor M1. Note that the coupling of the second drain / source terminal to the gate of the audio transmission transistor M1 can be through NMOS transistor M2, as will be further discussed herein. The turn-off assist transistor M3 is also denoted as the first transistor in this text.
[0021] A sufficient positive voltage (e.g., 1.8V) biases the gate of transistor M2. In this way, transistor M2 is turned on during both the audio operation mode and the high-speed data operation mode. In the audio operation mode, the switch linearizer 205 drives the gate of the audio transmission transistor M1 with a positive voltage such as up to 5.5V. The range of the audio signal voltage can be between approximately 1.4V and -1.4V. In the absence of transistor M2, when the audio signal discharges to -1.4V, the drain-source voltage across the turn-off assist transistor M3 can be approximately 7V. This relatively large drain-source voltage across the turn-off assist transistor M3 may damage the transistor. However, transistor M2 can only transfer its gate voltage of 1.8V minus its threshold voltage to the adjacent second drain / source terminal of the turn-off assist transistor M3. Thus, by including transistor M2, the turn-off assist transistor M3 is protected from damage during the audio operation mode. In an alternative embodiment, if the turn-off assist transistor M3 is enabled to withstand such a large voltage stress, for example, by using an appropriately thick gate oxide, transistor M2 can be eliminated. The turn-off assist transistor M3 and switch S6 (and optionally transistor M2) can be considered to constitute components for coupling the negative charge on the integrated circuit terminals to the gate of the audio transmission transistor during the high-speed data operation mode. Transistor M2 is also denoted as the second transistor in this text. Similarly, switch S6 is also denoted as the second switch in this text.
[0022] During the high-speed data operation mode, the controller controls switch S5 to select to ground. Similarly, the controller controls switch S6 to couple and turn off the gate of auxiliary transistor M3 to select to ground. During the high-speed data operation mode, the base of auxiliary transistor M3 (not shown) is also coupled to ground through switch S6. When auxiliary transistor M3 is turned on, resistor R and the on-resistances of transistor M2 and auxiliary transistor M3 then form a resistive voltage divider for the negative voltage of integrated circuit terminals DP / N. When the high-speed data signal swings to a negative voltage (such as approximately -250 mV), the gate-source voltage of auxiliary transistor M3 is charged to approximately 250 mV, which is greater than the threshold voltage of auxiliary transistor M3 of approximately 100 mV to 200 mV. Therefore, auxiliary transistor M3 is turned on, such that integrated circuit terminals DP / N are coupled to the gate of the audio transmission transistor through the voltage divider formed by resistor R and the on-resistances of transistor M2 and auxiliary transistor M3. Accordingly, the gate voltage of audio transmission transistor M1 is negatively discharged, such as to -150 mV to -200 mV, while integrated circuit terminals DP / N are negatively charged. Regardless of the exact value of the negative voltage of the data signaling used in any particular high-speed data operation mode, the gate voltage of audio transmission transistor M1 will be pulled to a significant proportion of that negative voltage. In this way, during the high-speed data operation mode, audio transmission transistor M1 is stably held off, such that integrated circuit DP / N is not loaded by the capacitance from the audio source. Therefore, the high-speed data operation mode can be practiced without the cost and complexity of a constantly-on negative voltage source.
[0023] To prevent transistor M2 and auxiliary transistor M3 from affecting the audio signaling through integrated circuit terminals DP / N, switch S6 couples the gate (and its base) of auxiliary transistor M3 to a -1.8V voltage source during the audio operation mode. The -1.8V voltage source can be activated only during the audio operation mode because it is not needed during the high-speed data operation mode. In this way, the audio transmission transistor turn-off circuit 200 is not affected by the power consumption and complexity of a constantly-on negative voltage source. The -1.8V voltage source can be constructed using a switched power converter or a switched capacitor circuit. When the gate of auxiliary transistor M3 is coupled to the -1.8V voltage source, even if the audio signal swings the voltage of integrated circuit terminals DP / N to a negative value (such as -1.4V), the gate-source voltage of auxiliary transistor M3 still remains negative. Therefore, auxiliary transistor M3 is stably held off during the audio operation mode, such that it does not affect the audio signaling through integrated circuit terminals DP / N. Both transistor M2 and auxiliary transistor M3 can be thick gate oxide devices to protect them from any voltage stress during the high-speed data and audio operation modes.
[0024] Now, a method for controlling an audio transmission transistor according to the present disclosure will be discussed with respect to the flowchart of Figure 3 . The method is performed during a high-speed data operation mode and includes an action 300 of coupling the gate of the audio transmission transistor to ground through a resistor. An example of action 300 is coupling the gate of the audio transmission transistor M1 to ground through a switch S5 and a resistor R. The method further includes an action 305 of driving a high-speed data signal through an integrated circuit terminal coupled to the audio transmission transistor to charge the integrated circuit terminal with a negative voltage. An example of action 305 is the negative charging of the integrated circuit terminals DP, DN (or general DP / N terminals). Finally, the method includes an action 310 of coupling a negative voltage through a first transistor coupled between the integrated circuit terminal and the gate of the audio transmission transistor to maintain the audio transmission transistor off during the high-speed data operation mode. An example of action 310 is the coupling of the turn-off assist transistor M3.
[0025] The audio transmission transistor turn-off circuit as disclosed herein can be incorporated into any suitable mobile device or electronic system. For example, as Figure 4 shown, a cellular phone 400, a laptop computer 405, and a tablet PC 410 can all include an audio transmission transistor turn-off circuit according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with an audio transmission transistor turn-off circuit constructed according to the present disclosure.
[0026] The present disclosure will now be outlined in the following series of clauses:
[0027] Clause 1. An integrated circuit, the integrated circuit comprising:
[0028] An integrated circuit terminal;
[0029] An audio transmission transistor having a first drain / source terminal coupled to the integrated circuit terminal; and
[0030] A first transistor having a first drain / source terminal coupled to the gate of the audio transmission transistor and having a second drain / source terminal coupled to the integrated circuit terminal.
[0031] Clause 2. The integrated circuit according to Clause 1, the integrated circuit further comprising:
[0032] A resistor coupled to ground; and
[0033] A first switch configured to couple the gate of the audio transmission transistor to ground through the resistor during a high-speed data operation mode of the integrated circuit.
[0034] Clause 3. The integrated circuit according to Clause 2, the integrated circuit further comprising:
[0035] A switched linearizer circuit, wherein the first switch is further configured to couple the gate of the audio transmission transistor to the switched linearizer circuit during the audio operation mode of the integrated circuit.
[0036] Clause 4. The integrated circuit according to any one of Clauses 2 to 3, the integrated circuit further comprising:
[0037] A second switch configured to couple the gate of the first transistor to ground during the high-speed data operation mode.
[0038] Clause 5. The integrated circuit according to Clause 4, the integrated circuit further comprising:
[0039] A negative voltage source, wherein the second switch is further configured to couple the gate of the first transistor to the negative voltage source during the audio operation mode of the integrated circuit.
[0040] The gate of the first transistor to the negative voltage source.
[0041] Clause 6. The integrated circuit according to any one of Clauses 1 to 5, the integrated circuit further comprising:
[0042] An audio source for an audio signal, the audio source being coupled to a second drain / source terminal of the audio transmission transistor.
[0043] Clause 7. The integrated circuit according to any one of Clauses 1 to 6, the integrated circuit further comprising:
[0044] A second transistor, wherein a second drain / source terminal of the first transistor is coupled to the integrated circuit terminal through the second transistor.
[0045] Clause 8. The integrated circuit according to claim 7, wherein the gate of the second transistor is biased with a positive voltage so as to be conductive during both the audio operation mode of the integrated circuit and the high-speed data operation mode of the integrated circuit.
[0046] Clause 9. The integrated circuit according to any one of Clauses 1 to 8, wherein the first transistor and the audio transmission transistor each comprise an n-type metal oxide semiconductor (NMOS) transistor.
[0047] Clause 10. The integrated circuit according to any one of Clauses 1 to 9, wherein the integrated circuit terminal is a data terminal of a universal serial bus (USB) interface of the integrated circuit.
[0048] Clause 11. The integrated circuit according to Clause 10, wherein the USB interface is a USB-C interface.
[0049] Clause 12. The integrated circuit according to any one of Clauses 1 to 11, wherein the integrated circuit is included within a cellular phone.
[0050] Clause 13. The integrated circuit according to Clause 7, wherein the first transistor and the second transistor are each a thick gate oxide NMOS transistor.
[0051] Clause 14. A method of controlling an audio transmission transistor, the method comprising:
[0052] During a high-speed data operation mode:
[0053] Coupling the gate of the audio transmission transistor to ground through a resistor;
[0054] Driving a high-speed data signal through an integrated circuit terminal coupled to the audio transmission transistor to charge the integrated circuit terminal with a negative voltage; and
[0055] Coupling the negative voltage through a first transistor coupled between the integrated circuit terminal and the gate of the audio transmission transistor to maintain the audio transmission transistor off during the high-speed data operation mode.
[0056] Clause 15. The method according to Clause 14, the method further comprising:
[0057] During the high-speed data operation mode, grounding the gate of the first transistor.
[0058] Clause 16. The method according to Clause 14, the method further comprising:
[0059] During an audio operation mode, coupling the gate of the audio transmission transistor to a switched linearizer circuit, and
[0060] During the audio operation mode, driving an audio signal to the integrated circuit terminal through the audio transmission transistor.
[0061] Clause 17. The method according to Clause 16, the method further comprising:
[0062] During the audio operation mode, biasing the gate of the first transistor with a negative voltage.
[0063] Clause 18. An integrated circuit, the integrated circuit comprising:
[0064] Integrated circuit terminals;
[0065] An audio source of an audio signal;
[0066] An audio transmission transistor coupled between the audio source and the integrated circuit terminal;
[0067] A resistor coupled to ground;
[0068] A first switch configured to couple the gate of the audio transmission transistor to ground through the resistor during a high-speed data operation mode of the integrated circuit; and
[0069] A component for coupling a negative charge on the integrated circuit terminal to the gate of the audio transmission transistor during the high-speed data operation mode.
[0070] Clause 19. The integrated circuit according to clause 18, the integrated circuit further comprising:
[0071] A switched linearizer circuit, wherein the first switch is further configured to couple the gate of the audio transmission transistor to the switched linearizer circuit during an audio operation mode of the integrated circuit.
[0072] Clause 20. The integrated circuit according to any one of clauses 18 to 19, wherein the audio source has a capacitance, and wherein the component for coupling the negative charge is configured to substantially isolate the integrated circuit terminal from the capacitance during the high-speed data operation mode.
[0073] It should be understood that many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific embodiments illustrated and described herein (since they are only some examples of the present disclosure), but should be fully equivalent to the following appended claims and their functional equivalents.
Claims
1. An integrated circuit, the integrated circuit comprising: Integrated circuit terminals; An audio transmission transistor having a first drain / source terminal coupled to the integrated circuit terminals; And A first transistor having a first drain / source terminal coupled to the gate of the audio transmission transistor and having a second drain / source terminal coupled to the integrated circuit terminals.
2. The integrated circuit according to claim 1, the integrated circuit further comprising: A resistor coupled to ground; And A first switch configured to couple the gate of the audio transmission transistor to ground through the resistor during a high-speed data operation mode of the integrated circuit.
3. The integrated circuit according to claim 2, the integrated circuit further comprising: A switch linearizer circuit, wherein the first switch is further configured to couple the gate of the audio transmission transistor to the switch linearizer circuit during an audio operation mode of the integrated circuit.
4. The integrated circuit according to claim 2, the integrated circuit further comprising: A second switch configured to couple the gate of the first transistor to ground during the high-speed data operation mode.
5. The integrated circuit according to claim 4, the integrated circuit further comprising: A negative voltage source, wherein the second switch is further configured to couple the gate of the first transistor to the negative voltage source during an audio operation mode of the integrated circuit.
6. The integrated circuit according to claim 1, the integrated circuit further comprising: An audio source of an audio signal, the audio source coupled to a second drain / source terminal of the audio transmission transistor.
7. The integrated circuit according to claim 1, the integrated circuit further comprising: A second transistor, wherein the second drain / source terminal of the first transistor is coupled to the integrated circuit terminals through the second transistor.
8. The integrated circuit according to claim 7, wherein the gate of the second transistor is biased with a positive voltage so as to be conductive during both an audio operation mode of the integrated circuit and a high-speed data operation mode of the integrated circuit.
9. The integrated circuit according to claim 1, wherein the first transistor and the audio transmission transistor each comprise an n-type metal oxide semiconductor (NMOS) transistor.
10. The integrated circuit according to claim 1, wherein the integrated circuit terminals are data terminals of a universal serial bus (USB) interface of the integrated circuit.
11. The integrated circuit according to claim 10, wherein the USB interface is a USB-C interface.
12. The integrated circuit according to claim 1, wherein the integrated circuit is included within a cellular phone.
13. The integrated circuit according to claim 7, wherein the first transistor and the second transistor are each a thick gate oxide NMOS transistor.
14. A method of controlling an audio transmission transistor, the method comprising: During a high-speed data operation mode: Coupling the gate of the audio transmission transistor to ground through a resistor; Drive a high-speed data signal through an integrated circuit terminal coupled to the audio transmission transistor to charge the integrated circuit terminal with a negative voltage; and Couple the negative voltage through a first transistor coupled between the integrated circuit terminal and the gate of the audio transmission transistor to maintain the audio transmission transistor off during the high-speed data operation mode.
15. The method according to claim 14, the method further comprising: During the high-speed data operation mode, ground the gate of the first transistor through a resistor.
16. The method according to claim 14, the method further comprising: During the audio operation mode, couple the gate of the audio transmission transistor to a switched linearizer circuit, and drive an audio signal to the integrated circuit terminal through the audio transmission transistor during the audio operation mode.
17. The method according to claim 16, the method further comprising: During the audio operation mode, bias the gate of the first transistor with a negative voltage.
18. An integrated circuit, the integrated circuit comprising: An integrated circuit terminal; An audio source for an audio signal; An audio transmission transistor coupled between the audio source and the integrated circuit terminal; A resistor coupled to ground; A first switch configured to couple the gate of the audio transmission transistor to ground through the resistor during a high-speed data operation mode of the integrated circuit; and Components for coupling a negative charge on the integrated circuit terminal to the gate of the audio transmission transistor during the high-speed data operation mode.
19. The integrated circuit according to claim 18, the integrated circuit further comprising: A switched linearizer circuit, wherein the first switch is further configured to couple the gate of the audio transmission transistor to the switched linearizer circuit during an audio operation mode of the integrated circuit.
20. The integrated circuit according to claim 18, wherein the audio source has a capacitance, and wherein the components for coupling the negative charge are configured to substantially isolate the integrated circuit terminal from the capacitance during the high-speed data operation mode.