Orthogonal signal high-precision error compensation system based on FPGA

Abstract

The invention discloses an orthogonal signal high-precision error compensation system based on a field programmable gate array (FPGA), which takes the FPGA as a core, realizes the whole process of acquisition, filtering, error compensation, fine direction distinguishing, displacement calculation and signal transmission of orthogonal signals, and completes high-precision error correction of the orthogonal signals on a chip. According to the method, parallel QR decomposition and Cholesky decomposition are carried out on a coefficient matrix by utilizing the high-speed parallel calculation advantage of the FPGA, and a Hydemann parameter is calculated, so that high-precision real-time error compensation is carried out on an orthogonal signal. And based on the orthogonal signal after error compensation, carrying out subdivision orientation and displacement calculation, and uploading the data after error compensation, the signal subdivision number and the displacement calculation result to an upper computer system. According to the method, external hardware and auxiliary calculation of an upper computer are not needed, the system structure is simple, and high-precision real-time error compensation of orthogonal signals is completely achieved through the FPGA.

Description

Technical Field

[0001] The present invention belongs to the technical field of precision measurement, and particularly relates to a high-precision error compensation system for orthogonal signals based on FPGA. Background Art

[0002] Grid sensors and laser interferometers are widely used in modern precision measurement instruments, robots, numerical control machine tools, automated production lines and other fields, which have strongly promoted the progress of scientific research work and industrial production. The optical signals output by grid sensors and laser interferometers are converted into analog voltage signals through optoelectronic conversion circuits, and the two signals are orthogonal. In actual measurement work, due to the influence of working optical paths, optoelectronic conversion circuits and other external factors, the two orthogonal signals output by the system usually contain multiple errors, which affect the subsequent data processing work. In order to meet the needs of high-precision measurement instruments, how to improve the real-time performance and accuracy of orthogonal signal data processing has become a key research issue in the field of high-precision measurement.

[0003] The Hydemann algorithm is a classic algorithm for orthogonal signal error compensation. Its core idea is to use the method of ellipse fitting to solve the errors contained in orthogonal signals. If there are measurement errors in the orthogonal signals output by the front-end measurement system, their Lissajous figures present an elliptical shape. The Hydemann algorithm uses a mathematical model to compensate for the errors. After error compensation, a set of orthogonal signals whose relationship in the coordinate system presents a circular shape is obtained, and the compensation effect is good. Since this algorithm involves the operation of fifth-order matrices and the solution of equations, the data processing is complex and the hardware implementation is difficult. The existing solutions are basically based on the PC side for data operation and its error compensation, and it is difficult to achieve high-precision real-time error compensation of orthogonal signals. Summary of the Invention

[0004] The present invention provides a high-precision error compensation system for orthogonal signals based on FPGA, aiming to solve the problems of low precision and poor real-time performance of orthogonal signals in high-precision measurement work based on a hardware solution, and improve the corresponding performance indicators.

[0005] To solve the above technical problems, a technical solution adopted by the present invention is:

[0006] A high-precision error compensation system for orthogonal signals based on FPGA includes an AD module, an FPGA module, a DA module and a host computer system;

[0007] The AD module converts two analog signals into digital signals and inputs them into the FPGA module;

[0008] In the FPGA module:

[0009] The input orthogonal signal undergoes data cross-clock domain processing through the asynchronous FIFO input module, and then is output in two paths after mean filtering: the first path is converted into floating-point data through the floating-point IP core for storage, which is used for subsequent signal compensation; the second path obtains the coefficient matrix through multiplication and accumulation, and the coefficient matrix is converted into floating-point data through the floating-point IP core;

[0010] The coefficient matrix is simultaneously subjected to QR decomposition and Cholesky decomposition. The rank of the matrix is judged according to the QR decomposition, and then whether the Cholesky decomposition result is credible is judged: when the coefficient matrix is full rank, the system of equations is solved based on the matrix obtained by Cholesky decomposition to solve the Hydemann parameters; if the coefficient matrix is not full rank, the Cholesky decomposition result is not credible, and the previous set of valid Hydemann parameters is used as the current data compensation coefficient;

[0011] Based on the Hydemann parameters, error compensation is performed on the orthogonal signal after mean filtering;

[0012] The compensated data is output in three paths: the first path is output to the DA module through the asynchronous FIFO output module to output the orthogonal signal after error compensation; the second path passes through the data sending module and is sent to the host computer system; the third path performs fine-resolution direction and displacement calculation, and the calculation results are sent to the host computer system through the data sending module.

[0013] Further, the analog voltage signal is obtained by converting the optical signal output by the front-end measurement system through an optoelectronic conversion device.

[0014] Further, after the FPGA module reads the digital signal output by the AD module, it completes the data cross-clock domain processing through the asynchronous FIFO input module.

[0015] Further, the first path of data after mean filtering is converted into floating-point data through the floating-point IP core and stored in the BRAM of the FPGA module.

[0016] Further, the second path of data after mean filtering is combined through self-multiplication and mutual multiplication to calculate the high-order power value, and the calculation results are accumulated to obtain the coefficient matrix.

[0017] Further, the coefficient matrix is converted into floating-point numbers by using the floating-point IP core, and parallel QR decomposition and Cholesky decomposition are performed on the coefficient matrix based on the floating-point numbers.

[0018] Furthermore, the specific process of performing parallel QR decomposition on the coefficient matrix is as follows: Solve the sine and cosine values in the Givens matrix in a numerically stable manner, and perform iterative multiplication using the Givens matrix. When calculating the product, combine the characteristics of the Givens matrix, multiply the elements of the irrelevant rows by the corresponding Givens matrix simultaneously, update the iterative coefficient matrix after calculation, and achieve parallel decomposition operation. The QR decomposition result can be obtained with only 6 iterations.

[0019] Furthermore, the specific method for judging the rank of the matrix based on QR decomposition and thus judging whether the Cholesky decomposition result is credible is as follows: Based on the upper triangular matrix obtained by parallel QR decomposition of the coefficient matrix, perform data validity judgment. If there is a 0 element among the main diagonal elements of the upper triangular matrix, the coefficient matrix is rank-deficient, and the current data is considered abnormal, and the Cholesky decomposition result is not credible, that is, it is impossible to correctly calculate the Hydemann parameters applicable to this group of orthogonal signals based on the current data. Combine with the front-end system to judge whether there is an abnormality. If there is an abnormality, feedback the situation to the host computer system, and use the previous set of valid Hydemann parameters as the compensation coefficient for the current data; if the coefficient matrix is full rank, it can be known that the coefficient matrix is positive definite, the Cholesky decomposition data is credible, and the system of equations can be solved based on the decomposition matrix and the Hydemann parameters can be calculated.

[0020] Furthermore, the first-channel data after error compensation is converted into fixed-point data through a floating-point IP core, cached through an asynchronous FIFO output module, and converted into an analog signal output through a DA module.

[0021] Furthermore, the second-channel data after error compensation is directly sent to the host computer through a data sending module.

[0022] Furthermore, the third-channel data after error compensation uses the CORDIC algorithm to solve the arctangent function, solve the current phase, shift and normalize the phase, perform fine direction discrimination, and perform displacement calculation based on the signal fine fraction.

[0023] There is also provided an orthogonal signal processing device, including the high-precision error compensation system for orthogonal signals based on FPGA as described above.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] 1. The present invention provides a high-precision real-time processing system for orthogonal signals based on FPGA with a simple system structure, high real-time performance, and high processing accuracy, which can perform real-time error compensation on the DC drift error, phase error, and channel gain ratio error existing in the orthogonal signals output by the front-end measurement system, providing a hardware solution for the high-precision real-time processing of orthogonal signals.

[0026] 2. The present invention takes FPGA as the core in terms of structure, builds a full-functional system for orthogonal signal data acquisition, processing, storage and transmission, gives full play to the advantages of parallel computing of FPGA, solves the need of general orthogonal signal processing systems relying on external hardware, and also solves the problem that data needs to be uploaded to the host computer software for calculation and then transmitted back. In the whole process of signal acquisition, filtering, correction, storage, signal subdivision, displacement calculation and signal transmission of the present invention, all are executed inside the FPGA board, reducing the complexity of the orthogonal signal processing system and improving the real-time performance and accuracy of orthogonal signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of the high-precision error compensation system for orthogonal signals based on FPGA of the present invention.

[0028] Figure 2 is a data processing program flowchart of the high-precision real-time processing system for orthogonal signals of the present invention.

[0029] Figure 3 is a schematic diagram of the parallel QR decomposition method process for the coefficient matrix.

[0030] Figure 4 is a comparison waveform diagram of the FPGA operation data, original data and ideal data in the embodiment.

[0031] Figure 5 is a Lissajous figure comparison diagram of the FPGA operation data, original data and ideal data in the embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The following elaborates on the preferred embodiments of the present invention in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0034] The present invention provides a high-precision real-time processing system for orthogonal signals based on FPGA with a simple system structure, high real-time performance and high processing accuracy, providing a hardware solution for the high-precision real-time processing of orthogonal signals.

[0035] See attached Figure 1, an FPGA-based high-precision error compensation system for orthogonal signals, including an AD module 1, an FPGA module 18, a DA module 17, and a host computer system 11.

[0036] The AD module 1 converts two voltage signals into digital signals and inputs them into the FPGA module 18. In this embodiment, the analog voltage signals are obtained by converting the optical signals output by the front-end measurement system through optoelectronic conversion devices, denoted as X and Y respectively.

[0037] In the FPGA module 18, the orthogonal signals are collected and processed. The orthogonal signals after mean filtering and error correction are subjected to fine-resolution direction finding and displacement calculation, and the calculation results are output to the host computer.

[0038] See Appendix Figure 2 , and the data processing flow is specifically as follows:

[0039] The input orthogonal signals are cached through the asynchronous FIFO input module 2. After the FPGA module reads the digital signals output by the AD module, the cross-clock domain processing of the data is completed through the asynchronous FIFO input module 2. Since the clock frequency of the output port of the asynchronous FIFO input module 2 is the same as the main clock of the FPGA, after the cross-clock domain processing, the original digital signals can be directly subjected to mean filtering 3 in the FPGA.

[0040] The signal data after mean filtering 3 is output in two paths: The first path of data is converted into floating-point data through the floating-point IP core and stored in the BRAM of the FPGA module 18 through the data storage module 6 for subsequent signal compensation. The second path of data is combined through self-multiplication (X 2 , Y 2 , X 3 , Y 3 , X 4 , Y 4 ) and cross-multiplication (XY, X 2 Y 2 , XY 2 , X 2 Y, X 3 Y, XY 3 ) to calculate the high-order power values, and the calculation results are subjected to respective multiplication and accumulation 4 to obtain the coefficient matrix. The coefficient matrix passes through the floating-point conversion module 5 and is converted into floating-point data using the floating-point IP core, and parallel QR decomposition and Cholesky decomposition are performed on the coefficient matrix based on floating-point numbers.

[0041] Perform QR decomposition 7 and Cholesky decomposition 8 on the coefficient matrix respectively. Based on the result of QR decomposition 7, judge whether the coefficient matrix is full rank, so as to judge whether the result of Cholesky decomposition 8 is credible. The specific method is as follows: According to the upper triangular matrix obtained by parallel QR decomposition 7 of the coefficient matrix, perform data validity judgment. If there is a 0 element in the main diagonal elements of the upper triangular matrix, the coefficient matrix is not full rank, and it is considered that the current data is abnormal. The result of Cholesky decomposition 8 is not credible, that is, it is impossible to correctly calculate the Hydemann parameters applicable to this group of orthogonal signals based on the current data. Combine the working characteristics of the front-end system to judge whether an abnormal situation occurs. If it is abnormal, feedback the abnormal situation to the host computer system 11; if the coefficient matrix is full rank, it is considered that the data is valid, the data of Cholesky decomposition 8 is credible, and the system of equations can be solved 9 based on the decomposition matrix, and then the Hydemann parameters can be solved 10.

[0042] After the Hydemann parameter solution 10 is completed, read the mean filtered signal stored in the BRAM, and based on the Hydemann parameters, perform signal compensation 15 on the orthogonal signal after mean filtering 3 to obtain the orthogonal signal after error correction. The compensated data is output in three ways: The first-way data is converted into fixed-point data through a floating-point IP core and output to the DA module 17 through the asynchronous FIFO output module 16 to output a group of orthogonal signals after error compensation; the second way is directly sent to the host computer system 11 through the data sending module 12 for data display and subsequent processing; the third-way data uses the CORDIC algorithm to solve the arctangent function, solve the current phase, shift and normalize the phase, perform fine direction discrimination 14, perform displacement calculation 13 based on the signal fine fraction, and send the calculation result to the host computer system 11 through the data sending module 12.

[0043] So far, the system has completed the error correction of a group of sampled data.

[0044] This invention is based on an FPGA chip and uses the Hydemann algorithm for orthogonal signal error compensation. The main difficulty lies in using the FPGA to complete complex matrix operations and system of equations solving. The specific algorithm implementation process is as follows:

[0045] The ideal orthogonal signal mathematical model is:

[0046]

[0047] In actual situations, the orthogonal signal contains various errors and can be expressed as:

[0048]

[0049] Where: p is the DC drift of the cosine channel, q is the DC drift of the sine channel, α is the phase error (non-orthogonal error), and γ is the channel gain ratio.

[0050] Through trigonometric transformation, we can obtain:

[0051]

[0052] Then:

[0053]

[0054] Then:

[0055]

[0056] That is:

[0057]

[0058] By performing equivalent transformation on the above expressions, we can obtain:

[0059] AX 2 +BY 2 +CXY+DX+EY=1 Where:

[0060]

[0061] Express the above system of equations in matrix form:

[0062]

[0063] It can be denoted as:

[0064] AX=1 Thus, the least squares method can be used for solution, and the equation becomes:

[0065] A T AX=A T

[0066] That is:

[0067] CX=B (C=A T A,B=A T ) By collecting multiple groups of data, we can obtain:

[0068]

[0069] After obtaining the coefficient matrix, perform parallel QR decomposition on the coefficient matrix. The present invention uses the Givens matrix for parallel QR decomposition, and the decomposition process of the parallel QR decomposition is as Figure 3 shown. The specific process is as follows:

[0070] The Givens matrix can be expressed as:

[0071]

[0072] In an FPGA, directly calculating trigonometric functions requires the use of the CORDIC algorithm. However, the CORDIC algorithm consumes a relatively large amount of resources. There is a numerically stable solution that can be used for QR decomposition in hardware:

[0073]

[0074] In order to make full use of the advantages of parallel computing in the FPGA, the present invention adopts parallel QR decomposition, and the decomposition idea is as Figure 3 shown. After 6 iterations, the decomposition result of a fifth-order matrix can be obtained, that is:

[0075]

[0076] The present invention uses parallel QR decomposition for matrix decomposition. In actual calculation, when multiplying two fifth-order matrices, it is only necessary to multiply the two rows of elements corresponding to the Givens matrix in the iterative matrix by the Givens matrix, thus avoiding the direct calculation of the fifth-order matrix and greatly reducing the amount of calculation.

[0077] Since Q is an orthogonal matrix, the rank of R is the same as that of C, and R is an upper triangular matrix. Therefore, it can be determined whether C is full rank by judging whether the main diagonal elements of R contain 0 elements. When R is full rank, it means that the coefficient matrix C is full rank. When the coefficient matrix is full rank, it is easy to obtain that the coefficient matrix is positive definite:

[0078] C = A T A

[0079] Then C is a semi-positive definite matrix. When C is full rank, it means that all the eigenvalues of C are positive, so C is a positive definite matrix. If the coefficient matrix C is a positive definite matrix, then Cholesky decomposition can be performed, that is:

[0080] C = LL T (L is a lower triangular matrix)

[0081] Then the equation can be equivalently transformed into:

[0082] LL T X = B

[0083] Thus, the solution of the system of equations can be solved by the back substitution method. After obtaining the exact values of A, B, C, D, and E, the Hydemann parameters can be solved according to the following formula:

[0084]

[0085] Since subsequent signal correction does not require the calculation of α, only sinα and cosα are needed. When calculating the arcsine function, several iterations of the CORDIC algorithm or a lookup table need to be used, which is computationally cumbersome. And since α is in [-90°, 90°], cosα is non - negative. Therefore, the algorithm is modified, and the specific formula is as follows:

[0086]

[0087] After obtaining the Hydemann parameters, the signal can be corrected. Denote the signal before correction as X and Y, and the signal after correction as x and y:

[0088]

[0089] Thus, the orthogonal signal after error compensation is obtained. Based on the corrected signal, the current phase can be calculated using trigonometric functions:

[0090] θ = atan(y / x)

[0091] And the calculated phase is normalized to obtain the fine fraction n, that is:

[0092]

[0093] Thus, the integer fine fraction N can be solved according to the fine fraction n. When the fine fraction ranges from 0 to 1, n = 1, that is, when the signal moves forward one period, N is incremented by 1; when the fine fraction ranges from 1 to 0, n = 0, that is, when the signal moves backward one period, N is decremented by 1, thereby completing signal subdivision.

[0094] After obtaining the fine fraction, the displacement D can be calculated according to the specific parameters of the front - end measurement system:

[0095]

[0096] where: λ is the measurement light wavelength.

[0097] On the basis of successful algorithm simulation, Verilog language programming is carried out, and calculations are performed using FPGA. The FPPGA model used in the present invention is Xilinx xc7a200tfbg484 - 2. After the FPGA operation data is sent to the host computer, its corrected waveform can be plotted for comparative display, as Figure 4 shown, which shows the waveform comparison of the waveform after error correction by FPGA with the original signal and the standard orthogonal signal; as Figure 5 shown, which shows the Lissajous figure comparison of the Lissajous figure after error correction by FPGA with the original signal and the standard orthogonal signal. From Figure 4 and Figure 5It can be seen that by adopting the orthogonal signal high-precision error compensation system of the present invention, high-precision real-time error compensation of orthogonal signals can be achieved, and the effect is relatively ideal.

[0098] An orthogonal signal processing device is also provided, which includes the orthogonal signal high-precision error compensation system based on FPGA as described above, and is used for high-precision real-time processing of orthogonal signals.

[0099] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0100] The above description is only the embodiments of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be included in the patent protection scope of the present invention by the same token.

Claims

1. An orthogonal signal high-precision error compensation system based on FPGA, comprising an AD module, an FPGA module, a DA module and a host computer system; The AD module converts two analog signals into digital signals and inputs them into the FPGA module; In the FPGA module: The input orthogonal signal undergoes cross-clock domain processing of data through the asynchronous FIFO input module, and then is output in two paths after mean filtering: the first path is converted into floating-point data through the floating-point IP core for storage, which is used for subsequent signal compensation; The second path obtains a coefficient matrix through multiplication and accumulation, and the coefficient matrix is converted into floating-point data after passing through the floating-point IP core; Perform QR decomposition and Cholesky decomposition on the coefficient matrix simultaneously. Judge the rank of the matrix according to the QR decomposition, and further judge whether the Cholesky decomposition result is credible: when the coefficient matrix is full rank, solve the system of equations based on the Cholesky decomposition matrix to solve the Hydemann parameters; If the coefficient matrix is not full rank, the Cholesky decomposition result is not credible, and the previous set of valid Hydemann parameters is used as the current data compensation coefficient; Based on the Hydemann parameters, perform error compensation on the orthogonal signal after mean filtering; The compensated data is output in three paths: the first path is output to the DA module through the asynchronous FIFO output module to output the orthogonal signal after error compensation; The second path passes through the data sending module and is sent to the host computer system; the third path performs fine-resolution direction and displacement calculation, and sends the calculation result to the host computer system through the data sending module.

2. The high-precision error compensation system for orthogonal signals based on FPGA according to claim 1, wherein: The analog voltage signal is obtained by converting the optical signal output by the front-end measurement system through an optoelectronic conversion device.

3. The orthogonal signal high-precision error compensation system based on FPGA according to claim 1, wherein: After the FPGA module reads the digital signal output by the AD module, it completes the cross-clock domain processing of data through the asynchronous FIFO input module.

4. The high-precision error compensation system for orthogonal signals based on FPGA according to any one of claims 1 to 3, characterized in that: The first path of data after mean filtering is converted into floating-point data through the floating-point IP core and stored in the BRAM of the FPGA module.

5. The high-precision error compensation system for orthogonal signals based on FPGA according to any one of claims 1 to 3, characterized in that: The second path of data after mean filtering combines data by self-multiplication and mutual multiplication, calculates the high-power product value, and accumulates the calculation results to obtain a coefficient matrix.

6. The orthogonal signal high-precision error compensation system based on FPGA according to claim 5, characterized in that: Use the floating-point IP core to convert the coefficient matrix into a floating-point number, and perform parallel QR decomposition and Cholesky decomposition on the coefficient matrix based on the floating-point number.

7. The orthogonal signal high-precision error compensation system based on FPGA according to claim 6, wherein: The specific process of performing parallel QR decomposition on the coefficient matrix is: solve the sin value and cos value in the Givens matrix, and use the Givens matrix for iterative multiplication. When calculating the multiplication, combine the characteristics of the Givens matrix, multiply the elements of the irrelevant rows by the corresponding Givens matrix at the same time, and update the iterative coefficient matrix after calculation to achieve parallel decomposition operation.

8. The high-precision error compensation system for orthogonal signals based on FPGA according to claim 1 or 6, characterized in that: The specific method for judging the rank of a matrix according to QR decomposition and thus judging whether the Cholesky decomposition result is credible is as follows: Based on the upper triangular matrix obtained by parallel QR decomposition of the coefficient matrix, data validity judgment is carried out. If there is a zero element in the main diagonal elements of the upper triangular matrix, the coefficient matrix is of deficient rank, the current data is considered abnormal, and the Cholesky decomposition result is not credible, that is, it is impossible to correctly calculate the Hydemann parameters applicable to this group of orthogonal signals based on the current data. Combine with the working conditions of the front-end equipment to judge whether the system is abnormal. If it is abnormal, feedback this abnormal situation to the host computer system, and use the previous set of valid Hydemann parameters as the error compensation coefficient for the current data; If the coefficient matrix is of full rank, the Cholesky decomposition result is considered credible, and the system of equations can be solved based on the decomposition matrix to calculate the Hydemann parameters.

9. The high-precision error compensation system for orthogonal signals based on FPGA according to claim 1, characterized in that: The first channel of data after error compensation is converted into fixed-point data through a floating-point IP core, cached through an asynchronous FIFO output module, and converted into an analog signal output through a DA module; the second channel of data after error compensation is directly sent to the host computer; The third channel of data after error compensation uses the CORDIC algorithm to solve the arctangent function, solve the current phase, shift and normalize the phase, perform fine direction discrimination, and perform displacement calculation based on the signal fine fraction.

10. An orthogonal signal processing device, characterized in that: It includes the high-precision error compensation system for orthogonal signals based on FPGA according to any one of claims 1 to 9.

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