Series fault arc detection device based on multi-criterion fusion

Abstract

The invention relates to a series fault arc detection device based on multi-criterion fusion. The device comprises a data acquisition unit used for acquiring circuit data of a to-be-detected circuit; the signal processing unit is used for preprocessing the circuit data so as to improve the data quality and obtain preprocessed circuit data; the feature extraction and analysis unit is used for extracting feature parameters of the fault arc from the circuit data and reconstructing the feature parameters to obtain the feature parameters of the fault arc; and the decision judgment unit is used for inputting the circuit data and the reconstructed fault arc characteristic parameters into a trained machine learning model, and judging whether the to-be-detected circuit generates a fault arc or not. According to the invention, high-quality circuit data acquisition and processing are realized, accurate and reliable characteristic information is provided, it is ensured that the detection device can timely and accurately identify a fault arc, all the units work cooperatively to realize rapid and accurate detection of the fault arc, and the problem of how to accurately detect the fault arc generated in a circuit is solved.

Description

Technical Field

[0001] The present application relates to the technical field of electrical safety detection, and particularly to a series fault arc detection device based on multi-criterion fusion. Background Art

[0002] With the continuous improvement of the electrification level of modern society, electrical equipment is increasingly widely used in production and life, and the potential electrical fire hazards are becoming increasingly prominent. Among them, fault arcs, as one of the key factors causing electrical fires, seriously threaten people's lives and property safety.

[0003] Fault arcs can be divided into parallel type and series type according to the connection relationship between their fault positions and loads in the circuit. When a series fault arc occurs, the circuit is equivalently connected to a time-varying non-linear load, and at this time, the fault current is less than the load current during the normal operation of the electrical system. This characteristic makes it difficult for traditional protection switches to detect it in a timely and effective manner, thus increasing the risk of electrical fires.

[0004] Currently, no effective solution has been proposed for how to accurately detect fault arcs generated in the circuit in the related art. Summary of the Invention

[0005] An embodiment of the present application provides a series fault arc detection device based on multi-criterion fusion to at least solve the problem of how to accurately detect fault arcs generated in the circuit in the related art.

[0006] In a first aspect, an embodiment of the present application provides a series fault arc detection device based on multi-criterion fusion, and the device includes an integrated data acquisition unit, a signal processing unit, a feature extraction and analysis unit, and a decision-making judgment unit;

[0007] The data acquisition unit is configured to acquire circuit data of a circuit to be detected;

[0008] The signal processing unit is configured to preprocess the circuit data to improve data quality and obtain preprocessed circuit data;

[0009] The feature extraction and analysis unit is configured to extract fault arc feature parameters of the fault arc from the circuit data; and perform feature reconstruction on the fault arc feature parameters to obtain reconstructed fault arc feature parameters;

[0010] The decision-making judgment unit is configured to input the circuit data and the reconstructed fault arc feature parameters into a trained machine learning model to determine whether a fault arc is generated in the circuit to be detected.

[0011] In some of these embodiments, the data acquisition unit is configured to collect circuit data of a circuit to be detected through a current sensor and a zero-sequence current sensor, and convert the circuit data from an analog signal to a digital signal through an A / D conversion module.

[0012] In some of these embodiments, the signal processing unit is configured to filter the circuit data converted into a digital signal through a digital filter, and perform gain adjustment on the filtered circuit data through an amplifier to improve the data quality of the circuit data.

[0013] In some of these embodiments, the training process of the machine learning model includes:

[0014] Construct a first experimental scenario and a second experimental scenario, where the first experimental scenario is a circuit scenario without interference, and the second experimental scenario is a circuit scenario with interference;

[0015] In the first experimental scenario, by changing the circuit load, circuit topology, and arcing mode in the experimental circuit, a number of first normal operating conditions and first fault conditions are simulated;

[0016] In the second experimental scenario, by changing the circuit load, circuit topology, and arcing mode in the experimental circuit, a number of second normal operating conditions and second fault conditions are simulated;

[0017] Collect the circuit data generated under the first normal operating condition, the first fault condition, the second normal operating condition, and the second fault condition;

[0018] Train the machine learning model based on the circuit data to obtain a trained machine learning model.

[0019] In some of these embodiments, training the machine learning model based on the circuit data to obtain a trained machine learning model includes:

[0020] Extract fault arc feature parameters of the fault arc from the circuit data;

[0021] Perform feature reconstruction on the fault arc feature parameters to reduce the blurring of fault features caused by circuit noise interference, and obtain reconstructed fault arc feature parameters;

[0022] Train the machine learning model based on the circuit data and the reconstructed fault arc feature parameters to obtain a trained machine learning model.

[0023] In some of these embodiments, extracting the fault arc feature parameters of the fault arc from the circuit data includes:

[0024] Decompose the current signal of the circuit data using the mother wavelet coif1 to obtain a preprocessed signal;

[0025] Extract the fault arc characteristic parameters from the preprocessed signal based on two dimensions of single cycle and multi - cycle to obtain the single - cycle characteristic parameters and multi - cycle characteristic parameters of the fault arc.

[0026] In some embodiments, perform feature reconstruction on the fault arc characteristic parameters to reduce the fuzziness of fault features caused by circuit noise interference, and the reconstructed fault arc characteristic parameters obtained include:

[0027] Use the Teager energy operator to enhance the mutation characteristics in the zero - sequence current coupling signal of the circuit data to obtain the fault arc characteristic parameters after feature enhancement;

[0028] Utilize the periodic symmetry characteristic of the AC power supply voltage to calculate the ratio of the fault arc characteristic parameters after feature enhancement within the front and back 10 - ms time windows to obtain the reconstructed fault arc characteristic parameters.

[0029] In some embodiments, train a machine - learning model based on the circuit data and the reconstructed fault arc characteristic parameters, and the trained machine - learning model obtained includes:

[0030] Construct a machine - learning model based on the decision - tree algorithm. Among them, the machine - learning model uses the information gain ratio as the measurement standard for feature selection. By calculating the information gain ratios of different features, select the features with the maximum information gain ratio for decision - tree node splitting;

[0031] Input the circuit data and the reconstructed fault arc characteristic parameters into the machine - learning model, determine the network weights of the model, and obtain the trained machine - learning model.

[0032] In some embodiments, build a second experimental scenario including:

[0033] Set up a bypass interference loop to build a second experimental scenario on the basis of the first experimental scenario. Among them, the bypass interference loop uses an AC / AC converter and an AC / DC inverter as loads to simulate and generate harmonic interference and voltage - fluctuation interference.

[0034] In some embodiments, if the trained machine - learning model determines that the circuit to be detected generates a fault arc, trigger the protection switch to cut off the circuit through the protection switch.

[0035] Compared with the related art, an apparatus for detecting series fault arcs based on multi-criterion fusion provided by an embodiment of the present application includes: a data acquisition unit for acquiring circuit data of a circuit to be detected; a signal processing unit for preprocessing the circuit data to improve data quality and obtaining preprocessed circuit data; a feature extraction and analysis unit for extracting fault arc feature parameters of a fault arc from the circuit data; and performing feature reconstruction on the fault arc feature parameters to obtain reconstructed fault arc feature parameters; a decision-making unit for inputting the circuit data and the reconstructed fault arc feature parameters into a trained machine learning model to determine whether a fault arc occurs in the circuit to be detected. Through this apparatus, the acquisition and processing of high-quality circuit data are realized to provide accurate and reliable feature information, ensuring that the detection apparatus can identify fault arcs in a timely and accurate manner. Each unit works together to achieve fast and accurate detection of fault arcs, solving the problem of how to accurately detect fault arcs generated in a circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0037] Figure 1 is a structural block diagram of an apparatus for detecting series fault arcs based on multi-criterion fusion according to an embodiment of the present application;

[0038] Figure 2 is a flowchart of steps for training a machine learning model according to an embodiment of the present application;

[0039] Figure 3 is a schematic flowchart of feature reconstruction according to an embodiment of the present application;

[0040] Figure 4 is a comparison schematic diagram of the pulse factor ratio before and after reconstruction according to an embodiment of the present application;

[0041] Figure 5 is a comparison schematic diagram of the zero-sequence current Shannon entropy ratio before and after reconstruction according to an embodiment of the present application;

[0042] Figure 6 is a comparison schematic diagram of the D1 energy ratio before and after reconstruction according to an embodiment of the present application;

[0043] Figure 7 is a schematic internal structure diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be described and explained below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present application without creative efforts belong to the scope of protection of the present application.

[0045] Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, however, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be understood as the content disclosed in the present application being insufficient.

[0046] Referring to "embodiments" in the present application means that the specific features, structures or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the present application. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.

[0047] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "an", "one kind", "the" and the like involved in this application do not indicate a quantity limitation and may represent a singular or plural number. The terms "include", "comprise", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include unlisted steps or units, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connect", "be connected", "couple" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application refers to two or more. The "and / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the front and rear associated objects. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific sorting of the objects.

[0048] An embodiment of the present application provides a series fault arc detection device based on multi-criterion fusion. Figure 1 It is a structural block diagram of the series fault arc detection device based on multi-criterion fusion according to the embodiment of the present application, as Figure 1 shown. The device includes a data acquisition unit, a signal processing unit, a feature extraction and analysis unit, and a decision-making judgment unit;

[0049] The data acquisition unit is used to acquire circuit data of the circuit to be detected;

[0050] Further, the data acquisition unit is used to acquire circuit data of the circuit to be detected through a current sensor and a zero-sequence current sensor, and convert the circuit data from an analog signal to a digital signal through an A / D conversion module.

[0051] It should be noted that through the current sensor and the zero-sequence current sensor, it is ensured that the circuit data (current signal and zero-sequence current coupling signal) can be accurately acquired. These sensors have good electromagnetic compatibility and can work stably in a complex electromagnetic environment, effectively avoiding the influence of external interference on the acquired signal. The acquired analog signal is quickly converted into a digital signal through a high-speed A / D conversion module, providing a high-quality data basis for subsequent signal processing and analysis.

[0052] A signal processing unit for preprocessing circuit data to improve data quality and obtaining preprocessed circuit data;

[0053] Furthermore, a signal processing unit for filtering the circuit data converted into digital signals through a digital filter and adjusting the gain of the filtered circuit data through an amplifier to improve the data quality of the circuit data.

[0054] It should be noted that preprocessing operations such as filtering and amplifying the collected digital signals are carried out. A digital filter (such as a Butterworth filter) is used to design appropriate filtering parameters according to the frequency characteristics of the signal, effectively removing high-frequency noise and low-frequency interference signals and improving the purity of the signal; the gain of the signal is adjusted through an amplifier to ensure that the signal amplitude meets the requirements of subsequent processing and further improve the signal quality.

[0055] A feature extraction and analysis unit for extracting fault arc feature parameters of a fault arc from circuit data; and performing feature reconstruction on the fault arc feature parameters to obtain reconstructed fault arc feature parameters;

[0056] It should be noted that the above-mentioned fault arc feature extraction and reconstruction algorithms are implemented at the hardware and software levels. Among them, at the hardware level, the high-speed computing capabilities of a field-programmable gate array (FPGA) or a digital signal processor (DSP) are utilized to quickly calculate various feature parameters and perform feature reconstruction. In this way, accurate and reliable feature information is provided for the decision-making unit to ensure that the detection device can identify fault arcs in a timely and accurate manner.

[0057] At the software level, ① the mother wavelet coif1 is used to decompose the current signal of the circuit data to obtain a preprocessed signal; fault arc feature parameters are extracted from the preprocessed signal based on two dimensions of a single cycle and multiple cycles to obtain single-cycle and multi-cycle feature parameters of the fault arc. ② The Teager energy operator is used to enhance the mutation features in the zero-sequence current coupling signal of the circuit data to obtain fault arc feature parameters after feature enhancement; the ratio of the fault arc feature parameters after feature enhancement within a 10-ms time window before and after is calculated using the periodic symmetry characteristic of the AC power supply voltage to obtain the reconstructed fault arc feature parameters.

[0058] A decision-making unit for inputting the circuit data and the reconstructed fault arc feature parameters into a trained machine learning model to determine whether a fault arc occurs in the circuit to be detected. If it is determined that a fault arc occurs in the circuit to be detected, a protection switch is triggered to cut off the circuit through the protection switch.

[0059] It should be noted that the characteristic parameters output by the feature extraction and analysis unit are input into the trained machine learning model (decision tree classifier), and whether a faulty arc occurs is judged according to the output result of the classifier. If a faulty arc is detected, the decision-making unit immediately triggers the alarm system and at the same time controls the circuit cutting-off unit to act, quickly cutting off the faulty circuit to achieve real-time protection of the electrical system and effectively prevent the occurrence of electrical fires.

[0060] Through the series faulty arc detection device in the embodiments of the present application, high-quality circuit data collection and processing are realized to provide accurate and reliable characteristic information, ensuring that the detection device can identify faulty arcs in a timely and accurate manner. Each unit works together to achieve fast and accurate detection of faulty arcs, solving the problem of how to accurately detect faulty arcs generated in a circuit.

[0061] In some of these embodiments, the series faulty arc detection device provided in the above embodiments uses a machine learning model. Figure 2 It is a flowchart of the steps for training a machine learning model according to an embodiment of the present application, as Figure 2 shown. The training process of this machine learning model includes the following steps:

[0062] Step S202, build a first experimental scenario and a second experimental scenario. Among them, the first experimental scenario is a circuit scenario without interference, and the second experimental scenario is a circuit scenario with interference.

[0063] Specifically in step S202, build a first experimental scenario without interference, and on the basis of the first experimental scenario, build a second experimental scenario by setting up a bypass interference circuit. Among them, the bypass interference circuit uses an AC / AC converter and an AC / DC inverter as loads to simulate harmonic interference and voltage fluctuation interference.

[0064] It should be noted that the bypass interference circuit uses an AC / AC converter and an AC / DC inverter as loads. The output frequency adjustment range of the AC / AC converter should cover the common frequency fluctuation range in the actual electrical system, and the amplitude adjustment accuracy should reach ±1V; the DC output voltage adjustment range of the AC / DC inverter is 98V - 242V, and the current adjustment range is 1A - 500A. By precisely adjusting these parameters, various complex interferences such as harmonic interference and voltage fluctuation interference are simulated. The simulation of these interferences truly restores the situation where the faulty arc characteristics are annihilated by interference in the actual operating environment, providing more comprehensive, true and reliable experimental data for the training of the machine learning model for subsequent faulty arc detection.

[0065] Step S204, in the first experimental scenario, by changing the circuit load, circuit topology and arc generation method in the experimental circuit, a number of first normal operating conditions and first faulty operating conditions are simulated.

[0066] It should be noted that to ensure a comprehensive simulation of various load characteristics in the actual electrical system in the first experimental scenario, the selection of the circuit load covers typical loads such as resistors and halogen lamps required by the standard tests, and also includes common loads widely used in real distribution systems, such as electric kettles, ovens, induction cookers, microwave ovens, vacuum cleaners, electric drills, switching power supplies, fluorescent lamps, dimmable lamps, etc. For the resistive load, by setting different resistance values, the electrical characteristics under different power consumption scenarios are accurately simulated; for the dimmable lamp, its conduction angle can be flexibly changed (such as 30°, 60°, 90°, 120°, 180°) to simulate the electrical behavior under different brightness adjustment states, so as to comprehensively and accurately reproduce the operating conditions of various actual electrical equipment in the circuit.

[0067] Furthermore, it should be noted that representative circuit topologies are designed, including but not limited to single-load circuits, multi-load circuits, parallel connection of small-power fault branches and large-power normal branches, and parallel connection of small-power normal branches and large-power fault branches. The single-load circuit is mainly used to deeply study the characteristics of fault arcs under single-load conditions; the multi-load circuit simulates the complex scenario of multiple electrical appliances operating simultaneously in a household or small commercial premises; the two topologies of parallel connection of small-power fault branches and large-power normal branches and parallel connection of small-power normal branches and large-power fault branches focus on exploring the effect of the interaction between branches with different powers on the characteristics of fault arcs. During the design process of each topology, the stability and reliability of the circuit operation are ensured, and at the same time, precise control of the circuit parameters is achieved.

[0068] Even further, it should be noted that real arc faults are simulated by the arc generation method. Mainly two methods of arc drawing and carbonized wire arc generation are used to simulate the fault conditions in the actual electrical system. During the arc drawing process, by precisely controlling the electrode material (such as selecting electrodes of different materials such as copper and aluminum), the electrode spacing (which can be finely adjusted within the range of 0.1 - 10 mm), and the contact pressure (monitored and adjusted in real time using a high-precision pressure sensor), the generation process of fault arcs when the line is in poor contact is truly simulated; for carbonized wire arc generation, insulated wires with different degrees of aging are selected, and local carbonization is carried out by methods such as heating or chemical corrosion to simulate the fault arcs caused by line insulation aging.

[0069] Step S206, in the second experimental scenario, by changing the circuit load, circuit topology, and arc generation method in the experimental circuit, a number of second normal operating conditions and second fault conditions are simulated;

[0070] It should be noted that to ensure a comprehensive simulation of various load characteristics in the actual electrical system in the second experimental scenario, the circuit load selection covers typical loads such as resistors and halogen lamps required by the standard tests, and also includes common loads widely used in real distribution systems, such as kettles, ovens, induction cookers, microwave ovens, vacuum cleaners, electric drills, switching power supplies, fluorescent lamps, and dimmable lights. For resistive loads, by setting different resistance values, the electrical characteristics under different power consumption scenarios are accurately simulated; for dimmable lights, the conduction angle can be flexibly changed (such as 30°, 60°, 90°, 120°, 180°) to simulate the electrical behavior under different brightness adjustment states, so as to comprehensively and accurately reproduce the operating conditions of various actual electrical equipment in the circuit.

[0071] Furthermore, it should be noted that representative circuit topologies are designed, including but not limited to single-load circuits, multi-load circuits, parallel connections of low-power fault branches and high-power normal branches, and parallel connections of low-power normal branches and high-power fault branches. Single-load circuits are mainly used to deeply study the characteristics of fault arcs under single-load conditions; multi-load circuits simulate complex scenarios where multiple electrical appliances operate simultaneously in households or small commercial premises; the two topologies of parallel connections of low-power fault branches and high-power normal branches, and parallel connections of low-power normal branches and high-power fault branches focus on exploring the effects of the mutual influence between branches with different powers on the characteristics of fault arcs. During the design process of each topology, the stability and reliability of the circuit operation are ensured, and at the same time, precise control of circuit parameters is achieved.

[0072] Even further, it should be noted that real arc faults are simulated by means of arc generation. Mainly two methods, arc-drawing arc generation and carbonized wire arc generation, are used to simulate the fault conditions in the actual electrical system. During the arc-drawing arc generation process, by precisely controlling the electrode material (such as selecting electrodes made of different materials like copper and aluminum), the electrode spacing (which can be finely adjusted within the range of 0.1 - 10 mm), and the contact pressure (monitored and adjusted in real time using a high-precision pressure sensor), the generation process of fault arcs when the line is in poor contact is realistically simulated; carbonized wire arc generation simulates the fault arcs caused by line insulation aging by selecting insulated wires with different degrees of aging and using methods such as heating or chemical corrosion to locally carbonize them.

[0073] Step S208, collect the circuit data generated under the first normal condition, the first fault condition, the second normal condition, and the second fault condition;

[0074] Specifically, in step S208, circuit data generated under the first normal condition, the first fault condition, the second normal condition, and the second fault condition are collected. The circuit data includes current signals, arc voltage signals, and zero-sequence current coupling signals. It should be noted that in addition to the circuit data, in each experiment of working condition simulation, environmental parameters such as ambient temperature and humidity during each experiment also need to be recorded in detail, because these environmental factors may have subtle but non-negligible effects on electrical characteristics, ensuring the integrity and traceability of the collected data; and strict screening and preprocessing operations are performed on the collected data to eliminate abnormal data caused by equipment failures or experimental operation errors, etc., so as to construct a high-quality and representative data set.

[0075] Step S208 preferably includes the following steps:

[0076] In step S2081, in the offline analysis mode, a high-precision oscilloscope is selected for data acquisition. The sampling rate of the oscilloscope is set to 10 MHz, and the time window is set to 20 ms to ensure that the current, arc voltage, and zero-sequence current coupling signals can be collected synchronously and accurately. Before sampling, strict calibration operations are performed on the oscilloscope to ensure the accuracy of the measurement; during the acquisition process, the collected data is transmitted to the computer in real time through a high-speed data transmission interface, and with the help of specially developed data storage software, the data is classified and stored according to experimental conditions (including load type, circuit topology, arc generation method, etc.) for in-depth analysis later.

[0077] In step S2082, in the online detection mode, a high-performance microprocessor TMS320F28335 is used to undertake the data acquisition task. The microprocessor integrates a high-speed A / D conversion module inside, which can quickly and accurately convert analog signals into digital signals. By optimizing the data acquisition program, it is ensured that the current and zero-sequence current coupling signals can still be collected stably and reliably in a complex electromagnetic environment.

[0078] In step S210, a machine learning model is trained based on the circuit data to obtain a trained machine learning model, where the machine learning model is used to detect whether a fault arc occurs in the circuit.

[0079] Step S210 specifically includes the following steps:

[0080] In step S2101, fault arc characteristic parameters of the fault arc are extracted from the circuit data;

[0081] Specifically, in step S2101, the mother wavelet coif1 is used to decompose the current signal of the circuit data to obtain a preprocessed signal; the fault arc characteristic parameters are extracted from the preprocessed signal based on two dimensions of single period and multi-period, and the single-period characteristic parameters and multi-period characteristic parameters of the fault arc are obtained.

[0082] It should be noted that, in view of the fact that the waveform characteristics of the current signal are extremely vulnerable to interference from the circuit load and circuit topology, the present invention uses the mother wavelet coif1 to perform one-layer decomposition on the current signal. During the decomposition process, by optimizing the wavelet decomposition parameters (such as reasonably selecting the decomposition level, accurately setting the threshold, etc.), it is ensured that the 50Hz background signal and low-frequency noise signal can be effectively removed, and the characteristic information related to the fault arc is retained to the greatest extent. The first-layer detail coefficients are used as the preprocessing signals for subsequent fault arc feature extraction, and feature parameter extraction is carried out from two dimensions: single cycle and multi-cycle.

[0083] Furthermore, it should be noted that the single-cycle characteristic parameters include D1 energy, D1 Shannon entropy, D1 range, pulse factor, interval time, pulse peak standard deviation, zero-sequence current standard deviation, and zero-sequence current Shannon entropy.

[0084] Taking D1 energy as an example, the first-layer detail coefficients d j (j = 1, 2,..., N / 2) of the preprocessing signal are traversed one by one, and the cumulative calculation is performed according to the formula to obtain the D1 energy value within this cycle, where N is the number of sampling points in one current cycle.

[0085] Taking the pulse factor as an example, first find the maximum value max(|p j | of the zero-sequence current coupling signal p within a unit current cycle, and then calculate its ratio to the average absolute value j |, that is, the pulse factor to accurately characterize the pulse characteristics of the current signal within one cycle. In this way, it accurately characterizes the pulse characteristics of the current signal within one cycle.

[0086] In addition, D1 Shannon entropy D1 range C r = max(d j ) - min(d j ), interval time (f s is the sampling frequency), pulse peak standard deviation (x1 represents the maximum value in the sequence p j (j = 1, 2,..., N), x2 represents the second maximum value in the sequence p j (j = 1, 2,..., N), and so on, m is the number of pulse peaks participating in the calculation), zero-sequence current standard deviation zero-sequence current Shannon entropy Accurately characterize the pulse characteristics of the current signal within one cycle through the above single-cycle characteristic parameters.

[0087] Furthermore, it should be noted that the multi-cycle characteristic parameters include the standard deviation of D1 energy, the standard deviation of D1 Shannon entropy, the standard deviation of D1 range, the standard deviation of impulse factor, and the standard deviation of zero-sequence current Shannon entropy. Taking the standard deviation of D1 energy as an example, first calculate the D1 energy within multiple adjacent current cycles q is the number of calculation cycles, and then according to the formula calculate the standard deviation, where is the average value of D1 energy in multiple cycles. The calculation methods of other multi-cycle characteristic parameters are similar. Through the above multi-cycle characteristic parameters, the fluctuation of D1 energy in multiple cycles can be effectively reflected, providing more comprehensive and accurate characteristic information for fault arc detection.

[0088] Step S2102: Perform feature reconstruction on the fault arc characteristic parameters to reduce the fuzziness of fault characteristics caused by circuit noise interference, and obtain the reconstructed fault arc characteristic parameters;

[0089] Specifically, in step S2102, the Teager energy operator is used to enhance the mutation characteristics in the zero-sequence current coupling signal of the circuit data to obtain the fault arc characteristic parameters after feature enhancement; using the periodic symmetry characteristic of the AC power supply voltage, calculate the ratio of the fault arc characteristic parameters after feature enhancement within the front and back 10 ms time windows to obtain the reconstructed fault arc characteristic parameters.

[0090] It should be noted that for the problem that the boundary between normal and fault states becomes unclear after some fault characteristics are interfered by circuit noise, the present invention introduces the Teager energy operator to process the zero-sequence current coupling signal. For the discrete zero-sequence current coupling signal {x1, x2,..., x j ,..., x N}, calculate the energy value of each sampling point according to the formula Perform point-by-point calculation on the zero-sequence current coupling signal, thereby effectively enhancing the mutation characteristics in the signal.

[0091] Furthermore, it should be noted that using the low-voltage AC power supply voltage u sBased on the periodic symmetry characteristic of (t) (i.e., the electrical signals in the first 10 ms and the last 10 ms are symmetric), the fault arc characteristics are reconstructed (by calculating the ratio of the fault arc characteristic parameters in the time windows of the first and last 10 ms). In the normal state, the fault arc characteristic parameters extracted from the electrical signals of the front and back parts are at the same order of magnitude, and their ratio fluctuates within a small range near 1; when a series fault arc occurs, due to the unstable characteristics of the fault arc, the fault arc characteristic parameters extracted from the electrical signals of the front and back parts show obvious differences, and their ratio fluctuates significantly near 1. Based on this characteristic, the characteristic ratio is used to reconstruct the fault arc characteristic parameters (single-cycle characteristic parameters - pulse factor ratio, zero-sequence current Shannon entropy ratio, D1 energy ratio, D1 Shannon entropy ratio, D1 range ratio, etc., and the corresponding multi-cycle characteristic parameters - standard deviation of D1 energy ratio, standard deviation of D1 Shannon entropy ratio, standard deviation of D1 range ratio, standard deviation of pulse factor ratio, standard deviation of zero-sequence current Shannon entropy ratio). Through this characteristic ratio reconstruction, the distinguishability of the characteristics under different working conditions is significantly improved, laying a solid foundation for the subsequent machine learning model to accurately detect fault arcs. Figure 3 is a schematic flowchart of the feature reconstruction according to the embodiment of the present application, as Figure 3 shown, it is necessary to reconstruct the single-cycle characteristic parameters first, and then reconstruct the corresponding multi-cycle characteristic parameters;

[0092] Figure 4 is a comparison schematic diagram of the pulse factor ratio before and after reconstruction according to the embodiment of the present application, Figure 5 is a comparison schematic diagram of the zero-sequence current Shannon entropy ratio before and after reconstruction according to the embodiment of the present application, Figure 6 is a comparison schematic diagram of the D1 energy ratio before and after reconstruction according to the embodiment of the present application, as Figures 4 to 6 shown, the dark dots are the features after reconstruction, and the light dots are the features before reconstruction. It can be seen that the distribution of the characteristic parameters after reconstruction has the advantage of being more concentrated, which can improve the distinguishability from noise.

[0093] Step S2103, training the machine learning model based on the circuit data and the reconstructed fault arc characteristic parameters to obtain a trained machine learning model.

[0094] Specifically, in step S2103, a machine learning model based on the decision tree algorithm is constructed. Among them, the machine learning model uses the information gain ratio as the metric standard for feature selection. By calculating the information gain ratios of different features, the features with the largest information gain ratio are selected for decision tree node splitting; the circuit data and the reconstructed fault arc characteristic parameters are input into the machine learning model to determine the network weights of the model, and a trained machine learning model is obtained.

[0095] It should be noted that a decision tree is used as the classifier of the machine learning model (the depth of the decision tree can be less than 10). When constructing the decision tree, the information gain ratio is used as the measurement criterion for feature selection. By calculating the information gain ratio of different features, the feature with the maximum information gain ratio is selected for node splitting to optimize the classification performance of the decision tree. Based on the reconstructed fault arc feature parameters and training data, the relevant network weights of the classification rules and thresholds of the model are determined (for example, when the pulse factor ratio exceeds the set threshold T1 and the standard deviation of the D1 energy ratio is lower than the set threshold T2, the decision tree determines that a fault arc has occurred). The relevant network weights of the classification rules and thresholds need to be trained and optimized according to a large amount of experimental data to ensure the accuracy and reliability of the detection.

[0096] After step S210, the method includes step S211. If the machine learning model detects a fault arc in the circuit, the protection switch is triggered to cut off the circuit through the protection switch.

[0097] It should be noted that the detection result of the detection device is used as the trigger signal for the operation of the fault arc protection switch. When a fault arc is detected, the protection switch should cut off the circuit within the set time; according to the fault arc characteristics extracted in the detection method and the set detection algorithm, the operation logic of the protection switch is optimized to improve the operation accuracy and reliability of the protection switch, so that the protection switch can act in a timely and accurate manner according to the detection result, effectively cut off the faulty circuit, and ensure the safety of the electrical system.

[0098] Through the above steps in the embodiments of the present application, the following beneficial technical effects can be achieved:

[0099] 1. Comprehensive consideration of system factors: It can highly simulate various load types, complex circuit topologies, different arcing methods, and circuit noises in a real electrical system. By comprehensively considering these factors, the obtained data is more representative, providing a solid and reliable basis for in-depth research on fault arc characteristics and accurate detection of fault arcs.

[0100] 2. Improvement of detection accuracy: Through the innovative fault arc feature reconstruction technology, the distinguishability of features under different working conditions is significantly enhanced. This technology effectively reduces the misoperation rate of the detection model under unknown working conditions, greatly improving the accuracy and reliability of fault arc detection, and providing a more effective technical means for preventing electrical fires.

[0101] 3. Engineering application value: It has a wide range of engineering application prospects and can be directly applied to low-voltage AC distribution systems. At the same time, it provides an important technical reference for the development of fault arc protection switches, which has important practical significance for ensuring the safe and stable operation of electrical systems.

[0102] It should be noted that the steps shown in the above process or the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0103] In one embodiment, Figure 7 is a schematic internal structure diagram of an electronic device according to an embodiment of the present application. As Figure 7 shown, an electronic device is provided. The electronic device can be a server, and its internal structure diagram can be as Figure 7 shown. The electronic device includes a processor, a network interface, an internal memory, and a non-volatile memory connected through an internal bus. Among them, the non-volatile memory stores an operating system, a computer program, and a database. The processor is used to provide computing and control capabilities. The network interface is used to communicate with external terminals through a network connection. The internal memory is used to provide an environment for the operation of the operating system and the computer program. The computer program, when executed by the processor, is used to implement the above-mentioned training process of the machine learning model. The database is used to store data.

[0104] Those skilled in the art can understand that Figure 7 the structure shown in

[0105] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the electronic device to which the solution of the present application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. This computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0106] Those skilled in the art should understand that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0107] The above embodiments only represent several implementation manners of this application. The description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.

Claims

1. A series fault arc detection device based on multi-criterion fusion, characterized in that The device includes an integrated data acquisition unit, a signal processing unit, a feature extraction and analysis unit, and a decision-making and judgment unit; The data acquisition unit is used to acquire circuit data of the circuit to be detected; The signal processing unit is used to preprocess the circuit data to improve the data quality and obtain the preprocessed circuit data; The feature extraction and analysis unit is used to extract the fault arc feature parameters of the fault arc from the circuit data; and perform feature reconstruction on the fault arc feature parameters to obtain the reconstructed fault arc feature parameters; The decision-making and judgment unit is used to input the circuit data and the reconstructed fault arc feature parameters into a trained machine learning model to determine whether a fault arc occurs in the circuit to be detected.

2. The device according to claim 1, wherein The data acquisition unit is used to acquire the circuit data of the circuit to be detected through a current sensor and a zero-sequence current sensor, and convert the circuit data from an analog signal to a digital signal through an A / D conversion module.

3. The device according to claim 2, characterized in that, The signal processing unit is used to filter the circuit data converted into a digital signal through a digital filter, and perform gain adjustment on the filtered circuit data through an amplifier to improve the data quality of the circuit data.

4. The device according to claim 1, characterized in that, The training process of the machine learning model includes: Constructing a first experimental scenario and a second experimental scenario, where the first experimental scenario is a circuit scenario without interference, and the second experimental scenario is a circuit scenario with interference; In the first experimental scenario, by changing the circuit load, circuit topology, and arc generation method in the experimental circuit, a number of first normal conditions and first fault conditions are simulated; In the second experimental scenario, by changing the circuit load, circuit topology, and arc generation method in the experimental circuit, a number of second normal conditions and second fault conditions are simulated; Collecting the circuit data generated under the first normal condition, the first fault condition, the second normal condition, and the second fault condition; Training the machine learning model based on the circuit data to obtain a trained machine learning model.

5. The device according to claim 4, characterized in that, Training the machine learning model based on the circuit data to obtain a trained machine learning model includes: Extracting the fault arc feature parameters of the fault arc from the circuit data; Performing feature reconstruction on the fault arc feature parameters to reduce the fuzziness of the fault features caused by circuit noise interference, and obtaining the reconstructed fault arc feature parameters; Training the machine learning model based on the circuit data and the reconstructed fault arc feature parameters to obtain a trained machine learning model.

6. The device according to claim 5, characterized in that, Extracting the fault arc feature parameters of the fault arc from the circuit data includes: Decomposing the current signal of the circuit data by using the mother wavelet coif1 to obtain a preprocessed signal; Extracting the fault arc feature parameters from the preprocessed signal based on two dimensions of single cycle and multi-cycle to obtain the single-cycle feature parameters and multi-cycle feature parameters of the fault arc.

7. The device according to claim 5, characterized in that, Performing feature reconstruction on the fault arc feature parameters to reduce the fuzziness of the fault features caused by circuit noise interference, and obtaining the reconstructed fault arc feature parameters includes: Enhance the mutation characteristics in the zero-sequence current coupling signal of the circuit data by using the Teager energy operator to obtain the fault arc characteristic parameters after feature enhancement; Utilize the periodic symmetry characteristic of the AC power supply voltage to calculate the ratio of the fault arc characteristic parameters after feature enhancement within the front and back 10 ms time windows to obtain the reconstructed fault arc characteristic parameters.

8. The device according to claim 5, characterized in that Train a machine learning model based on the circuit data and the reconstructed fault arc characteristic parameters, and the trained machine learning model includes: Construct a machine learning model based on the decision tree algorithm. Among them, the machine learning model uses the information gain ratio as the measurement criterion for feature selection. By calculating the information gain ratios of different features, select the features with the maximum information gain ratio for decision tree node splitting; Input the circuit data and the reconstructed fault arc characteristic parameters into the machine learning model, determine the network weights of the model, and obtain the trained machine learning model.

9. The device according to claim 4, characterized in that, Build a second experimental scenario, including: Set up a bypass interference circuit to build a second experimental scenario on the basis of the first experimental scenario. Among them, the bypass interference circuit uses an AC / AC converter and an AC / DC inverter as loads to simulate and generate harmonic interference and voltage fluctuation interference.

10. The device according to claim 1, characterized in that If the trained machine learning model determines that a fault arc occurs in the circuit to be detected, trigger the protection switch to cut off the circuit through the protection switch.

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