Chip Trojan detection method, device, program product, medium and electronic device

Abstract

The present application belongs to the field of chip and its detection technology, and proposes a chip Trojan detection method, device, program product, medium and electronic device. Among them, the method includes: obtaining a target code module for describing at least one corresponding operation function in the chip to be detected, and the operation function is implemented by multiple transistors integrated according to the set logic; constructing a data flow graph that matches the target code module, and the data flow graph is used to characterize the data operation logic of the target code module during operation; identifying the target sub-data flow graph with malicious characteristics in the data flow graph through a pre-trained Trojan recognition model, and the target sub-data flow graph reflects the presence of a chip Trojan in the chip to be detected. The technical solution provided by this application can improve the detection capability of chip Trojans.

Description

Technical Field

[0001] The present application belongs to the field of chips and their detection technology, and in particular relates to a chip Trojan detection method, device, program product, medium and electronic equipment. Background Art

[0002] With the continuous advancement of integrated circuit technology, chip security is receiving increasing attention. Chip Trojans (also known as hardware Trojans) are a potential security threat and can cause serious consequences such as chip malfunction and information leakage. Effective detection of chip Trojans during the integrated circuit design phase is crucial for ensuring chip security.

[0003] Currently, chip Trojan detection technologies primarily include test pattern generation, formal verification, code analysis, machine learning, and graph matching. However, these technologies have limitations, including the inability to cover all potential trigger conditions, an inability to handle unknown types of malicious behavior, the need for manual analysis that can easily miss hidden Trojans, and a reliance on known Trojan libraries, resulting in high computational complexity. These limitations significantly restrict chip Trojan detection capabilities. Therefore, improving chip Trojan detection capabilities is an urgent technical challenge. Summary of the Invention

[0004] The embodiments of the present application provide a chip Trojan detection method, device, computer program product, computer-readable storage medium, and electronic device, which can improve the chip Trojan detection capability to a certain extent.

[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0006] According to a first aspect of an embodiment of the present application, a chip Trojan detection method is provided, the method comprising: obtaining a target code module, the target code module being used to describe at least one corresponding operation function in a chip to be detected, the operation function being implemented by a plurality of transistors integrated according to a set logic; constructing a data flow graph matching the target code module, the data flow graph being used to characterize the data operation logic of the target code module during operation; identifying a target sub-data flow graph with malicious features in the data flow graph through a pre-trained Trojan recognition model, the target sub-data flow graph reflecting the presence of a chip Trojan in the chip to be detected, the Trojan recognition model comprising a graph attention neural network module, the graph attention neural network module being used to focus on the sub-data flow graph with malicious features in the data flow graph.

[0007] In some embodiments of the present application, based on the aforementioned scheme, obtaining the target code module includes: obtaining a hardware description program corresponding to the chip to be tested; determining at least one code module in the hardware description program, wherein each code module is used to describe the corresponding operation function in the chip to be tested; and flattening the at least one code module to integrate the at least one code module into a target code module.

[0008] In some embodiments of the present application, based on the aforementioned scheme, the constructing of a data flow graph that matches the target code module includes: parsing the target code module to generate an abstract syntax tree of the target code module, the abstract syntax tree including multiple signals; extracting the dependency relationship between each adjacent signal from the abstract syntax tree, and constructing a dependency tree corresponding to each adjacent signal based on the dependency relationship, the dependency tree including two signal nodes and a pointing relationship between the two signal nodes; merging the dependency trees to obtain an initial data flow graph that matches the target code module; removing redundant signal nodes in the initial data flow graph to obtain a data flow graph that matches the target code module.

[0009] In some embodiments of the present application, based on the aforementioned scheme, the identification of the target sub-data flow graph with malicious features in the data flow graph by a pre-trained Trojan recognition model includes: converting each signal node in the data flow graph into a one-hot encoding, and converting the pointing relationship between each signal node in the data flow graph into an adjacency matrix; inputting the one-hot encoding corresponding to each signal node and the adjacency matrix into the Trojan recognition model, so that the Trojan recognition model can identify the target sub-data flow graph with malicious features in the data flow graph.

[0010] In some embodiments of the present application, based on the aforementioned solution, the Trojan identification model further includes a first alternating fully connected layer network module, which is used to locate the position of each sub-data flow graph in the data flow graph.

[0011] In some embodiments of the present application, based on the aforementioned scheme, the Trojan identification model also includes a second alternating fully connected layer network module, which is used to calculate the probability that each sub-data flow graph in the data flow graph has malicious features.

[0012] In some embodiments of the present application, based on the aforementioned solution, the second alternating fully connected layer network module is used to calculate the probability that each sub-data flow graph in the data flow graph has malicious features in each attribute.

[0013] In some embodiments of the present application, based on the aforementioned scheme, the feature matrix input to the first alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module, and the feature matrix input to the second alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module and the feature matrix output by the first alternating fully connected layer network module.

[0014] In some embodiments of the present application, based on the aforementioned scheme, the Trojan identification model is trained through the following steps: obtaining sample data flow graphs corresponding to multiple sample code modules, wherein the sub-data flow graphs with malicious features in the sample data flow graphs are marked with Trojan labels; based on the sample data flow graphs corresponding to the multiple sample code modules, a pre-constructed Trojan identification model framework is supervised trained to obtain the Trojan identification model.

[0015] In some embodiments of the present application, based on the aforementioned solution, the data flow graph is replaced with a control flow graph.

[0016] According to a second aspect of an embodiment of the present application, a chip Trojan detection device is provided, the device comprising: an acquisition unit for acquiring a target code module, the target code module being used to describe at least one corresponding operation function in a chip to be detected, the operation function being implemented by a plurality of transistors integrated according to a set logic; a construction unit for constructing a data flow graph matching the target code module, the data flow graph being used to characterize the data operation logic of the target code module during operation; an identification unit for identifying a target sub-data flow graph with malicious features in the data flow graph through a pre-trained Trojan identification model, the target sub-data flow graph reflecting the presence of a chip Trojan in the chip to be detected, the Trojan identification model comprising a graph attention neural network module, the graph attention neural network module being used to focus on the sub-data flow graph with malicious features in the data flow graph.

[0017] According to a third aspect of an embodiment of the present application, a computer program product is provided, which includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so that a computer device having the processor executes to implement the operations performed by the method described in the first aspect above.

[0018] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one computer program instruction is stored. The at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the method described in the first aspect above.

[0019] According to a fifth aspect of an embodiment of the present application, an electronic device is provided, comprising one or more processors and one or more memories, wherein at least one computer program instruction is stored in the one or more memories, and the at least one computer program instruction is loaded and executed by the one or more processors to implement the operations performed by the method described in the first aspect above.

[0020] The technical solution proposed in this application significantly improves chip Trojan detection capabilities by converting target code modules into data flow graphs and analyzing them using a pre-trained Trojan recognition model that includes a graph attention neural network module. Specifically, the data flow graph comprehensively reflects the data operation logic and control flow of the target code module during operation, providing a deeper understanding of potential abnormal behavior within the chip. By analyzing these graph structures, the Trojan recognition model can automatically focus on and identify sub-data flow graphs with malicious characteristics, effectively detecting various types and forms of chip Trojans, including stealthy and complex ones. This solution eliminates the need for trusted benchmarks and Trojan libraries as references for Trojan detection, not only improving the accuracy and robustness of chip Trojan detection but also significantly increasing the automation and efficiency of chip Trojan detection, significantly reducing the workload of manual detection and the rate of false positives and false negatives. Furthermore, as chip design becomes increasingly complex, this solution can continuously adapt to and generalize the detection needs of new chip Trojans, thereby enhancing chip security. Therefore, this technical solution can effectively improve chip Trojan detection capabilities.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0023] Figure 1 A flowchart of a chip Trojan detection method in an embodiment of the present application is shown;

[0024] Figure 2 shows a data flow diagram in an embodiment of the present application;

[0025] Figure 3 A model framework diagram of a Trojan horse identification model in an embodiment of the present application is shown;

[0026] Figure 4A block diagram of a chip Trojan detection device in an embodiment of the present application is shown;

[0027] Figure 5 A schematic structural diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0030] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should also be noted that in the accompanying drawings, certain components that do not affect the explanation of the technical solutions of this application have been omitted for clarity.

[0031] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0032] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0033] In order to enable those skilled in the art to better understand this application, the technical concepts and application background involved in this application are first briefly explained.

[0034] Chip Trojans: Chip Trojans (HT), also known as hardware Trojans, are malicious circuits or modules intentionally implanted in integrated circuits (ICs). These malicious circuits are typically introduced during the chip design or manufacturing process, with the intent to steal information, disrupt chip functionality, cause system failures, or provide attackers with unauthorized access. Chip Trojans can take on a variety of forms and characteristics. They can be very small circuit structures, making them difficult to detect using conventional detection methods. These Trojans can be triggered under specific conditions, such as specific input signal sequences, time intervals, or environmental conditions. Once triggered, they can perform various malicious actions, such as leaking sensitive information, tampering with data, rendering the chip inoperable, or bypassing security mechanisms.

[0035] In today's integrated circuit industry, chip security is paramount. Chip Trojans, as a potential security threat, pose significant risks to chip operation and information security. With the rapid development of integrated circuit technology and the increasing complexity of chips, detecting chip Trojans has become increasingly difficult.

[0036] Currently, chip Trojan detection technologies primarily include test pattern generation, formal verification, code analysis, machine learning, and graph matching. However, these methods all have limitations. Test pattern generation relies on specific test vectors to trigger Trojans, but often fails to cover all potential triggering conditions, making some Trojans difficult to detect. Formal verification detects Trojans using predefined security properties, but this approach is often ineffective against unknown types of malicious behavior. Code analysis uses coverage metrics to flag suspicious signals, but requires manual analysis, which is not only inefficient but also prone to missing hidden Trojans. Machine learning and graph matching methods utilize graph structures to represent hardware designs, but they rely on known Trojan libraries and have high computational complexity, facing numerous challenges in practical applications.

[0037] In addition, there are some other problems with the existing technology. For example, many methods rely on golden reference models and require a trusted design without Trojans as a benchmark. However, in actual scenarios, it is very difficult to obtain a completely trusted design without Trojans. At the same time, the existing technology has insufficient detection capabilities for unknown Trojans and cannot effectively identify new Trojans that are not included in the training library. These problems have seriously affected the accuracy and efficiency of chip Trojan detection. There is an urgent need for a more effective detection method to improve the detection capabilities of chip Trojans. In this case, the present application proposes a chip Trojan detection solution to improve the detection capabilities of chip Trojans.

[0038] The following describes the implementation details of the technical solution of the embodiment of the present application:

[0039] Reference Figure 1 , shows a flowchart of a chip Trojan detection method in an embodiment of the present application, which can be executed by a device with a computing and processing function, referring to Figure 1 As shown, the chip Trojan detection method includes at least steps 110 to 130, which are described in detail as follows:

[0040] In step 110 , a target code module is obtained, where the target code module is used to describe at least one corresponding operation function in the chip to be detected, where the operation function is implemented by a plurality of transistors integrated according to a set logic.

[0041] In this application, the target code module can be a code snippet, unit, or function used to describe at least one computing function in the chip to be tested. Typically, these code modules can be written in a hardware description language (such as Verilog, VHDL, SystemVerilog, etc.), which can clearly express the structure, data flow, signal interaction, and control logic of each computing function within the chip. Each computing function can be composed of a number of basic circuit modules such as logic gates, triggers, and registers, and can ultimately be implemented in physical implementation by multiple transistors integrated according to a set logic. It should be noted that the set logic for integrating multiple transistors to implement the computing function can be defined by the target code module.

[0042] In the present application, when testing a chip, for example, in a chip containing an AES encryption function, the Verilog module describing the AES algorithm may be located and extracted as a target code module for subsequent data flow and control flow analysis; for example, in the detection of a RISC-V processor chip, the Verilog code of the arithmetic logic unit (ALU) module that implements operations such as addition, subtraction, AND, OR, and shift may be identified and extracted as a target code module to provide a basis for subsequent graph structure construction and Trojan detection; for example, for a complex SoC chip, multiple functional modules related to the data path (such as register files, multipliers, accumulators, etc.) may be flattened and integrated, and analyzed as a whole target code module to discover cross-module Trojan logic.

[0043] Specifically, in this application, the object code module can be obtained by performing the following steps 111 to 113:

[0044] Step 111: Obtain the hardware description program corresponding to the chip to be tested.

[0045] Step 112: Determine at least one code module in the hardware description program, wherein each code module is used to describe a corresponding operation function in the chip to be tested.

[0046] Step 113: Flatten the at least one code module to integrate the at least one code module into a target code module.

[0047] In this application, a hardware description program is the source code used to describe the chip's circuit structure and functionality, typically written in a hardware description language (HDL) such as Verilog, VHDL, or SystemVerilog. This program contains detailed definitions of the chip's various modules, signals, data paths, and control logic. In actual application scenarios, the complete HDL source code file for the chip to be tested can be retrieved from the chip design team or design database. If the chip to be tested is a third-party IP core, the hardware description program can also be obtained through the source code or intermediate representation file provided by the vendor.

[0048] In this application, a code module refers to a unit, entity, process, or function in an HDL program that independently describes a specific function. Each code module corresponds to an operational function in the chip to be tested, such as an adder, multiplier, state machine, register group, etc.

[0049] In this application, flattening refers to integrating multiple hierarchical code modules into a non-hierarchical target code module. Its purpose is to eliminate the hierarchical boundaries between modules and integrate the signals, operations, and control logic originally scattered in different code modules into a whole, which is convenient for subsequent data flow and control flow analysis. The specific implementation method may include: first, expanding the module instantiation and inlining all called sub-code modules into the top-level module; then, merging the signal definitions and logic descriptions of each code module, unifying the namespace, eliminating duplication and conflicts; finally, retaining the dependencies and control relationships between the original signals to ensure that the functional logic remains unchanged.

[0050] In order to enable those skilled in the art to better understand the present application, the flattening process is described below with reference to a specific embodiment:

[0051] Assume that there is the following original hierarchical Verilog code:

[0052] / / Submodule

[0053] module adder(input [3:0] a, input [3:0]b, output [4:0] sum);

[0054] assign sum = a + b;

[0055] endmodule

[0056] / / Top-level module

[0057] module top(input [3:0] x, input [3:0]y, output [4:0] z);

[0058] wire [4:0] temp;

[0059] adder u1(.a(x), .b(y), .sum(temp));

[0060] assign z = temp;

[0061] endmodule

[0062] By flattening the above submodules and top-level modules (i.e., the two code modules), the functionality of the adder module is directly expanded into the top module, and the module instantiation is no longer retained, resulting in the following target code module 1:

[0063] module top(input [3:0] x, input [3:0]y, output [4:0] z);

[0064] wire [4:0] temp;

[0065] / / Directly expand the adder function

[0066] assign temp = x + y;

[0067] assign z = temp;

[0068] endmodule

[0069] In this application, flattening processing can break the original hierarchical structure limitations, allowing subsequent data flow diagrams to cover signals and logical relationships across modules and levels, thereby improving the comprehensiveness and accuracy of chip Trojan detection and helping to discover hidden Trojans hidden between modules.

[0070] In this application, based on steps 111 to 113, the target code module can be systematically and accurately extracted and integrated from the hardware description program of the chip to be tested. This not only ensures the completeness and clear structure of the input data for subsequent Trojan detection and analysis, but also provides a solid foundation for detecting complex Trojan behaviors across modules, thereby significantly improving the chip Trojan detection capabilities and engineering practical value.

[0071] Continue to refer to Figure 1 In step 120, a data flow graph matching the target code module is constructed, and the data flow graph is used to represent the data operation logic of the target code module during operation.

[0072] In this application, a data flow graph (DFG) is a graphical representation method used to describe the flow and processing of data in a system. In hardware design, data flow graphs are mainly used to show the data flow and operation process between various signals. Specifically, the nodes in the data flow graph represent signals or operations, and the edges represent the direction of data flow. Through the data flow graph, one can clearly see the entire process from data input to output after a series of processing operations. It emphasizes the flow and changes of data, as well as the data dependencies between various operations. In this application, the input target code module is subjected to steps such as preprocessing, parsing, data flow analysis, merging and pruning to generate a data flow graph. This data flow graph is used for subsequent hardware Trojan detection. By analyzing and learning the graph structure, automated detection of hardware Trojans is achieved.

[0073] In this application, it should be noted that it is also possible to construct only a control flow graph (CFG) that matches the target code module, replacing the data flow graph described above with a CFG. Specifically, a control flow graph (CFG) is a graphical representation of a program's control flow. In a program, control flow determines the execution order and branching of the program. The nodes of a CFG represent basic blocks of the program, which are a set of statements executed sequentially and have only one entry and one exit. The edges of a CFG represent the possible execution paths of the program, reflecting control structures such as conditionals and loops within the program. A CFG provides an intuitive understanding of the program's execution path and logical structure, facilitating analysis of program behavior, identification of potential errors, and optimization. For example, in software testing, test cases can be generated based on the CFG to cover different execution paths of the program. In program analysis and optimization, CFG analysis can be used to identify loop structures, conditionals, and other structures, allowing for appropriate optimization.

[0074] Specifically, in step 120, a data flow graph and / or a control flow graph matching the target code module is constructed, which can be performed according to the following steps 121 to 124:

[0075] Step 121: Parse the target code module to generate an abstract syntax tree of the target code module, where the abstract syntax tree includes multiple signals.

[0076] Step 122: extract the dependency relationship between each adjacent signal from the abstract syntax tree, and construct a dependency tree corresponding to each adjacent signal based on the dependency relationship, wherein the dependency tree includes two signal nodes and a pointing relationship between the two signal nodes.

[0077] Step 123: Merge the dependency trees to obtain an initial data flow graph that matches the target code module.

[0078] Step 124: remove redundant signal nodes in the initial data flow graph to obtain a data flow graph that matches the target code module.

[0079] In this application, it is first necessary to explain that an Abstract Syntax Tree (AST) is a tree-like data structure used to represent the structure of program code. It is an abstract representation of source code, converting the source code's grammatical structure into a tree structure. Each signal represents a syntactic element in the source code, such as a variable, function, register, function call, statement, etc., and the relationship between signals represents the grammatical relationship between these syntactic elements. An AST can be constructed by performing syntactic analysis on the source code. In an AST, leaf signals typically represent basic syntactic units, such as identifiers and constants, while internal signals represent more complex syntactic structures, such as expressions, statement blocks, and function definitions. The structure of the AST reflects the syntactic structure of the source code, making source code analysis and processing more convenient and efficient.

[0080] In this application, it is also necessary to explain that the dependency tree is a tree structure built with the signal as the root node, which is used to represent the dependency relationship between signals. In hardware design, the generation of a signal may depend on the input or operation of other signals. By constructing a dependency tree, the dependency between each signal and other signals can be clearly displayed. Specifically, the dependency tree is constructed by extracting the data flow information of each signal from the abstract syntax tree, and then taking the signal as the root node and the signal it depends on as the child node to form a tree structure. In this way, through the dependency tree, you can intuitively understand how the generation of a signal depends on other signals, as well as the transmission and influence relationship between signals, which helps to analyze the structure and behavior of the hardware design and discover potential security issues.

[0081] In this application, a suitable programming language parser (e.g., one based on Pyverilog, ANTLR, Clang, Babel, etc.) can be used to perform lexical and syntactic parsing on the target code module. An abstract syntax tree (ABST) is then generated based on the parsing results. Multiple signals (variables, registers, function calls, etc.) are identified and marked in the ABST. These signals serve as the basis for subsequent dependency analysis.

[0082] After marking multiple signals in the abstract syntax tree, you can traverse the tree to identify dependencies between adjacent signals, which may appear in the same expression, statement, or basic block. For example, the statement SUM = A + B indicates that SUM depends on A and B. Dependencies are mainly categorized as data dependencies and control dependencies. Data dependencies are reflected in the influence of the right value on the left value in an assignment statement, while control dependencies involve the impact of conditional judgments on the execution of subsequent statements.

[0083] For each pair of adjacent signals, a dependency tree can be constructed. The tree's nodes represent signals, the edges represent dependencies, and the direction of the edges indicates the direction of the dependency (for example, from the dependent signal to the dependent signal). A dependency tree is typically presented as a directed tree structure, reflecting the chain of signal transmission and influence. For example, a line from A to SUM indicates that data flows from A to SUM. When constructing a dependency tree, it is important to distinguish between different types of dependencies and, when dealing with complex dependencies, ensure the accuracy and completeness of the dependencies.

[0084] After building the dependency tree, the local dependency trees can be integrated into a global dependency graph, that is, an initial data flow graph that matches the target code module to reflect the signal flow and / or control flow of the entire target code module. In the specific operation, the various dependency trees are merged according to the shared signal nodes to form a unified graph structure. During the merging process, it is necessary to avoid duplicate nodes and unify the node representations of the same signal. The generated graph is the initial data flow graph, which reflects the data transfer and dependency between signals. During the merging process, the consistency and correctness of the graph structure must be maintained.

[0085] In this application, redundant signal nodes refer to signal nodes that have no actual operation or control significance in the initial data flow graph, or do not contribute to the recognition results, such as constant signals, unused signals, and duplicate nodes. In the process of removing redundant signal nodes, isolated nodes, useless nodes, and duplicate nodes can be identified through graph traversal and analysis, and these redundant signal nodes can be screened and deleted according to preset rules (such as node degree, signal type, whether they participate in the critical path, etc.), and the edge connection relationship is adjusted to ensure the consistency and correctness of the graph structure. The advantage of removing redundant signal nodes is that it can simplify the graph structure and reduce the computational complexity, thereby improving the processing efficiency and accuracy of the subsequent Trojan identification model. For example, in the adder graph, if there are unused signal nodes or constant nodes (such as fixed value "0" signals), removing them can obtain a simpler final data flow graph.

[0086] In this application, in order to enable those skilled in the art to better understand, a data flow diagram corresponding to an object code module is given below in combination with an embodiment of the object code module.

[0087] In this application, please refer to the following target code module 2:

[0088] “module top(

[0089] input rst, / / reset signal, high level is valid

[0090] input clock, / / clock signal, high level is valid

[0091] input io_sfence, / / Input judgment condition signal

[0092] input [32:0] flag, / / 128-bit wide input signal state

[0093] output reg top.v_17 / / Output signal top.v_17 );

[0095] always @(posedge clock or posedge rst) begin

[0096] if (io_sfence==0) begin

[0097] top.v_17 <= 1'h0; / / When io_sfence is non-negative, assign the output signal top.v_17 to 0

[0098] end

[0099] else if (6'h11 == io_sfence) begin

[0100] top.v_17 <= 1'h1; / / When io_sfence is 11, assign the output signal top.v_17 to 1

[0101] end

[0102] else begin

[0103] top.v_17 <= 1'h2; / / Otherwise, the output signal top.v_17 is assigned a value of 2

[0104] end

[0105] end

[0106] endmodule".

[0107] Based on the target code module 2 exemplified above, it can be understood that the main function of the module top defined by this Verilog code module is to determine the value of the output signal top.v_17 based on the input reset signal rst, clock signal clock, and status signal io_sfence. When reset and clock are high and io_sfence is 0, top.v_17 is set to 0; when rst and clock are high and io_sfence is 11, top.v_17 is set to 1; when rst and clock are high and io_sfence is not 0 or 11, top.v_17 is set to 2. In this module, the always block is used to perform corresponding operations based on changes in the input signals, where the sensitive signal list of the always block is io_sfence1.

[0108] For the target code module 2 above, build a corresponding data flow diagram. Please refer to Figure 2 , shows the data flow diagram in an embodiment of the present application.

[0109] For example Figure 2 The data flow diagram shown is explained as follows:

[0110] First, the top-level node “top.v_17” is the starting point of the data flow, representing a trigger signal or a master control signal.

[0111] Secondly, the "Branch1" node represents the judgment of a condition, which determines which branch the data flows to. "COND" represents the judgment condition branch. "TRUE" means that if the judgment condition branch is true, the data flows to the TRUE branch; "FALSE" means that if the judgment condition branch is false, the data flows to the FALSE branch.

[0112] Third, the "Eq1" node represents an equality judgment; the "top_io_sfence" node represents the judgment signal; the "1'h0" node represents the number 0; this branch is used to determine whether top_io_sfence is equal to 0. If so, top.v_17 is assigned a value of 0.

[0113] Fourth, the "Branch2" node indicates that if the condition in the "Branch1" node is false, the data flow goes to the branch under the "Branch2" node.

[0114] Fifth, the "Eq2" node represents an equality judgment, the "top_io_sfence" node represents a status signal; the "6'h11" node represents the number 6'h11; the "1'h1" node represents the number 1; this branch is used to determine whether top_io_sfence is equal to 6'h11. If so, top.v_17 is assigned a value of 1.

[0115] Sixth, the "Branch3" node indicates that if the condition in the "Branch2" node is false, the data flow goes to the branch under the "Branch3" node.

[0116] Seventh, the "1'h2" node represents the number 2; this branch is used to assign the value of top.v_17 to 2.

[0117] It can be seen that Figure 2 The data flow diagram shown here describes how a signal (top.v_17) enters the system and passes through a series of conditional checks (branches). Each branch uses an Eq node for equality checks. The result of each branch determines how the data continues to flow, ultimately affecting an output or control signal.

[0118] In step 130, a pre-trained Trojan identification model is used to identify a target sub-data flow graph with malicious features in the data flow graph, and the target sub-data flow graph reflects the presence of a chip Trojan in the chip to be detected.

[0119] In this application, malicious features refer to program features that can reflect Trojan behavior. Furthermore, malicious features have different attributes, such as malicious features of abnormal data dependence, malicious features of unconventional control flow jumps, malicious features of suspicious API call sequences, malicious features of hidden communications, etc.

[0120] In this application, a sub-dataflow graph can be a "subset" or "local region" of the overall dataflow graph. It contains a portion of the nodes and edges of the overall dataflow graph and represents the local data flow relationship. For example, the nodes and edges related to the assignment and use of a variable constitute a sub-dataflow graph.

[0121] In this application, if a data flow graph is replaced by a control flow graph, a sub-control flow graph is a subset of the nodes and edges in the entire control flow graph, representing the structure of a local control flow in the program. For example, the control flow within a function body, or a branch structure, loop structure, etc. is a sub-control flow graph.

[0122] In this application, the Trojan identification model may include a graph attention neural network module, which is used to focus on sub-data flow graphs within the data flow graph that exhibit malicious characteristics. A Graph Attention Network (GAT) is a deep learning model capable of processing graph-structured data. Its core concept is to dynamically assign weights to the neighbors of different nodes through a self-attention mechanism, thereby focusing on key Trojan-related features in the data flow graph.

[0123] Specifically, the data flow graph and its node and edge features are first used as input to construct graph-structured data. Next, the graph attention layer calculates the attention scores of each node's neighbors. Nodes in subgraphs (i.e., sub-data flow graphs) with malicious features are assigned higher weights in the attention mechanism, thus exerting greater influence in the feature aggregation process. Each layer of the graph attention network then updates the representation of the current node by weightedly aggregating the features of neighboring nodes. After multiple layers are stacked, the model is able to capture more complex structures and behavioral patterns. Furthermore, the model automatically identifies and focuses on sub-data flow graphs highly correlated with malicious behavior through the attention mechanism, thereby strengthening the features of key areas. Finally, the output graph-level or node-level features are used for Trojan detection. By introducing a graph attention neural network module, it can automatically learn and focus on key substructures in the data flow graph that may carry malicious behavior characteristics, significantly improving the detection accuracy of complex or hidden Trojans and enhancing the accuracy and robustness of chip Trojan detection. Furthermore, the graph attention neural network module can adapt to a variety of graph input structures, processing both data flow graphs and control flow graphs, and even a fusion of the two, demonstrating enhanced generalization capabilities.

[0124] In the present application, the Trojan identification model may further include a first alternating fully connected layer network module, which is used to locate the position of each sub-data flow graph in the data flow graph. That is, the first alternating fully connected layer network module can accurately locate the specific position of these sub-graphs in the overall data flow graph. For example, Figure 2 The subgraph 201 shown, for example, Figure 2 The subgraph 202 shown in FIG. 202 can locate the position of the sub-data flow graph in the data flow graph through the first alternating fully connected layer network module, which can provide basic data support for subsequent malicious behavior analysis, evidence collection and program repair.

[0125] In the present application, the Trojan identification model further includes a second alternating fully connected layer network module, which is used to calculate the probability that each sub-data flow graph in the data flow graph has malicious features.

[0126] In the present application, the feature matrix input to the first alternating fully connected layer network module may include the feature matrix output by the graph attention neural network module, and the feature matrix input to the second alternating fully connected layer network module may include the feature matrix output by the graph attention neural network module and the feature matrix output by the first alternating fully connected layer network module.

[0127] In this way, the second alternating fully connected layer network module can combine the feature information output by the graph attention neural network module and the position information of each subgraph output by the first alternating fully connected layer network module to accurately analyze whether each subgraph in the data flow graph has malicious features. Specifically, the second alternating fully connected layer network module can classify each sub-data flow graph in the data flow graph and output a probability value for each subgraph having malicious features. This probability value can reflect the model's confidence that the substructure is a Trojan horse behavior. Through this probability value, it can be determined whether the corresponding subgraph is a Trojan horse with malicious features.

[0128] Furthermore, the second alternating fully connected layer network module can also be used to calculate the probability that each sub-data flow graph in the data flow graph has malicious characteristics in various attributes. For example, for a sub-data flow graph in the data flow graph, the second alternating fully connected layer network module can calculate the probability values ​​of each sub-data flow graph belonging to different attributes of malicious characteristics such as abnormal data dependency, unconventional control flow jump, suspicious API call sequence, hidden communication, etc. In this way, more refined Trojan detection results can be output.

[0129] In order to make those skilled in the art better understand the Trojan identification model, Figure 3 A specific embodiment is used for description.

[0130] See also Figure 3 , shows a model framework diagram of the Trojan identification model in an embodiment of the present application.

[0131] like Figure 3As shown, each signal node in the data flow graph is first characterized using one-hot encoding, while the adjacency matrix is ​​used to describe the connectivity between signal nodes, thereby fully expressing the graph's structural information. These node features and the adjacency matrix are then fed into a graph attention neural network module. Because the module incorporates an attention mechanism, it can adaptively learn high-dimensional representations of nodes based on the importance between them and their neighbors, further enhancing its ability to model the graph's structure and semantics. The node features output by the graph attention neural network module are then fed into two alternating fully connected layer network modules. One branch is used to locate and predict the specific location information of sub-data flow graphs, while the other branch is used to determine the probability that these sub-graphs contain malicious features, thereby enabling the identification of malicious behavior. This structured multi-task modeling approach not only accurately captures and analyzes the complex structure and potential anomalies in data flow graphs, but also simultaneously outputs sub-graph locations and the maliciousness probability of each sub-graph, thereby identifying target sub-data flow graphs with malicious features within the data flow graph, significantly improving the accuracy and practicality of detection.

[0132] In addition, the alternating fully connected layer can be used to perform further nonlinear transformations and deep information fusion on the high-dimensional node features output by the graph attention neural network module. By stacking multiple layers, more abstract features are extracted, combined with the features extracted in the previous layer, and the location information prediction and malicious feature identification tasks of the sub-data flow graph are optimized separately in the multi-task branch. This can effectively prevent the loss of important feature information during network transmission and improve the accuracy of feature information extraction. At the same time, it can also prevent overfitting and improve the model's generalization ability. Therefore, by continuously reorganizing and filtering features, the model's discriminative ability is enhanced, providing richer and more efficient feature support for malicious feature detection and improving overall detection performance.

[0133] In the present application, the identification of the target sub-data flow graph with malicious features in the data flow graph by the pre-trained Trojan identification model can be performed according to the following steps 131 to 132:

[0134] Step 131: convert each signal node in the data flow graph into a one-hot encoding, and convert the directional relationship between each signal node in the data flow graph into an adjacency matrix.

[0135] Step 132: input the one-hot encoding corresponding to each signal node and the adjacency matrix into the Trojan recognition model, so that the Trojan recognition model can identify the target sub-data flow graph with malicious characteristics in the data flow graph.

[0136] In this application, one-hot encoding is a commonly used method for vectorizing discrete features. Assume there are N different types of signal nodes (e.g., assignment, addition, conditional judgment, etc.), each type is assigned a unique number, and each signal node is represented by an N-dimensional vector, where only the corresponding type position is 1, and the rest are 0. For example, if the node type is "addition" and "addition" is in the third position, its one-hot encoding is [0, 0, 1, 0, ..., 0]. In this way, the originally symbolic and categorized node information is converted into numerical input that can be directly processed by models such as neural networks.

[0137] In the present application, the directional relationship between the various signal nodes in the data flow graph is that the edges between the signal nodes represent the data flow or control flow transfer direction between the signals (that is, who points to whom).

[0138] The edges between signal nodes in the data flow graph represent the data flow or control flow transfer between signals, that is, the pointing relationship. If signal node m points to signal node n, the structure of the graph is represented by a two-dimensional matrix A, A[m][n]=1, otherwise it is 0. The following adjacency matrix is Figure 2 The adjacency matrix corresponding to the data flow graph shown, for example, the signal node "Top.v_17" points to the signal node "Branch1".

[0139]

[0140] In this application, the adjacency matrix can be used as a standard input format for graph neural network and other models to process graph structures, that is, to convert the original graph structure information into a matrix form readable by the model, which can facilitate subsequent deep learning processing of the graph structure.

[0141] In this application, the input of the Trojan identification model includes the one-hot encoding vector of each signal node and the adjacency matrix of the pointing relationship between each signal node. During the model identification process, the feature information of each node and its neighboring nodes is aggregated through a multi-layer neural network to extract high-order structural features. The model learns the graph structure patterns that represent "malicious features", such as specific data flow patterns or abnormal control flow structures, so that these patterns can be automatically detected in the input data flow graph. The model outputs the "malicious probability" or classification label of each subgraph or node / edge, and can further output the specific index and node set of the sub-data flow graph that is judged to have malicious features. Combining the model output results and the original adjacency matrix, the specific position of the malicious subgraph in the overall data flow graph can be quickly located, providing data support for subsequent tracing analysis.

[0142] In this way, based on the technical solution of steps 131 to 132 above, the graph structure information and node attributes can be fully utilized to achieve more accurate malicious behavior identification and support automated and batch Trojan detection and positioning.

[0143] In this application, the Trojan horse recognition model can be trained through the following steps 101 to 102:

[0144] Step 101: obtain sample data flow graphs corresponding to multiple sample code modules, wherein the sub-data flow graphs with malicious features in the sample data flow graphs are marked with Trojan labels.

[0145] Step 102: Based on the sample data flow graphs corresponding to the multiple sample code modules, supervised training is performed on the pre-built Trojan identification model framework to obtain the Trojan identification model.

[0146] In this application, a sample code module refers to a batch of data samples used for training. Each sample is typically a source code snippet, a function, a module, or a complete program. The sample should include both normal code and malicious code, including Trojans, to ensure that the pre-built Trojan recognition model framework can learn the characteristics of malicious code.

[0147] In this application, the process of obtaining sample data flow graphs corresponding to multiple sample code modules can refer to the process of constructing a data flow graph matching the target code module in the above steps 121 to 124, and this application will not repeat it here.

[0148] In this application, sub-data flow diagrams in the sample data flow diagram that have malicious characteristics are annotated with a Trojan label. The sub-data flow diagrams annotated with the Trojan label are known Trojan implementations, suspicious data flow patterns, or malicious behavior segments determined by expert analysis to have a certain attribute. The annotation method can be manual annotation, rule-based automatic annotation, or combined with static / dynamic analysis tools to assist in annotation.

[0149] In this application, the pre-built Trojan identification model framework can also use model types such as graph neural networks (GNNs) and graph convolutional networks (GCNs), which can simultaneously process node features and graph structures. The input of the model includes a node feature matrix (such as one-hot encoding) and an adjacency matrix, and the output is the classification result of each subgraph or node / edge, such as whether it is a malicious subgraph. During the supervised training process, training is performed using prepared labeled data, and loss functions such as cross-entropy loss can be used for backpropagation to optimize model parameters. The training goal is to enable the model to learn to distinguish between normal subgraphs and malicious subgraphs, thereby automatically identifying Trojan features.

[0150] In terms of training details, mini-batching, data augmentation, and regularization can be used to enable the model to learn subgraph features that indicate maliciousness, thereby enabling it to identify unknown malicious subgraphs and improving the model's generalization capabilities. Furthermore, training samples can be expanded through methods such as subgraph sampling and sliding windows. Ultimately, the trained model can be fed new data flow graphs and automatically identify malicious sub-data flow graphs within them, thereby enabling Trojan detection.

[0151] It can be seen that in this application, through labeled real samples, the model can learn the complex Trojan implementation methods and structural characteristics of hidden malicious behaviors, thereby improving the accuracy and automation level of Trojan detection.

[0152] The technical solution proposed in this application significantly improves chip Trojan detection capabilities by converting target code modules into data flow graphs and analyzing them using a pre-trained Trojan recognition model that includes a graph attention neural network module. Specifically, the data flow graph comprehensively reflects the data operation logic and control flow of the target code module during operation, providing a deeper understanding of potential abnormal behavior within the chip. By analyzing these graph structures, the Trojan recognition model can automatically focus on and identify sub-data flow graphs with malicious characteristics, effectively detecting various types and forms of chip Trojans, including stealthy and complex ones. This solution eliminates the need for trusted benchmarks and Trojan libraries as references for Trojan detection, not only improving the accuracy and robustness of chip Trojan detection but also significantly increasing the automation and efficiency of chip Trojan detection, significantly reducing the workload of manual detection and the rate of false positives and false negatives. Furthermore, as chip design becomes increasingly complex, this solution can continuously adapt to and generalize the detection needs of new chip Trojans, thereby enhancing chip security. Therefore, this technical solution can effectively improve chip Trojan detection capabilities.

[0153] The technical solution proposed in this application, which detects chip Trojans based on a data flow graph, can be widely applied in the field of integrated circuit design, especially in the following scenarios:

[0154] 1. Chip design stage: During the chip design process, the designed code is checked for Trojans to promptly discover and eliminate potential security risks and ensure the security and reliability of the chip.

[0155] 2. Third-party IP core verification: For IP cores provided by third parties, use this method to detect Trojans and verify their security to avoid introducing potential risks into the chip.

[0156] 3. Quality control during chip production: During the chip production process, random inspections are performed on the chips, and this method is used to detect whether there are Trojans in the chips to ensure the quality and security of the chips.

[0157] 4. Chip security assessment: Conduct security assessments on chips already in use, using this method to detect whether there are Trojans in the chip, promptly discover and address security issues, and ensure the normal operation and information security of the chip.

[0158] The following describes an embodiment of the device of the present application, which can be used to execute the chip Trojan detection method in the above embodiment of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the chip Trojan detection method in the above embodiment of the present application.

[0159] See also Figure 4 , shows a block diagram of a chip Trojan detection device in an embodiment of the present application.

[0160] like Figure 4 As shown, the chip Trojan detection device 400 according to an embodiment of the present application includes: an acquisition unit 401, a construction unit 402 and an identification unit 403.

[0161] Among them, the acquisition unit 401 is used to obtain the target code module, and the target code module is used to describe at least one corresponding operation function in the chip to be detected, and the operation function is implemented by multiple transistors integrated according to the set logic; the construction unit 402 is used to construct a data flow graph matching the target code module, and the data flow graph is used to characterize the data operation logic of the target code module during operation; the identification unit 403 is used to identify the target sub-data flow graph with malicious characteristics in the data flow graph through a pre-trained Trojan recognition model, and the target sub-data flow graph reflects the presence of a chip Trojan in the chip to be detected. The Trojan recognition model includes a graph attention neural network module, and the graph attention neural network module is used to focus on the sub-data flow graph with malicious characteristics in the data flow graph.

[0162] In some embodiments of the present application, based on the aforementioned scheme, the acquisition unit 401 is configured to: obtain a hardware description program corresponding to the chip to be tested; determine at least one code module in the hardware description program, wherein each code module is used to describe the corresponding operation function in the chip to be tested; and flatten the at least one code module to integrate the at least one code module into a target code module.

[0163] In some embodiments of the present application, based on the aforementioned scheme, the construction unit 402 is configured to: parse the target code module to generate an abstract syntax tree of the target code module, the abstract syntax tree including multiple signals; extract the dependency relationship between each adjacent signal from the abstract syntax tree, and construct a dependency tree corresponding to each adjacent signal based on the dependency relationship, the dependency tree including two signal nodes and a pointing relationship between the two signal nodes; merge the various dependency trees to obtain an initial data flow graph that matches the target code module; remove redundant signal nodes in the initial data flow graph to obtain a data flow graph that matches the target code module.

[0164] In some embodiments of the present application, based on the aforementioned scheme, the identification unit 403 is configured to: convert each signal node in the data flow graph into a one-hot encoding, and convert the directional relationship between each signal node in the data flow graph into an adjacency matrix; input the one-hot encoding corresponding to each signal node and the adjacency matrix into the Trojan recognition model, so that the Trojan recognition model can identify the target sub-data flow graph with malicious characteristics in the data flow graph.

[0165] In some embodiments of the present application, based on the aforementioned solution, the Trojan identification model further includes a first alternating fully connected layer network module, which is used to locate the position of each sub-data flow graph in the data flow graph.

[0166] In some embodiments of the present application, based on the aforementioned scheme, the Trojan identification model also includes a second alternating fully connected layer network module, which is used to calculate the probability that each sub-data flow graph in the data flow graph has malicious features.

[0167] In some embodiments of the present application, based on the aforementioned solution, the second alternating fully connected layer network module is used to calculate the probability that each sub-data flow graph in the data flow graph has malicious features in each attribute.

[0168] In some embodiments of the present application, based on the aforementioned scheme, the feature matrix input to the first alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module, and the feature matrix input to the second alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module and the feature matrix output by the first alternating fully connected layer network module.

[0169] In some embodiments of the present application, based on the aforementioned scheme, the device also includes: a training unit, used to obtain sample data flow graphs corresponding to multiple sample code modules, and the sub-data flow graphs with malicious characteristics in the sample data flow graphs are marked with Trojan labels; based on the sample data flow graphs corresponding to the multiple sample code modules, a pre-constructed Trojan identification model framework is supervised trained to obtain the Trojan identification model.

[0170] In some embodiments of the present application, based on the aforementioned solution, the data flow graph is replaced with a control flow graph.

[0171] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so that a computer device with the processor executes to implement the operations performed by the chip Trojan detection method as described above.

[0172] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, which stores at least one computer program instruction. The at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the chip Trojan detection method described above.

[0173] Based on the same inventive concept, the present application also provides an electronic device, referring to Figure 5 , shows a structural schematic diagram of an electronic device in an embodiment of the present application, wherein the electronic device includes one or more memories 504, one or more processors 502, and at least one computer program (computer program instruction) stored in the memory 504 and executable on the processor 502. When the processor 502 executes the computer program, the chip Trojan detection method as described above is implemented.

[0174] Among them, Figure 5In the embodiment of the present invention, a bus architecture (represented by bus 500) is shown. Bus 500 may include any number of interconnected buses and bridges. Bus 500 links various circuits, including one or more processors represented by processor 502 and memory represented by memory 504. Bus 500 may also link various other circuits, such as peripherals, voltage regulators, and power management circuits. These are well known in the art and are therefore not described further herein. Bus interface 505 provides an interface between bus 500 and receiver 501 and transmitter 503. Receiver 501 and transmitter 503 may be the same component, namely a transceiver, which provides a means for communicating with various other devices over a transmission medium. Processor 502 is responsible for managing bus 500 and general processing, while memory 504 may be used to store data used by processor 502 when performing operations.

[0175] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and implementations are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Furthermore, the functional units may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0176] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0177] The units described as separate components may or may not be physically separate, and the components of the control device may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0178] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, etc. Various media that can store computer program instructions.

[0179] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of the claims of the present application.

Claims

1. A chip Trojan detection method, characterized in that: The method comprises: Obtaining a target code module, the target code module being used to describe at least one corresponding operation function in the chip to be detected, the operation function being implemented by a plurality of transistors integrated according to a set logic; Constructing a data flow graph that matches the target code module, wherein the data flow graph is used to represent the data operation logic of the target code module during operation; Identify a target sub-data flow graph with malicious features in the data flow graph through a pre-trained Trojan identification model, wherein the target sub-data flow graph reflects the presence of a chip Trojan in the chip to be detected, and the Trojan identification model includes a graph attention neural network module, wherein the graph attention neural network module is used to focus on the sub-data flow graph with malicious features in the data flow graph; The Trojan identification model further includes a first alternating fully connected layer network module and a second alternating fully connected layer network module, wherein the first alternating fully connected layer network module is used to locate the position of each sub-data flow graph in the data flow graph; the second alternating fully connected layer network module is used to calculate the probability that each sub-data flow graph in the data flow graph has malicious features on each attribute; The feature matrix input to the first alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module, and the feature matrix input to the second alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module and the feature matrix output by the first alternating fully connected layer network module.

2. The method according to claim 1, characterized in that The obtaining of the target code module comprises: Obtain the hardware description program corresponding to the chip to be tested; Determining at least one code module in the hardware description program, wherein each code module is used to describe a corresponding operation function in the chip to be tested; Flattening is performed on the at least one code module to integrate the at least one code module into a target code module.

3. The method according to claim 1, characterized in that The constructing of a data flow graph matching the target code module includes: Parsing the target code module to generate an abstract syntax tree of the target code module, wherein the abstract syntax tree includes a plurality of signals; Extracting a dependency relationship between each adjacent signal from the abstract syntax tree, and constructing a dependency tree corresponding to each adjacent signal based on the dependency relationship, wherein the dependency tree includes two signal nodes and a pointing relationship between the two signal nodes; Merging the dependency trees to obtain an initial data flow graph that matches the target code module; Redundant signal nodes in the initial data flow graph are removed to obtain a data flow graph that matches the target code module.

4. The method according to claim 1, wherein The identifying a target sub-data flow graph having malicious features in the data flow graph by using a pre-trained Trojan identification model includes: Convert each signal node in the data flow graph into a one-hot encoding, and convert the directional relationship between each signal node in the data flow graph into an adjacency matrix; The one-hot encoding corresponding to each signal node and the adjacency matrix are input into the Trojan recognition model so that the Trojan recognition model can identify the target sub-data flow graph with malicious features in the data flow graph.

5. The method according to any one of claims 1 to 4, characterized in that The Trojan identification model is trained through the following steps: Obtaining sample data flow graphs corresponding to a plurality of sample code modules, wherein sub-data flow graphs having malicious characteristics in the sample data flow graphs are marked with a Trojan label; Based on the sample data flow graphs corresponding to the multiple sample code modules, supervised training is performed on the pre-built Trojan identification model framework to obtain the Trojan identification model.

6. The method according to any one of claims 1 to 4, characterized in that The data flow graph is replaced by a control flow graph.

7. A chip Trojan detection device, characterized in that: The device comprises: an acquisition unit, configured to acquire a target code module, wherein the target code module is configured to describe at least one corresponding operation function in the chip to be detected, wherein the operation function is implemented by a plurality of transistors integrated according to a set logic; A construction unit, configured to construct a data flow graph matching the target code module, wherein the data flow graph is used to represent the data operation logic of the target code module during operation; an identification unit, configured to identify a target sub-data flow graph having malicious features in the data flow graph by using a pre-trained Trojan identification model, wherein the target sub-data flow graph reflects the presence of a chip Trojan in the chip to be detected, wherein the Trojan identification model includes a graph attention neural network module, and the graph attention neural network module is configured to focus on the sub-data flow graph having malicious features in the data flow graph; The Trojan identification model further includes a first alternating fully connected layer network module and a second alternating fully connected layer network module, wherein the first alternating fully connected layer network module is used to locate the position of each sub-data flow graph in the data flow graph; the second alternating fully connected layer network module is used to calculate the probability that each sub-data flow graph in the data flow graph has malicious features on each attribute; The feature matrix input to the first alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module, and the feature matrix input to the second alternating fully connected layer network module includes the feature matrix output by the graph attention neural network module and the feature matrix output by the first alternating fully connected layer network module.

8. A computer program product, characterized in that The computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor, so as to enable a computer device having the processor to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that At least one program code is stored in the computer-readable storage medium, and the at least one program code is loaded and executed by the processor to implement the operations performed by the method according to any one of claims 1 to 6.

10. An electronic device, characterized in that: The electronic device includes one or more processors and one or more memories, wherein at least one program code is stored in the one or more memories, and the at least one program code is loaded and executed by the one or more processors to implement the method according to any one of claims 1 to 6.

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