A dynamic recognition system and method based on light-controlled neural synaptic array

Abstract

This invention proposes a dynamic identification system and method based on a light-controlled neural synapse array, relating to the field of photoelectric pulse technology. The system includes: a lens imaging module configured to acquire optical signals and transmit them to the light-controlled neural synapse array to adjust the resistance value of the array; a displacement buffer module configured to receive serial input signals from a microcontroller unit, convert them into parallel output signals, and transmit the parallel output signals to the array after the register is full; the light-controlled neural synapse array, comprising multiple light-controlled synapses, where the corresponding target light-controlled synapse operates when the parallel output signal is low, and is connected to an analog-to-digital converter; the analog-to-digital converter configured to acquire the voltage value of the target light-controlled synapse and determine its resistance value based on the voltage value; and a dynamic imaging module configured to convert the resistance value into a grayscale image.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic pulse technology, and in particular to a dynamic recognition system and method based on a light-controlled neural synapse array. Background Technology

[0002] With the advent of the Internet of Things (IoT) era, motion detection and recognition (MDR) has become a core requirement for various intelligent scenarios such as smart homes, artificial vision, security monitoring, autonomous vehicles, and military defense. Traditional motion capture methods typically require the installation of 3D sensors to acquire images frame by frame, followed by computer processing of massive amounts of image data. This not only relies on a large number of high-quality single-frame images and complex data conversion, transmission, storage, and processing operations between different modules, but also consumes high computational energy, hindering miniaturization and integration. Biological neural synapses achieve synaptic memory by altering their function or structure through excitation or inhibition under the influence of neural activity or experience. Opto-controlled neural synapses are a type of biological synaptic behavior simulation device. Photoelectric synapses possess a unique function: when the light stimulus is removed, their response does not immediately return to zero, but rather stores a portion of the signal in the device, thus achieving cumulative signal storage. This mechanism can be used to simulate the plasticity of biological synapses to achieve the plasticity of photoelectric synapses. However, current research on the simulation of biological synaptic behavior mostly focuses on the basic simulation of the plasticity of synapses in a single device, which is insufficient to meet the needs of motion detection and recognition. Summary of the Invention

[0003] In view of this, the present invention proposes a dynamic recognition system and method based on a light-controlled neural synaptic array.

[0004] The technical solution of this invention is implemented as follows: The first aspect of this invention provides a dynamic recognition system based on a light-controlled neural synapse array, comprising: a lens imaging module, a displacement buffer module, a light-controlled neural synapse array, an analog-to-digital converter, and a dynamic imaging module; wherein,

[0005] The lens imaging module is configured to acquire target temporal optical signals and transmit the target temporal optical signals to a light-controlled neural synapse array to adjust the resistance value of the light-controlled neural synapse array.

[0006] The displacement buffer module is configured to receive the serial input signal of the microcontroller unit, convert the serial input signal into a parallel output signal, and transmit the parallel output signal to the optically controlled neural synapse array after the register is full.

[0007] The light-controlled synapse array includes multiple light-controlled synapses. When the parallel output signal is low, the corresponding target light-controlled synapse operates and connects to the analog-to-digital converter.

[0008] The analog-to-digital converter is configured to acquire the timing voltage value of the target optically controlled neural synapse and determine the timing resistance value of the target optically controlled neural synapse based on the timing voltage value.

[0009] The dynamic imaging module is configured to convert the timing resistance value into a grayscale image.

[0010] Based on the above technical solutions, preferably, the light-controlled neural synapse array includes at least: a first light-controlled neural synapse and a second light-controlled neural synapse;

[0011] When the parallel output signal connected to the first photosensitive synapse is at a low level, the second photosensitive synapse is connected to a high level, the first photosensitive synapse is activated, and the second photosensitive synapse is deactivated.

[0012] Based on the above technical solutions, preferably, the resistance value of the target light-controlled neural synapse satisfies:

[0013]

[0014] Among them, V REF V represents the voltage signal at the emitter of the PNP transistor in the target light-controlled neural synapse. testi R is the timing voltage value acquired by the analog-to-digital converter. c To determine the resistance value of the resistor, R i R is the resistance value of the i-th light-controlled neural synapse. BJT This is the on-resistance.

[0015] Based on the above technical solutions, preferably, a filtering submodule is also included; the filtering submodule is configured to perform Kalman filtering on the voltage values ​​acquired by the analog-to-digital converter.

[0016] More preferably, a second aspect of the present invention provides a dynamic recognition method based on a light-controlled neural synapse array, applied to the dynamic recognition system based on a light-controlled neural synapse array described in the first aspect, comprising:

[0017] Acquire the target temporal optical signal and transmit the target temporal optical signal to the light-controlled neural synapse array;

[0018] A parallel voltage signal is applied to the optically controlled neural synapse array, and the timing resistance values ​​of multiple optically controlled neural synapses in the optically controlled neural synapse array under the parallel voltage signal are obtained.

[0019] The time-series resistance values ​​are converted into grayscale images, and the dynamics of the observed target are determined based on the grayscale values ​​of the grayscale images.

[0020] Based on the above technical solutions, preferably, the light-controlled synapse array includes a first light-controlled synapse and a second light-controlled synapse; the step of applying a parallel voltage signal to the light-controlled synapse array and obtaining the timing resistance values ​​of multiple light-controlled synapses in the light-controlled synapse array under the parallel voltage signal includes:

[0021] A low-level voltage signal is applied to the first photosensitive synapse, and a high-level voltage signal is applied to the second photosensitive synapse to obtain the timing resistance value of the first photosensitive synapse.

[0022] Based on the above technical solution, preferably, the light-controlled neural synapse includes a PNP transistor; the step of applying a parallel voltage signal to the light-controlled neural synapse array and obtaining the timing resistance values ​​of multiple light-controlled neural synapses in the light-controlled neural synapse array under the parallel voltage signal includes:

[0023] With a high-level voltage signal applied to the emitter of the PNP transistor, a low-level voltage signal is applied to the base of the PNP transistor to obtain the timing resistance value of the target photosensitive neural synapse.

[0024] Based on the above technical solutions, preferably, the step of converting the time-series resistance value into a grayscale image and determining the dynamics of the observed target based on the grayscale value of the grayscale image includes:

[0025] The temporal resistance values ​​of all light-controlled synapses in the light-controlled synapse array are converted into corresponding grayscale images to obtain image fusion features; the image fusion features include grayscale values ​​and image trajectories.

[0026] The moving speed and direction of the observed target are determined based on the grayscale values ​​and image trajectory.

[0027] More preferably, a third aspect of the present invention provides an electronic device, including a processor and a memory; the memory has a computer program stored thereon, wherein the computer program, when executed by the processor, implements the dynamic recognition method based on a light-controlled neural synaptic array as described in the second aspect.

[0028] More preferably, in a fourth aspect of the present invention, a computer storage medium is provided on which a computer program is stored, wherein the computer program, when executed by a processor, implements the dynamic recognition method based on a light-controlled neural synaptic array as described in the second aspect.

[0029] The dynamic recognition system based on a light-controlled neural synaptic array of the present invention has the following advantages over the prior art:

[0030] 1. By integrating multiple light-controlled neural synapses and utilizing their sensitivity to light signals, the change in resistance value is visualized as a change in image depth value. This allows for the analysis of the visual attenuation process of the monitored target, thereby reconstructing the object's motion trajectory and achieving a unique "visual persistence" effect. This presents a "dynamic" effect on a single frame image, thus enabling motion capture and improving the accuracy and efficiency of dynamic monitoring of the observed target.

[0031] 2. By utilizing the depth value information on a single frame image, the spatiotemporal information of the monitored target can be deduced, and dynamic trajectory recognition can be completed. MDR can be achieved without the need for the complex algorithms of traditional MDR to analyze and learn multiple frames of images, which greatly simplifies the calculation process and improves monitoring efficiency.

[0032] 3. The dual-terminal optically controlled neural synapse replaces a large number of traditional MDR hardware system modules, making the entire system highly integrated. It is controlled by the MCU and can process and transmit information simultaneously without complex connections. This is conducive to the integration and miniaturization of the device, and reduces the requirements for memory capacity, effectively reducing hardware costs. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A schematic diagram of the structure of a dynamic recognition system based on a light-controlled neural synapse array provided in an embodiment of the present invention;

[0035] Figure 2 A schematic diagram illustrating the signal transmission sequence provided in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the structure of the light-controlled neural synapse array provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the structure of the light-controlled neural synapse device provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of a monitoring scenario provided in an embodiment of the present invention;

[0039] Figure 6This is a schematic diagram of the path grayscale values ​​corresponding to different time positions provided in an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of the structure of the test circuit board provided in the embodiment of the present invention;

[0041] Figure 8 A flowchart illustrating a dynamic recognition method based on a light-controlled neural synaptic array, provided in an embodiment of the present invention;

[0042] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0043] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0044] In some embodiments, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a dynamic recognition system based on a light-controlled neural synapse array, provided by an embodiment of the present invention. The dynamic recognition system based on a light-controlled neural synapse array provided by the present invention includes: a lens imaging module 110, a displacement buffer module 120, a light-controlled neural synapse array 130, an analog-to-digital converter 140, and a dynamic imaging module 150; wherein...

[0045] The lens imaging module 110 is configured to acquire the target time-series optical signal and transmit the target time-series optical signal to the light-controlled neural synapse array to adjust the resistance value of the light-controlled neural synapse array.

[0046] The displacement buffer module 120 is configured to receive the serial input signal from the microcontroller unit 160, convert the serial input signal into a parallel output signal, and transmit the parallel output signal to the light-controlled neural synapse array after the register is full.

[0047] The optically controlled neural synapse array 130 includes multiple optically controlled neural synapses. When the parallel output signal is at a low level, the corresponding target optically controlled neural synapse operates and is connected to the analog-to-digital converter.

[0048] The analog-to-digital converter 140 is configured to acquire the timing voltage value of the target light-controlled neural synapse and determine the timing resistance value of the target light-controlled neural synapse based on the timing voltage value.

[0049] The dynamic imaging module 150 is configured to convert time-series resistance values ​​into grayscale images.

[0050] In this embodiment, the lens imaging module 110 mainly includes a lens, a lens barrel, an aperture, and a focusing system. It captures external light and focuses it onto the light-controlled neural synapse array. By scanning each light-controlled neural synapse in the array, the resistance value of each synapse is obtained for subsequent data processing and imaging. To save hardware resources and computing power, a single analog-to-digital converter 140 can be used to perform analog-to-digital conversion on each light-controlled neural synapse. The ability to switch between conversion objects is achieved by the shift register module 120, which mainly consists of a shift register and a storage register. It performs its function by storing and transmitting input signals.

[0051] In an optional embodiment, the microcontroller unit 160 uses an STM32F103C8T6 chip, based on an ARM Cortex-M3 core, with a main frequency of 72MHz, 64KB of built-in Flash memory and 20KB of SRAM, and supports multiple peripheral interfaces, including three SPI interfaces, two I2C interfaces, three USART interfaces, and multiple GPIO ports. The microcontroller unit 160 connects to the analog-to-digital converter module 140 via the SPI interface to receive digital signals in real time. The shift register module 120 can be composed of an 8-bit shift register chain, a clock synchronization circuit, and a parallel output latch, used to receive serial input signals from the microcontroller unit 160 and convert them into parallel output signals. The module supports a maximum clock frequency of 50MHz, operates at 3.3V, and is compatible with the GPIO levels of the STM32F103C8T6. When the 8-bit data fills the register, the microcontroller unit 160 notifies the module via an interrupt signal (INT), and the module then outputs signals in parallel to the light-controlled neural synapse array via the output latch. See here. Figure 2 , Figure 2 This is a schematic diagram illustrating the signal transmission sequence provided in an embodiment of the present invention. The analog-to-digital converter (ADC) module 140 converts the input voltage signal into a digital signal for subsequent digital signal processing. The ADC module includes a sampling circuit, a quantization circuit, and an encoding circuit. The sampling circuit samples the analog signal, the quantization circuit converts the sampled signal into discrete levels, and the encoding circuit converts the quantized signal into a binary digital signal. The ADC module can have a resolution of 16 bits, a sampling rate of 1 MSPS (millions of samples per second), a signal-to-noise ratio of 90 dB, and a conversion accuracy of ±0.01%.

[0052] In some embodiments, the light-controlled synapse array includes at least: a first light-controlled synapse and a second light-controlled synapse;

[0053] When the parallel output signal connected to the first photosensitive synapse is low, the second photosensitive synapse is connected to a high level, the first photosensitive synapse is activated, and the second photosensitive synapse is deactivated.

[0054] It should be noted that the first and second light-controlled synapses are any two light-controlled synapses on the light-controlled synapse array. In addition to the first and second light-controlled synapses, the light-controlled synapse array may also include other light-controlled synapses, and there is no limit to their specific number here.

[0055] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the optically controlled neural synapse array provided in an embodiment of the present invention. Taking a 5×5 array as an example, the optically controlled neural synapse array consists of 25 small modules, each containing a PNP transistor and an optically controlled neural synapse device. Five small modules extracted from the 5×5 array are described below. The shift register module outputs the data Vin stored in the register to the optically controlled neural synapse array in parallel. For the PNP transistor, when the emitter is connected to a high level, a low level is input to the base, and the collector is equivalent to being connected to a high level; when a high level is input to the base, the collector is equivalent to being disconnected. Here, in the initial state, all registers output high levels, turning off all transistors. Then, a low level is output to the transistor of the first photosensitive synapse, making one end of this synapse high, while the other transistors remain off. At this time, the transistor of the first photosensitive synapse conducts, with an RBJT as its on-resistance. The synapse and the reference resistor form a closed loop. The voltage test point connected to the analog-to-digital converter samples the voltage signal Vtest1 at this point and transmits it back to the converter, acquiring the voltage value of the first photosensitive synapse. Since the other transistors are off at this time and do not participate in voltage division, the resistance value R1 of the first photosensitive synapse can be calculated. Next, a high level is input to the transistor of the first photosensitive synapse, and a low level is input to the transistor of the second photosensitive synapse, while the other transistors remain off, yielding Vtest2 and R2. A low level is input to the transistor of the third photosensitive synapse… and so on. By expanding the number of displacement buffer modules and arrays, arrays of 10×10, 50×50, and even 256×256 can be implemented. The above process will continue to cycle, constantly refreshing the resistance value of each synapse. It should be noted that the increase in the resistance value of each light-controlled neural synapse follows a basically linear relationship with the change in light intensity, and the rate of resistance decay of each light-controlled neural synapse is basically the same. When an object passes over the light-controlled neural synapse, the change in light intensity can be simplified into a rectangular pulse model.

[0056] In some embodiments, the resistance value of the target light-controlled neural synapse satisfies:

[0057]

[0058] Among them, V REF V represents the voltage signal at the emitter of the PNP transistor in the target light-controlled neural synapse. testi R is the timing voltage value acquired by the analog-to-digital converter. c To determine the resistance value of the resistor, R i R is the resistance value of the i-th light-controlled neural synapse. BJT This is the on-resistance.

[0059] In one example, see Figure 4 , Figure 4 This is a schematic diagram of the structure of the optically controlled neural synapse device provided in an embodiment of the present invention. The optically controlled neural synapse device is a dual-terminal optically controlled neural synapse composed of conductive glass, zinc oxide, perovskite, and gold. Zinc oxide serves as the common base for all synapses, meaning that one end of all optically controlled neural synapses in the circuit is connected together, and the other end is connected to the collector of a transistor. The base of the transistor is connected to the parallel output signal port of the shift register module, and the emitter is connected to VREF. This voltage is used as the reference voltage for the analog-to-digital converter (ADC), typically 3.3V. The common-base zinc oxide is connected to a reference resistor Rc, and the midpoint between them is connected to the analog signal input terminal of the ADC, serving as the voltage test point for the ADC module. After the ADC completes sampling, a DMA request is automatically triggered, directly storing the resistance data into a designated memory area. All sampled values ​​from the ADC will be continuously updated according to the pulse timing sequence, due to the tight timing and the influence of other external factors.

[0060] For the dynamic imaging module 150, after obtaining all resistance sample values, the resistance sample values ​​are converted into grayscale images, and the grayscale images are displayed on an OLED display. For an example of a vehicle dynamic detection experiment, please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of a monitoring scenario provided in an embodiment of the present invention, illustrating the vehicle's speed and direction. The vehicle travels from the upper left to the lower right. As the sampled values ​​and grayscale image are updated, the grayscale of the areas the vehicle has passed through continuously deepens over time, but it does not immediately return to its original grayscale value. Instead, it is gradually "forgotten" over time. Because the time it takes for the vehicle to pass a certain point varies, the degree to which the travel path is "forgotten" differs, which is reflected numerically as different ADC sampled values. Additionally, please refer to... Figure 6 , Figure 6This diagram illustrates the path grayscale values ​​corresponding to different time positions in an embodiment of the present invention; the path grayscale values ​​are inconsistent across different time positions. It is understood that for the same image location, the grayscale value decreases over time; similarly, for the same image at any given moment, the grayscale value decreases as the location becomes farther away. Based on this, the speed of the vehicle can be determined by the resistance attenuation values ​​of different light-controlled neural synapses, and the direction of the vehicle's movement can also be easily determined. Dynamic recognition can be performed within the same frame image, reconstructing the motion trajectory of the monitored target.

[0061] In one optional embodiment, the specific principle of determining the motion trajectory of the monitored target using the resistance attenuation of light-controlled neural synapses is as follows:

[0062] The change in resistance of a light-controlled neural synapse over time can be expressed as:

[0063] R i (t)=R i0 +αI i (t)-βt;

[0064] Among them, R i (t) represents the resistance of the i-th light-controlled neural synapse at time t, R i0 Let I be the initial resistance of the i-th light-controlled neural synapse, and α be the coefficient of resistance variation with light intensity. i (t) represents the light intensity received by the i-th photosensitive synapse at time t; β represents the resistance decay rate.

[0065] Correcting the actual decay rate using an unlit reference light-controlled neural synapse:

[0066]

[0067] R ref (t1), R ref (t2) represents the resistance of the reference pixel at times t1 and t2, respectively.

[0068] By monitoring a sudden increase in resistance when the target covers the light-controlled neural synapse, the displacement buffer module is triggered to transmit a parallel output signal to the light-controlled neural synapse array:

[0069] R i (t)=R i0 +αI max ·H(tt i )-β(tt i );

[0070] Where H(t) is the step function (1 when t≥0, 0 otherwise); t i To monitor the time it takes for the target to reach the i-th light-controlled neural synapse.

[0071] The trigger threshold is defined as 50% of the photoresistivity threshold.

[0072] R th =R i0 +0.5αI max ;

[0073] Arrange the trigger times of the 5×5 array according to their spatial positions to construct a time matrix:

[0074]

[0075] t x，y The triggering time of a pixel with coordinates (x, y) is represented.

[0076] Calculate the gradient of the time matrix using the Sobel kernel:

[0077] Horizontal gradient kernel:

[0078] Vertical gradient kernel:

[0079] Gradient components: * indicates a convolution operation.

[0080]

[0081] By dynamically warping and aligning the time series of multiple light-controlled neural synapses, path time differences can be extracted.

[0082] Δt path =DTW(t) path DTW stands for Dynamic Time Warping, an algorithm used to align non-uniform time series.

[0083] In some embodiments, the dynamic recognition system based on the light-controlled neural synapse array further includes a filtering submodule; the filtering submodule is configured to perform Kalman filtering on the voltage values ​​acquired by the analog-to-digital converter.

[0084] Due to the tight timing and other external factors, the measured ADC voltage samples are often inaccurate, further affecting the accuracy of the resistance values. Therefore, Kalman filtering is required during the ADC sampling process to improve the accuracy of the voltage samples. See the example below. Figure 7 , Figure 7 This is a schematic diagram of the experimental circuit board provided for the embodiments of the present invention; by verifying the circuit structure and circuit principle on the PCB, all data were successfully obtained.

[0085] In some embodiments, a second aspect of the present invention provides a dynamic recognition method based on a light-controlled neural synapse array, applied to the dynamic recognition system based on a light-controlled neural synapse array described in the first aspect, comprising:

[0086] S810 acquires the target time-series optical signal and transmits the target time-series optical signal to the light-controlled neural synapse array;

[0087] S820 applies a parallel voltage signal to the optically controlled neural synapse array and obtains the timing resistance values ​​of multiple optically controlled neural synapses in the optically controlled neural synapse array under the parallel voltage signal.

[0088] S830 converts the timing resistance values ​​into a grayscale image, and determines the dynamics of the observed target based on the grayscale values ​​of the grayscale image.

[0089] In some embodiments, the light-controlled synapse array includes a first light-controlled synapse and a second light-controlled synapse; applying a parallel voltage signal to the light-controlled synapse array and obtaining the timing resistance values ​​of multiple light-controlled synapses in the light-controlled synapse array under the parallel voltage signal includes:

[0090] A low-level voltage signal is applied to the first photosensitive synapse, and a high-level voltage signal is applied to the second photosensitive synapse to obtain the timing resistance value of the first photosensitive synapse.

[0091] In some embodiments, the light-controlled synapse includes a PNP transistor; applying a parallel voltage signal to the light-controlled synapse array and obtaining the timing resistance values ​​of multiple light-controlled synapses in the light-controlled synapse array under the parallel voltage signal includes:

[0092] With a high-level voltage signal applied to the emitter of the PNP transistor, a low-level voltage signal is applied to the base of the PNP transistor to obtain the timing resistance value of the target photocontrolled neural synapse.

[0093] In some embodiments, converting time-series resistance values ​​into grayscale images and determining the dynamics of the observed target based on the grayscale values ​​of the grayscale images includes:

[0094] The temporal resistance values ​​of all optically controlled synapses in the optically controlled synapse array are converted into corresponding grayscale images to obtain image fusion features; the image fusion features include grayscale values ​​and image trajectories.

[0095] The speed and direction of movement of the observed target are determined based on grayscale values ​​and image trajectory.

[0096] It should be noted that the dynamic recognition method based on light-controlled neural synaptic array provided in this application embodiment and the dynamic recognition system based on light-controlled neural synaptic array provided in this application embodiment are based on the same application concept. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned dynamic recognition system based on light-controlled neural synaptic array, and the repeated parts will not be described again.

[0097] In some embodiments, please refer to Figure 9 , Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 900 provided in this application includes a processor 910 and a memory 920; the memory 920 stores a computer program, wherein the computer program, when executed by the processor, implements the aforementioned dynamic recognition system based on a light-controlled neural synaptic array.

[0098] Specifically, processor 910 may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. Processor 910 may also include onboard memory for caching purposes. Processor 910 may be a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of this application.

[0099] The memory 920 can be any medium capable of containing, storing, transmitting, propagating, or transmitting instructions. For example, the memory 920 can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, apparatus, or propagation medium. Specific examples of the memory 920 include: magnetic storage devices such as magnetic tape or hard disk drives (HDDs); optical storage devices such as optical discs (CD-ROMs); and also random access memory (RAM) or flash memory; and / or wired / wireless communication links.

[0100] This application also provides a computer-readable medium storing a computer program thereon, which, when executed by a processor, implements the aforementioned dynamic recognition system based on a light-controlled neural synaptic array. This computer-readable medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into that device / apparatus / system. The aforementioned computer-readable medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0101] According to embodiments of this application, a computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wired, optical fiber, radio frequency signals, etc., or any suitable combination thereof.

[0102] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application. Therefore, the scope of this application should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A dynamic recognition system based on a light-controlled neural synaptic array, characterized in that, include: The system comprises a lens imaging module, a displacement buffer module, a light-controlled neural synapse array, an analog-to-digital converter, and a dynamic imaging module; among which, The lens imaging module is configured to acquire target temporal optical signals and transmit the target temporal optical signals to a light-controlled neural synapse array to adjust the resistance value of the light-controlled neural synapse array. The displacement buffer module is configured to receive the serial input signal of the microcontroller unit, convert the serial input signal into a parallel output signal, and transmit the parallel output signal to the optically controlled neural synapse array after the register is full. The light-controlled synapse array includes multiple light-controlled synapses. When the parallel output signal is low, the corresponding target light-controlled synapse operates and connects to the analog-to-digital converter. The analog-to-digital converter is configured to acquire the timing voltage value of the target optically controlled synapse and determine the timing resistance value of the target optically controlled synapse based on the timing voltage value; the timing resistance value of the target optically controlled synapse satisfies: ； in, The voltage signal at the emitter of the PNP transistor in the target light-controlled neural synapse. The timing voltage values ​​acquired by the analog-to-digital converter. To determine the resistance value of the resistor, Let be the resistance value of the i-th light-controlled neural synapse. For on-resistance; The dynamic imaging module is configured to convert the timing resistance value into a grayscale image. The dynamic recognition system is further configured to: obtain image fusion features from the grayscale image, the image fusion features including grayscale values ​​and image trajectories, and determine the moving speed and moving direction of the observed target based on the grayscale values ​​and image trajectories.

2. The dynamic recognition system based on a light-controlled neural synaptic array as described in claim 1, characterized in that, The light-controlled neural synapse array includes at least: a first light-controlled neural synapse and a second light-controlled neural synapse; When the parallel output signal connected to the first photosensitive synapse is at a low level, the second photosensitive synapse is connected to a high level, the first photosensitive synapse is activated, and the second photosensitive synapse is deactivated.

3. The dynamic recognition system based on a light-controlled neural synaptic array as described in claim 1, characterized in that, It also includes a filtering submodule; the filtering submodule is configured to perform Kalman filtering on the voltage values ​​acquired by the analog-to-digital converter.

4. A dynamic recognition method based on a light-controlled neural synaptic array, applied to the dynamic recognition system based on a light-controlled neural synaptic array as described in any one of claims 1-3, characterized in that, include: Acquire the target temporal optical signal and transmit the target temporal optical signal to the light-controlled neural synapse array; A parallel voltage signal is applied to the optically controlled neural synapse array, and the timing resistance values ​​of multiple optically controlled neural synapses in the optically controlled neural synapse array under the parallel voltage signal are obtained. The time-series resistance values ​​are converted into grayscale images, and image fusion features are obtained from the grayscale images. The image fusion features include grayscale values ​​and image trajectories. The moving speed and direction of the observed target are determined based on the grayscale values ​​and image trajectories.

5. The dynamic recognition method based on light-controlled neural synaptic array as described in claim 4, characterized in that, The light-controlled synapse array includes a first light-controlled synapse and a second light-controlled synapse; the step of applying a parallel voltage signal to the light-controlled synapse array and obtaining the timing resistance values ​​of multiple light-controlled synapses in the light-controlled synapse array under the parallel voltage signal includes: A low-level voltage signal is applied to the first photosensitive synapse, and a high-level voltage signal is applied to the second photosensitive synapse to obtain the timing resistance value of the first photosensitive synapse.

6. The dynamic recognition method based on light-controlled neural synaptic array as described in claim 4, characterized in that, The light-controlled synapse includes a PNP transistor; the step of applying a parallel voltage signal to the light-controlled synapse array and obtaining the timing resistance values ​​of multiple light-controlled synapses in the light-controlled synapse array under the parallel voltage signal includes: With a high-level voltage signal applied to the emitter of the PNP transistor, a low-level voltage signal is applied to the base of the PNP transistor to obtain the timing resistance value of the target photosensitive neural synapse.

7. An electronic device, comprising a processor and a memory; said memory having storage for computer programs, wherein, When executed by the processor, the computer program implements the dynamic recognition method based on the light-controlled neural synaptic array as described in any one of claims 4-6.

8. A computer storage medium, characterized in that, It stores a computer program, wherein when the computer program is executed by a processor, it implements the dynamic recognition method based on a light-controlled neural synaptic array as described in any one of claims 4-6.

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