Display device including multiplexer

Abstract

A display device including a multiplexer is disclosed. The display device includes: a timing control section for generating image data, a data control signal, and a gate control signal; a data driving section for generating a data voltage using the image data and the data control signal; a gate driving section for generating a gate voltage using the gate control signal; a display panel including a plurality of sub-pixels and displaying an image using the data voltage and the gate voltage; and a plurality of first MUX switches and a plurality of second MUX switches for sequentially transmitting the data voltage to two sub-pixels of the same color among the plurality of sub-pixels.

Description

[0001] This application is a divisional application of the invention patent application with the application date of December 23, 2021, application number 202111588750.1, and invention title "Display device including a multiplexer and driving method thereof". Technical Field

[0002] The present invention relates to a display device, and more particularly, to a display device including a multiplexer and a method of driving the display device, in which a voltage of one output terminal of a data driving unit is supplied to two sub-pixels of the same color by using the multiplexer. Background Art

[0003] With the development of the information age, display devices have developed rapidly. In the field of display devices, traditional cathode ray tubes (CRTs) have been rapidly replaced by flat panel display (FPD) devices with thin profiles, light weights, and low power consumption. FPD devices include liquid crystal display (LCD) devices, plasma display panels (PDPs), organic light emitting display (OLED) devices, and field emission display (FED) devices.

[0004] The display device displays an image by supplying a data voltage output from a data driving unit to pixels of a display panel. As the resolution increases, the number of pixels increases. Since the number of output terminals of the data driving unit increases, the size and number of the data driving unit increase and the manufacturing cost of the display device increases.

[0005] When the display panel is applied to a touch display device, the volume of the touch display device increases due to an additional driving unit for touch sensing. In particular, it is difficult to obtain a flexible touch display device due to the additional touch driving unit and the additional display driving unit. Summary of the Invention

[0006] Accordingly, the present invention aims to provide a display device that generally overcomes one or more problems caused by limitations and disadvantages of the related art.

[0007] One object of the present invention is to provide a display device including a multiplexer and a method of driving the display device, in which the number of digital-to-analog converters is reduced, and the size, number, and manufacturing cost of the data driving unit are reduced.

[0008] Another object of the present invention is to provide a display device including a multiplexer and a method of driving the display device, in which brightness deviation is reduced and deterioration such as vertical line stains is prevented.

[0009] Still another object of the present invention is to provide a display device including a multiplexer and a method of driving the display device, in which brightness uniformity is improved, optical compensation is optimized, and power consumption is reduced.

[0010] Additional features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or can be learned by practice of the present invention. These and other advantages of the present invention can be realized and obtained by the structures specifically pointed out in the specification, claims and drawings.

[0011] In order to achieve these and other advantages and in accordance with the intention of the present invention, as specifically embodied and broadly described herein, a display device includes: a timing control unit for generating image data, a data control signal, and a gate control signal; a data driving unit for generating a data voltage by using the image data and the data control signal; a gate driving unit for generating a gate voltage by using the gate control signal; a display panel including a plurality of sub-pixels and displaying an image by using the data voltage and the gate voltage; and a plurality of first MUX switches and a plurality of second MUX switches for sequentially transmitting the data voltage to two sub-pixels of the same color among the plurality of sub-pixels.

[0012] In another aspect, a method of driving a display device includes: generating image data, a data control signal, and a gate control signal; generating a data voltage by using the image data and the data control signal; generating a gate voltage by using the gate control signal; sequentially transmitting the data voltage to two sub-pixels of the same color among a plurality of sub-pixels via a plurality of first MUX switches and a plurality of second MUX switches; and displaying an image by using the data voltage and the gate voltage.

[0013] It should be understood that the foregoing general description and the following detailed description are explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the present invention and constitute a part of this application, illustrate embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. In the drawings:

[0015] Figure 1 is a view showing a display device according to a first embodiment of the present invention;

[0016] Figure 2 is a view showing sub-pixels of a display device according to a first embodiment of the present invention;

[0017] Figure 3 is a view showing a data driving unit and a display panel of a display device according to a first embodiment of the present invention;

[0018] Figure 4 is a view showing a data driver unit and a plurality of signals of a display panel according to a first embodiment of the present invention;

[0019] Figure 5 is a view showing an order in which data voltages are provided to a plurality of sub-pixels in a display device according to a first embodiment of the present invention;

[0020] Figure 6 is a view showing parasitic capacitance between a transmission line and a data line in a display device according to a first embodiment of the present invention;

[0021] Figure 7 is a view showing a data driver unit and a display panel of a display device according to a second embodiment of the present invention;

[0022] Figure 8 is a view showing a data driver unit and a plurality of signals of a display panel according to a second embodiment of the present invention;

[0023] Figure 9 is a view showing an order in which data voltages are provided to a plurality of sub-pixels in a display device according to a second embodiment of the present invention;

[0024] Figure 10 is a plan view showing red, green, and blue sub-pixels of a display device according to a second embodiment of the present invention;

[0025] Figure 11 is a view showing parasitic capacitance between a transmission line and a data line in a display device according to a second embodiment of the present invention;

[0026] Figure 12A is a view showing a data driver unit of a display device according to the first and second embodiments of the present invention;

[0027] Figure 12B is a view showing a display device according to the first and second embodiments of the present invention;

[0028] Figure 12C is a view showing a flexible touch display device including a display device according to the first and second embodiments of the present invention. Detailed Description

[0029] The advantages and features of the present invention, and the methods for achieving these advantages and features, will become clear through the exemplary embodiments described below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the disclosure of the present invention is sufficient and complete, to assist those skilled in the art to fully understand the scope of the present invention. In addition, the present invention is only defined by the scope of the appended claims.

[0030] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings for describing the embodiments of the present invention are merely examples. Therefore, the present invention is not limited to the details shown. Similar reference numerals represent similar elements throughout the application. In the following description of the present invention, when a detailed description of a related known function or structure is determined to unnecessarily obscure the focus of the present invention, the detailed description of such known function or structure may be omitted. In the case of using the terms "comprising", "having", and "including" described in this specification, other components may be added, unless a more restrictive term such as "only" is used.

[0031] When interpreting an element, the element is interpreted as including an error or tolerance range, even if there is no explicit description of such error or tolerance range.

[0032] When describing a positional relationship, when the positional relationship between two parts is described as, for example, "on...", "above...", "below...", or "after...", one or more other parts may be provided between these two parts, unless a more restrictive term such as "immediately" or "directly" is used.

[0033] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from other elements. For example, without departing from the scope of the present invention, the first element may be named the second element, and similarly, the second element may be named the first element.

[0034] The features of the embodiments of the present invention may be combined or combined with each other partially or wholly, and may interoperate and drive each other in various technical ways, as can be fully understood by those skilled in the art. The embodiments of the present invention may be implemented independently of each other, or implemented together in a mutually dependent relationship.

[0035] Hereinafter, a touch display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals refer to the same elements throughout. When a detailed description of a well-known function or structure related to the present invention is determined to unnecessarily obscure the gist of the technical concept, the detailed description thereof will be omitted or briefly described.

[0036] Figure 1 is a view showing a display device according to a first embodiment of the present invention. The display device may include an organic light emitting diode (OLED) display device.

[0037] In Figure 1 a display device 110 according to a first embodiment of the present invention includes a timing control unit 120, a data driving unit 130, a gate driving unit 140, and a display panel 150.

[0038] The timing control unit 120 generates image data, a data control signal, and a gate control signal by using an image signal transmitted from an external system (not shown) such as a graphics card or a television system, and a plurality of timing signals such as a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock. The timing control unit 120 transmits the image data and the data control signal to the data driving unit 130, and transmits the gate control signal to the gate driving unit 140.

[0039] The data driving unit 130 generates a data voltage (data signal) by using the data control signal and the image data transmitted from the timing control unit 120, and applies the data voltage to the data lines DL of the display panel 150.

[0040] The gate driving unit 140 generates a gate voltage (gate signal) by using the gate control signal transmitted from the timing control unit 120, and applies the gate voltage to the gate lines GL of the display panel 150.

[0041] The gate driving unit 140 may have an in-panel gate (GIP) type, in which the gate driving unit 140 is provided on a substrate of the display panel 150 having gate lines GL, data lines DL, and pixels P.

[0042] The display panel 150 displays an image by using the gate voltage and the data voltage, and includes a plurality of pixels P, a plurality of gate lines GL, and a plurality of data lines DL.

[0043] Each of the plurality of pixels P includes red, green, and blue sub-pixels SPr, SPg, and SPb. The gate lines GL and the data lines DL cross each other to define the red, green, and blue sub-pixels SPr, SPg, and SPb, and each of the red, green, and blue sub-pixels SPr, SPg, and SPb is connected to the gate lines GL and the data lines DL.

[0044] When the display device 110 is an OLED display device, each of the red, green, and blue sub-pixels SPr, SPg, and SPb may include: a plurality of TFTs such as a switching thin film transistor (TFT), a driving TFT, and a sensing TFT; a storage capacitor; and a light emitting diode.

[0045] Each sub-pixel of the display panel 150 will be described with reference to the accompanying drawings.

[0046] Figure 2 is a view showing sub-pixels of a display device according to a first embodiment of the present invention.

[0047] In Figure 2 each of the red, green, and blue sub-pixels SPr, SPg, and SPb of the display panel 150 of the display device 110 according to the first embodiment of the present invention includes first to tenth transistors T1 to T10, a storage capacitor Cst, and a light-emitting diode Del.

[0048] For example, the first to tenth transistors T1 to T10 may have a positive (P) type.

[0049] The first transistor T1, which is a switching transistor, may be switched according to the n-th gate voltage Scan(n) to transmit the data voltage Vdata. The gate of the first transistor T1 receives the n-th gate voltage Scan(n) of the n-th gate line, the source of the first transistor T1 is connected to the data line DL, and the drain of the first transistor T1 is connected to the sources of the second transistor T2 and the fourth transistor T4.

[0050] The second transistor T2, which is a driving transistor, may be switched according to the voltage of the first electrode of the storage capacitor Cs. The gate of the second transistor T2 is connected to the first electrode of the storage capacitor Cst, the drain of the fifth transistor T5, and the source of the eighth transistor T8; the source of the second transistor T2 is connected to the drain of the first transistor T1 and the source of the fourth transistor T4; the drain of the second transistor T2 is connected to the sources of the third transistor T3 and the fifth transistor T5.

[0051] The third transistor T3 may be switched according to the n-th emission voltage Em(n). The gate of the third transistor T3 receives the n-th emission voltage Em(n), the source of the third transistor T3 is connected to the drain of the second transistor T2 and the source of the fifth transistor T5, and the drain of the third transistor T3 is connected to the source of the sixth transistor T6 and the anode of the light-emitting diode Del.

[0052] The fourth transistor T4 may be switched according to the n-th emission voltage Em(n). The gate of the fourth transistor T4 receives the n-th emission voltage Em(n), the source of the fourth transistor T4 is connected to the drain of the first transistor T1 and the source of the second transistor T2, and the drain of the fourth transistor T4 receives a high-level voltage VDD and is connected to the source of the seventh transistor T7.

[0053] The fifth transistor T5 can be switched according to the nth gate voltage Scan(n). The gate of the fifth transistor T5 receives the nth gate voltage Scan(n). The source of the fifth transistor T5 is connected to the drain of the second transistor T2 and the source of the third transistor T3. The drain of the fifth transistor T5 is connected to the gate of the second transistor T2, the first electrode of the storage capacitor Cst, and the source of the eighth transistor T8.

[0054] The sixth transistor T6 can be switched according to the nth gate voltage Scan(n). The gate of the sixth transistor T6 receives the nth gate voltage Scan(n). The source of the sixth transistor T6 is connected to the drain of the third transistor T3 and the anode of the light-emitting diode Del. The drain of the sixth transistor T6 receives the initialization voltage Vini and is connected to the drain of the eighth transistor T8.

[0055] The seventh transistor T7 can be switched according to the nth light-emitting voltage Em(n). The gate of the seventh transistor T7 receives the nth light-emitting voltage Em(n). The source of the seventh transistor T7 receives the high-level voltage VDD. The drain of the seventh transistor T7 is connected to the second electrode of the storage capacitor Cst and the sources of the ninth transistor T9 and the tenth transistor T10.

[0056] The eighth transistor T8 can be switched according to the (n - 1)th gate voltage Scan(n - 1). The gate of the eighth transistor T8 receives the (n - 1)th gate voltage Scan(n - 1). The source of the eighth transistor T8 is connected to the first electrode of the storage capacitor Cst, the gate of the second transistor T2, and the drain of the fifth transistor T5. The drain of the eighth transistor T8 receives the initialization voltage Vini and is connected to the drain of the sixth transistor T6.

[0057] The ninth transistor T9 can be switched according to the nth gate voltage Scan(n). The gate of the ninth transistor T9 receives the nth gate voltage Scan(n). The source of the ninth transistor T9 is connected to the second electrode of the storage capacitor Cst and the drain of the seventh transistor T7. The drain of the ninth transistor T9 receives the reference voltage Vref.

[0058] The tenth transistor T10 can be switched according to the (n - 1)th gate voltage Scan(n - 1). The gate of the tenth transistor T10 receives the (n - 1)th gate voltage Scan(n - 1). The source of the tenth transistor T10 is connected to the second electrode of the storage capacitor Cst and the drain of the seventh transistor T7, and the drain of the tenth transistor T10 receives the reference voltage Vref.

[0059] The light-emitting diode Del is connected between the third transistor T3 and the low-level voltage VSS and emits light with a brightness proportional to the current of the second transistor T2.

[0060] The light-emitting diode Del emits light according to the operations of the first to tenth transistors T1 to T10 and the storage capacitor Cst, thereby displaying an image. In addition, the display device 110 can compensate for changes in the threshold voltage or degradation of the light-emitting diode according to the duration of use of the sub-pixels. In addition, the display device 110 can control the brightness by driving the light-emitting diode Del according to a duty ratio corresponding to the light-emitting time.

[0061] The data driving unit and the display panel of the display device 110 will be described with reference to the accompanying drawings.

[0062] Figure 3 is a view showing the data driving unit and the display panel of the display device according to the first embodiment of the present invention, Figure 4 is a view showing a plurality of signals of the data driving unit and the display panel of the display device according to the first embodiment of the present invention, Figure 5 is a view showing the order of providing data voltages to a plurality of sub-pixels in the display device according to the first embodiment of the present invention.

[0063] In Figure 3 , the data driving unit 130 of the display device 110 according to the first embodiment of the present invention may include a plurality of latches LT1 to LT6, a plurality of first source switches ST1, a plurality of second source switches ST2, a plurality of red digital-to-analog converters DACr1 and DACr2, a plurality of green digital-to-analog converters DACg1 and DACg2, a plurality of blue digital-to-analog converters DACb1 and DACb2, and a plurality of buffers BF1 and BF2 and BF3. The display panel 150 of the display device 110 according to the first embodiment of the present invention may include a plurality of first multiplexer (MUX) switches MT1, a plurality of second MUX switches MT2, a plurality of red sub-pixels SPr, a plurality of green sub-pixels SPg, and a plurality of blue sub-pixels SPb.

[0064] The data driving unit 130 may be connected to a non-display area surrounding the display area of the display panel 150. The plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 may be provided in the non-display area of the display panel 150.

[0065] The plurality of latches LT1 to LT6 sequentially receive image data of each color from the timing control unit 120 and store the image data of each color for a time corresponding to one clock. Next, the plurality of latches LT1 to LT6 sequentially output the image data of each color to the plurality of red digital-to-analog converters DACr1 and DACr2, the plurality of green digital-to-analog converters DACg1 and DACg2, and the plurality of blue digital-to-analog converters DACb1 and DACb2 through the plurality of first source switches ST1 and the plurality of second source switches ST2.

[0066] For example, the first red image data R1, the third red image data R3, and the fifth red image data R5 can be sequentially input to / sequentially output from the first latch LT1; the first green image data G1, the third green image data G3, and the fifth green image data G5 can be sequentially input to / sequentially output from the second latch LT2; the first blue image data B1, the third blue image data B3, and the fifth blue image data B5 can be sequentially input to / sequentially output from the third latch LT3. The second red image data R2, the fourth red image data R4, and the sixth red image data R6 can be sequentially input to / sequentially output from the fourth latch LT4; the second green image data G2, the fourth green image data G4, and the sixth green image data G6 can be sequentially input to / sequentially output from the fifth latch LT5; the second blue image data B2, the fourth blue image data B4, and the sixth blue image data B6 can be sequentially input to / sequentially output from the sixth latch LT6.

[0067] Multiple first source switches ST1 and multiple second source switches ST2 sequentially transfer the image data of each color output from the adjacent latches LT1 to LT6 to multiple red digital-to-analog converters DACr1 and DACr2, multiple green digital-to-analog converters DACg1 and DACg2, and multiple blue digital-to-analog converters DACb1 and DACb2 at different timings according to the first source enable signal SOE1 and the second source enable signal SOE2.

[0068] For example, according to the first source enable signal SOE1, multiple first source switches ST1 can sequentially transfer the first red image data R1, the third red image data R3, and the fifth red image data R5 of the first latch LT1 to the first red digital-to-analog converter DACr1, can sequentially transfer the first blue image data B1, the third blue image data B3, and the fifth blue image data B5 of the third latch LT3 to the first blue digital-to-analog converter DACb1, and can sequentially transfer the second green image data G2, the fourth green image data G4, and the sixth green image data G6 of the fifth latch LT5 to the second green digital-to-analog converter DACg2.

[0069] According to the second source enable signal SOE2, multiple second source switches ST2 can sequentially transfer the first green image data G1, the third green image data G3, and the fifth green image data G5 of the second latch LT2 to the first green digital-to-analog converter DACg1, can sequentially transfer the second red image data R2, the fourth red image data R4, and the sixth red image data R6 of the fourth latch LT4 to the second red digital-to-analog converter DACr2, and can sequentially transfer the second blue image data B2, the fourth blue image data B4, and the sixth blue image data B6 of the sixth latch LT6 to the second blue digital-to-analog converter DACb2.

[0070] Multiple red digital-to-analog converters DACr1 and DACr2, multiple green digital-to-analog converters DACg1 and DACg2, and multiple blue digital-to-analog converters DACb1 and DACb2 convert the image data input from multiple latches LT1 to LT6 into data voltages and output the data voltages in sequence.

[0071] For example, the first red digital-to-analog converter DACr1 can convert the first red image data R1, the third red image data R3, and the fifth red image data R5 of the first latch LT1 into the first red data voltage Vr1, the third red data voltage Vr3, and the fifth red data voltage Vr5, and can transmit the first red data voltage Vr1, the third red data voltage Vr3, and the fifth red data voltage Vr5 to the first buffer BF1. The first green digital-to-analog converter DACg1 can convert the first green image data G1, the third green image data G3, and the fifth green image data G5 of the second latch LT2 into the first green data voltage Vg1, the third green data voltage Vg3, and the fifth green data voltage Vg5 and can transmit the first green data voltage Vg1, the third green data voltage Vg3, and the fifth green data voltage Vg5 to the first buffer BF1. The first blue digital-to-analog converter DACb1 can convert the first blue image data B1, the third blue image data B3, and the fifth blue image data B5 of the third latch LT3 into the first blue data voltage Vb1, the third blue data voltage Vb3, and the fifth blue data voltage Vb5, and can transmit the first blue data voltage Vb1, the third blue data voltage Vb3, and the fifth blue data voltage Vb5 to the second buffer BF2. The second red digital-to-analog converter DACr2 can convert the second red image data R2, the fourth red image data R4, and the sixth red image data R6 of the fourth latch LT4 into the second red data voltage Vr2, the fourth red data voltage Vr4, and the sixth red data voltage Vr6 and can transmit the second red data voltage Vr2, the fourth red data voltage Vr4, and the sixth red data voltage Vr6 to the second buffer BF2. The second green digital-to-analog converter DACg2 can convert the second green image data G2, the fourth green image data G4, and the sixth green image data G6 of the fifth latch LT5 into the second green data voltage Vg2, the fourth green data voltage Vg4, and the sixth green data voltage Vg6, and can transmit the second green data voltage Vg2, the fourth green data voltage Vg4, and the sixth green data voltage Vg6 to the third buffer BF3. The second blue digital-to-analog converter DACb2 can convert the second blue image data B2, the fourth blue image data B4, and the sixth blue image data B6 of the sixth latch LT6 into the second blue data voltage Vb2, the fourth blue data voltage Vb4, and the sixth blue data voltage Vb6, and can transmit the second blue data voltage Vb2, the fourth blue data voltage Vb4, and the sixth blue data voltage Vb6 to the third buffer BF3.

[0072] Multiple buffers BF1, BF2, and BF3 stabilize multiple data voltages received from multiple red digital-to-analog converters DACr1 and DACr2, multiple green digital-to-analog converters DACg1 and DACg2, and multiple blue digital-to-analog converters DACb1 and DACb2, and sequentially output the multiple data voltages through output terminals (channels).

[0073] For example, the first buffer BF1 can sequentially output, through the first output terminal, the first red data voltage Vr1, the first green data voltage Vg1, the third red data voltage Vr3, the third green data voltage Vg3, the fifth red data voltage Vr5, and the fifth green data voltage Vg5 of the first red digital-to-analog converter DACr1 and the first green digital-to-analog converter DACg1. The second buffer BF2 can sequentially output, through the second output terminal, the first blue data voltage Vb1, the second red data voltage Vr2, the third blue data voltage Vb3, the fourth red data voltage Vr4, the fifth blue data voltage Vb5, and the sixth red data voltage Vr6 of the first blue digital-to-analog converter DACb1 and the second red digital-to-analog converter DACr2. The third buffer BF3 can sequentially output, through the third output terminal, the second green data voltage Vg2, the second blue digital voltage Vb2, the fourth green data voltage Vg4, the fourth blue data voltage Vb4, the sixth green data voltage Vg6, and the sixth blue data voltage Vb6 of the second green digital-to-analog converter DACg2 and the second blue digital-to-analog converter DACb2.

[0074] Multiple first MUX switches MT1 and multiple second MUX switches MT2 sequentially transfer the multiple data voltages output from the multiple buffers BF1, BF2, and BF3 to multiple data lines DL according to a first MUX signal MUX1 and a second MUX signal MUX2.

[0075] For example, according to the first MUX signal MUX1, the multiple first MUX switches MT1 can sequentially transfer the first red data voltage Vr1, the third red data voltage Vr3, and the fifth red data voltage Vr5 of the first buffer BF1 to the first data line, can sequentially transfer the first blue data voltage Vb1, the third blue data voltage Vb3, and the fifth blue data voltage Vb5 of the second buffer BUF2 to the third data line, and can sequentially transfer the second green data voltage Vg2, the fourth green data voltage Vg4, and the sixth green data voltage Vg6 of the third buffer BF3 to the fifth data line.

[0076] According to the second MUX signal MUX2, multiple second MUX switches MT2 can sequentially transmit the first green data voltage Vg1, the third green data voltage Vg3, and the fifth green data voltage Vg5 of the first buffer BF1 to the second data line, can sequentially transmit the second red data voltage Vr2, the fourth red data voltage Vr4, and the sixth red data voltage Vr6 of the second buffer BF2 to the fourth data line, and can sequentially transmit the second blue data voltage Vb2, the fourth blue data voltage Vb4, and the sixth blue data voltage Vb6 of the third buffer BF3 to the sixth data line.

[0077] Multiple red sub-pixels SPr, multiple green sub-pixels SPg, and multiple blue sub-pixels SPb display an image using multiple data voltages transmitted via multiple first MUX switches MT1, multiple second MUX switches MT2, and multiple data lines DL.

[0078] Each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb is connected to the data line DL and the gate line GL, such that the source and the gate of the first transistor T1 ( Figure 2 ) in each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb are respectively connected to the data line DL and the gate line GL.

[0079] For example, the first red sub-pixel SPr1, the first green sub-pixel SPg1, the first blue sub-pixel SPb1, the second red sub-pixel SPr2, the second green sub-pixel SPg2, and the second blue sub-pixel SPb2 on the first horizontal pixel row can emit light corresponding to the brightness of the first red data voltage Vr1, the first green data voltage Vg1, the first blue data voltage Vb1, the second red data voltage Vr2, the second green data voltage Vg2, and the second blue data voltage Vb2, respectively. The third red sub-pixel SPr3, the third green sub-pixel SPg3, the third blue sub-pixel SPb3, the fourth red sub-pixel SPr4, the fourth green sub-pixel SPg4, and the fourth blue sub-pixel SPb4 on the second horizontal pixel row can emit light corresponding to the brightness of the third red data voltage Vr3, the third green data voltage Vg3, the third blue data voltage Vb3, the fourth red data voltage Vr4, the fourth green data voltage Vg4, and the fourth blue data voltage Vb4, respectively. The fifth red sub-pixel SPr5, the fifth green sub-pixel SPg5, the fifth blue sub-pixel SPb5, the sixth red sub-pixel SPr6, the sixth green sub-pixel SPg6, and the sixth blue sub-pixel SPb6 on the third horizontal pixel row can emit light corresponding to the brightness of the fifth red data voltage Vr5, the fifth green data voltage Vg5, the fifth blue data voltage Vb5, the sixth red data voltage Vr6, the sixth green data voltage Vg6, and the sixth blue data voltage Vb6, respectively.

[0080] In Figure 4 it, during the first time period TP1, the (n - 1)-th gate voltage Scan(n - 1) has a low-level voltage and the eighth transistor T8 and the tenth transistor T10 are turned on, such that the first electrode and the second electrode of the storage capacitor Cst have an initialization voltage Vini and a reference voltage Vref respectively. As a result, the storage capacitor Cst is initialized.

[0081] During the second time period TP2 after the first time period TP1, the n-th gate voltage Scan(n) has a low-level voltage, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, such that the first electrode of the storage capacitor Cst has a sum voltage (Vdata + Vth) of the data voltage Vdata and the threshold voltage Vth, and the second electrode of the storage capacitor Cst has the reference voltage Vref. As a result, the storage capacitor Cst stores the compensated data voltage.

[0082] During the third time period TP3 between the first time period TP1 and the second time period TP2, the first MUX signal MUX1 has a low-level voltage and a plurality of first MUX transistors MT1 are turned on. During the fifth time period TP5 that is wider than and overlaps with the third time period TP3, the first red image data R1, the third red image data R3, and the fifth red image data R5 (RGB1(R)) of the first latch LT1 are input. As a result, during the fifth time period TP5, the first red data voltage Vr1, the third red data voltage Vr3, and the fifth red data voltage Vr5 are sequentially transmitted to the first red sub-pixels SPr1, the third red sub-pixels SPr3, and the fifth red sub-pixels SPr5 of the first horizontal pixel row, the second horizontal pixel row, and the third horizontal pixel row respectively.

[0083] During the fourth time period TP4 that connects the third time period TP3 and overlaps with the second time period TP2, the second MUX signal MUX2 has a low-level voltage and a plurality of second MUX transistors MT2 are turned on. During the sixth time period TP6 that is wider than and overlaps with the fourth time period TP4, the first green image data G1, the third green image data G3, and the fifth green image data G5 (RGB2(G)) of the second latch LT2 are input. As a result, during the sixth time period TP6, the first green data voltage Vg1, the third green data voltage Vg3, and the fifth green data voltage Vg5 are sequentially transmitted to the first green sub-pixels SPg1, the third green sub-pixels SPg3, and the fifth green sub-pixels SPg5 of the first horizontal pixel row, the second horizontal pixel row, and the third horizontal pixel row respectively.

[0084] Therefore, in the first horizontal pixel row, during the fifth time period TP5, the first red data voltage Vr1, the first blue data voltage Vb1, and the second green data voltage Vg2 are simultaneously transmitted to the first red sub-pixel SPr1, the first blue sub-pixel SPb1, and the second green sub-pixel SPg2, respectively. In the first horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the first green data voltage Vg1, the second red data voltage Vr2, and the second blue data voltage Vb2 are simultaneously transmitted to the first green sub-pixel SPg1, the second red sub-pixel SPr2, and the second blue sub-pixel SPb2, respectively.

[0085] In the second horizontal pixel row, during the fifth time period TP5, the third red data voltage Vr3, the third blue data voltage Vb3, and the fourth green data voltage Vg4 are simultaneously transmitted to the third red sub-pixel SPr3, the third blue sub-pixel SPb3, and the fourth green sub-pixel SPg4, respectively. In the second horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the third green data voltage Vg3, the fourth red data voltage Vr4, and the fourth blue data voltage Vb4 are simultaneously transmitted to the third green sub-pixel SPg3, the fourth red sub-pixel SPr4, and the fourth blue sub-pixel SPb4, respectively.

[0086] In the third horizontal pixel row, during the fifth time period TP5, the fifth red data voltage Vr5, the fifth blue data voltage Vb5, and the sixth green data voltage Vg6 are simultaneously transmitted to the fifth red sub-pixel SPr5, the fifth blue sub-pixel SPb5, and the sixth green sub-pixel SPg6, respectively. In the third horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the fifth green data voltage Vg5, the sixth red data voltage Vr6, and the sixth blue data voltage Vb6 are simultaneously transmitted to the fifth green sub-pixel SPg5, the sixth red sub-pixel SPr6, and the sixth blue sub-pixel SPb6, respectively.

[0087] In Figure 5 for each of a plurality of horizontal pixel rows, the data voltage is first transmitted to the left sub-pixel among two adjacent sub-pixels of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb, and the data voltage is then transmitted to the right sub-pixel among two adjacent sub-pixels of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb.

[0088] In the display device 110 according to the first embodiment of the present invention, a plurality of data voltages sequentially output from one output terminal (one channel) of the data driving unit 130 are sequentially transmitted to two adjacent sub-pixels in one horizontal pixel row through a plurality of first MUX switches MT1 and a plurality of second MUX switches MT2 of the display panel 150.

[0089] Therefore, since the number of output terminals (pin numbers) of the data driver unit 130 is reduced, the number of required data driver units (integrated circuits) 130 is reduced, and the manufacturing cost is lowered.

[0090] In the display device 110 according to the first embodiment of the present invention, a data voltage is applied to sub-pixels of two adjacent pixels in a plurality of horizontal pixel rows in a zigzag shape as Figure 3 and Figure 5 shown.

[0091] Among all the plurality of horizontal pixel rows, the data voltage is first applied to the left sub-pixel among two adjacent sub-pixels, and then to the right sub-pixel among two adjacent sub-pixels. Since the charging time of the data voltage first applied to the left sub-pixel is longer than the charging time of the data voltage then applied to the right sub-pixel, the data voltage first applied to the left sub-pixel can emit light with a higher brightness than the light emitted by the data voltage then applied to the right sub-pixel.

[0092] Since the difference in the supply order of the data voltage causes a difference in the charging degree of the data voltage and a brightness deviation, deterioration such as vertical line stain may occur.

[0093] When performing optical compensation for the display device 110 according to the first embodiment of the present invention using a brightness detection device such as a camera, it is necessary to consider the brightness non-uniformity due to the Figure 5 shown brightness deviation. As a result, there is a limitation that the brightness detection device has a first resolution corresponding to the sub-pixels.

[0094] Figure 6 is a view showing the parasitic capacitance between the transmission line and the data line in the display device according to the first embodiment of the present invention.

[0095] In Figure 6 , in order to simplify the driving elements of each sub-pixel, first nodes N1 of adjacent red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb are connected to each other through a transmission line TL, and a reference voltage Vref is supplied to a pair of ninth and tenth transistors T9 and T10 of the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb. As a result, the transmission line TL and the data line DL of each sub-pixel overlap each other to form a parasitic capacitance Cpara.

[0096] During a period when the light-emitting diode Del does not emit light due to the duty ratio, the seventh transistor T7 is turned off according to the emission voltage Em(n) corresponding to the cut-off state, and a high-level voltage VDD is not applied to the first node N1, so that the first node N1 is in a floating state.

[0097] Therefore, after the first red data voltage Vr1, the first blue data voltage Vb1, and the second green data voltage Vg2 are transmitted via the data line DL during the third time period TP3, during the fourth time period TP4 when the first green data voltage Vg1, the second red data voltage Vr2, and the second blue data voltage Vb2 are transmitted via the data line DL, the first red data voltage Vr1, the first blue data voltage Vb1, and the second green data voltage Vg2 charged into the sub-pixels are changed due to the coupling of the first green data voltage Vg1, the second red data voltage Vr2, and the second blue data voltage Vb2 via the parasitic capacitance Cpara, resulting in a color perception difference.

[0098] In the display device according to the second embodiment of the present invention, the above-mentioned drawbacks can be improved by sequentially transmitting data voltages to sub-pixels of the same color via the first and second MUX switches.

[0099] Figure 7 is a view showing a data driving unit and a display panel of a display device according to the second embodiment of the present invention, Figure 8 is a view showing a plurality of signals of a data driving unit and a display panel of a display device according to the second embodiment of the present invention, Figure 9 is a view showing the order of providing data voltages to a plurality of sub-pixels in a display device according to the second embodiment of the present invention. The description of parts identical to those of the first embodiment will be omitted.

[0100] In Figure 7 , the data driving unit 230 of the display device 210 (see Figure 12B ) according to the second embodiment of the present invention may include a plurality of latches LT1 to LT6, a plurality of first source switches ST1, a plurality of second source switches ST2, a red digital-to-analog converter DACr1, a green digital-to-analog converter DACg1, a blue digital-to-analog converter DACb1, and a plurality of buffers BF1, BF2, and BF3 respectively connected between the plurality of digital-to-analog converters DACr1, DACg1, DACb1 and a plurality of output terminals. The display panel 250 of the display device 210 according to the second embodiment of the present invention may include a plurality of first MUX switches MT1, a plurality of second MUX switches MT2, a plurality of red sub-pixels SPr, a plurality of green sub-pixels SPg, and a plurality of blue sub-pixels SPb.

[0101] The data driving unit 230 may be connected to a non-display area surrounding the display area of the display panel 250. The plurality of first MUX switches MT1 and the plurality of second MUX switches MT2 may be provided in the non-display area of the display panel 250.

[0102] Multiple latches LT1 to LT6 sequentially receive the image data of each color from the timing control unit and store the image data of each color for a time corresponding to one clock. Next, the multiple latches LT1 to LT6 sequentially output the image data of each color to the red digital-to-analog converter DACr1, the green digital-to-analog converter DACg1, and the blue digital-to-analog converter DACb1 through the multiple first source switches ST1 and the multiple second source switches ST2.

[0103] For example, the first red image data R1, the third red image data R3, and the fifth red image data R5 can be sequentially input to / output from the first latch LT1; the second red image data R2, the fourth red image data R4, and the sixth red image data R6 can be sequentially input to / output from the second latch LT2; the first green image data G1, the third green image data G3, and the fifth green image data G5 can be sequentially input to / output from the third latch LT3. The second green image data G2, the fourth green image data G4, and the sixth green image data G6 can be sequentially input to / output from the fourth latch LT4; the first blue image data B1, the third blue image data B3, and the fifth blue image data B5 can be sequentially input to / output from the fifth switch LT5; the second blue image data B2, the fourth blue image data B4, and the sixth blue image data B6 can be sequentially input to / output from the sixth latch LT6.

[0104] The multiple first source switches ST1 and the multiple second source switches ST2 respectively transmit the image data of each color output from the adjacent latches LT1 to LT6 to the red digital-to-analog converter DACr1, the green digital-to-analog converter DACg1, and the blue digital-to-analog converter DACb1 at different timings according to the first source enable signal SOE1 and the second source enable signal SOE2.

[0105] For example, according to the first source enable signal SOE1, the multiple first source switches ST1 can sequentially transmit the first red image data R1, the third red image data R3, and the fifth red image data R5 of the first latch LT1 to the first red digital-to-analog converter DACr1; can sequentially transmit the first green image data G1, the third green image data G3, and the fifth green image data G5 of the third latch LT3 to the first green digital-to-analog converter DACg1, and can sequentially transmit the first blue image data B1, the third blue image data B3, and the fifth blue image data B5 of the fifth latch LT5 to the first blue digital-to-analog converter DACb1.

[0106] According to the second source enable signal SOE2, multiple second source switches ST2 can sequentially transmit the second red image data R2, the fourth red image data R4, and the sixth red image data R6 of the second latch LT2 to the first red digital-to-analog converter DACr1, can sequentially transmit the second green image data G2, the fourth green image data G4, and the sixth green image data G6 of the fourth latch LT4 to the first green digital-to-analog converter DACg1, and can sequentially transmit the second blue image data B2, the fourth blue image data B4, and the sixth blue image data B6 of the sixth latch LT6 to the first blue digital-to-analog converter DACb1.

[0107] The red digital-to-analog converter DACr1, the green digital-to-analog converter DACg1, and the blue digital-to-analog converter DACb1 convert the image data input from multiple latches LT1 to LT6 into data voltages and sequentially output the data voltages.

[0108] For example, the first red digital-to-analog converter DACr1 can convert the first red image data R1, second red image data R2, fourth red image data R4, third red image data R3, fifth red image data R5, and sixth red image data R6 of the first latch LT1 and the second latch LT2 into the first red data voltage Vr1, second red data voltage Vr2, fourth red data voltage Vr4, third red data voltage Vr3, fifth red data voltage Vr5, and sixth red data voltage Vr6, and can transmit the first red data voltage Vr1, second red data voltage Vr2, fourth red data voltage Vr4, third red data voltage Vr3, fifth red data voltage Vr5, and sixth red data voltage Vr6 to the first buffer BF1. The first green digital-to-analog converter DACg1 can convert the first green image data G1, second green image data G2, fourth green image data G4, third green image data G3, fifth green image data G5, and sixth green image data G6 of the third latch LT3 and the fourth latch LT4 into the first green data voltage Vg1, second green data voltage Vg2, fourth green data voltage Vg4, third green data voltage Vg3, fifth green data voltage Vg5, and sixth green data voltage Vg6 and can transmit the first green data voltage Vg1, second green data voltage Vg2, fourth green data voltage Vg4, third green data voltage Vg3, fifth green data voltage Vg5, and sixth green data voltage Vg6 to the second buffer BF2. The first blue digital-to-analog converter DACb1 can convert the first blue image data B1, second blue image data B2, fourth blue image data B4, third blue image data B3, fifth blue image data B5, and sixth blue image data B6 of the fifth latch LT5 and the sixth latch LT6 into the first blue data voltage Vb1, second blue data voltage Vb2, fourth blue data voltage Vb4, third blue data voltage Vb3, fifth blue data voltage Vb5, and sixth blue data voltage Vb6, and can transmit the first blue data voltage Vb1, second blue data voltage Vb2, fourth blue data voltage Vb4, third blue data voltage Vb3, fifth blue data voltage Vb5, and sixth blue data voltage Vb6 to the third buffer BF3.

[0109] Multiple buffers BF1, BF2, and BF3 stabilize the multiple data voltages received from the red digital-to-analog converter DACr1, green digital-to-analog converter DACg1, and blue digital-to-analog converter DACb1, and sequentially output the multiple data voltages through the output terminals (channels).

[0110] For example, the first buffer BF1 can sequentially output the first red data voltage Vr1, the second red data voltage Vr2, the fourth red data voltage Vr4, the third red data voltage Vr3, the fifth red data voltage Vr5, and the sixth red data voltage Vr6 of the first red digital-to-analog converter DACr1 through the first output terminal. The second buffer BF2 can sequentially output the first green data voltage Vg1, the second green data voltage Vg2, the fourth green data voltage Vg4, the third green data voltage Vg3, the fifth green data voltage Vg5, and the sixth green data voltage Vg6 of the first green digital-to-analog converter DACg1 through the second output terminal. The third buffer BF3 can sequentially output the first blue data voltage Vb1, the second blue data voltage Vb2, the fourth blue data voltage Vb4, the third blue data voltage Vb3, the fifth blue data voltage Vb5, and the sixth blue data voltage Vb6 of the first blue digital-to-analog converter DACb1 through the third output terminal.

[0111] Multiple first MUX switches MT1 and multiple second MUX switches MT2 sequentially transmit multiple data voltages output from multiple buffers BF1, BF2, and BF3 to multiple data lines DL according to the first MUX signal MUX1 and the second MUX signal MUX2. As an implementation, multiple first MUX switches MT1 and multiple second MUX switches MT2 can sequentially transmit the first red image data R1, the second red image data R2, the third red image data R3, the fourth red image data R4, the fifth red image data R5, and the sixth red image data R6 to the first red digital-to-analog converter DACr1, sequentially transmit the first green image data G1, the second green image data G2, the third green image data G3, the fourth green image data G4, the fifth green image data G5, and the sixth green image data G6 to the first green digital-to-analog converter DACg1, and sequentially transmit the first blue image data B1, the second blue image data B2, the third blue image data B3, the fourth blue image data B4, the fifth blue image data B5, and the sixth blue image data B6 to the first blue digital-to-analog converter DACb1.

[0112] For example, according to the first MUX signal MUX1, multiple first MUX switches MT1 can sequentially transmit the first red data voltage Vr1, the third red data voltage Vr3, and the fifth red data voltage Vr5 of the first buffer BF1 to the first data line, can sequentially transmit the first green data voltage Vg1, the third green data voltage Vg3, and the fifth green data voltage Vg5 of the second buffer BUF2 to the second data line, and can sequentially transmit the first blue data voltage Vb1, the third blue data voltage Vb3, and the fifth blue data voltage Vb5 of the third buffer BF3 to the third data line.

[0113] According to the second MUX signal MUX2, multiple second MUX switches MT2 can sequentially transmit the second red data voltage Vr2, the fourth red data voltage Vr4, and the sixth red data voltage Vr6 of the first buffer BF1 to the fourth data line, can sequentially transmit the second green data voltage Vg2, the fourth green data voltage Vg4, and the sixth green data voltage Vg6 of the second buffer BF2 to the fifth data line, and can sequentially transmit the second blue data voltage Vb2, the fourth blue data voltage Vb4, and the sixth blue data voltage Vb6 of the third buffer BF3 to the sixth data line.

[0114] Multiple red sub-pixels SPr, multiple green sub-pixels SPg, and multiple blue sub-pixels SPb display an image using multiple data voltages transmitted via multiple first MUX switches MT1, multiple second MUX switches MT2, and multiple data lines DL.

[0115] For example, on the first horizontal pixel row, the first red sub-pixel SPr1, the first green sub-pixel SPg1, the first blue sub-pixel SPb1, the second red sub-pixel SPr2, the second green sub-pixel SPg2, and the second blue sub-pixel SPb2 can emit light corresponding to the brightness of the first red data voltage Vr1, the first green data voltage Vg1, the first blue data voltage Vb1, the second red data voltage Vr2, the second green data voltage Vg2, and the second blue data voltage Vb2, respectively. On the second horizontal pixel row, the third red sub-pixel SPr3, the third green sub-pixel SPg3, the third blue sub-pixel SPb3, the fourth red sub-pixel SPr4, the fourth green sub-pixel SPg4, and the fourth blue sub-pixel SPb4 can emit light corresponding to the brightness of the third red data voltage Vr3, the third green data voltage Vg3, the third blue data voltage Vb3, the fourth red data voltage Vr4, the fourth green data voltage Vg4, and the fourth blue data voltage Vb4, respectively. On the third horizontal pixel row, the fifth red sub-pixel SPr5, the fifth green sub-pixel SPg5, the fifth blue sub-pixel SPb5, the sixth red sub-pixel SPr6, the sixth green sub-pixel SPg6, and the sixth blue sub-pixel SPb6 can emit light corresponding to the brightness of the fifth red data voltage Vr5, the fifth green data voltage Vg5, the fifth blue data voltage Vb5, the sixth red data voltage Vr6, the sixth green data voltage Vg6, and the sixth blue data voltage Vb6, respectively.

[0116] In Figure 8 during the first time period TP1, the (n - 1)-th gate voltage Scan(n - 1) has a low-level voltage and the eighth transistor T8 and the tenth transistor T10 are turned on, so that the first electrode and the second electrode of the storage capacitor Cst have the initialization voltage Vini and the reference voltage Vref, respectively. As a result, the storage capacitor Cst is initialized.

[0117] During a second time period TP2 after a first time period TP1, the n-th gate voltage Scan(n) has a low-level voltage, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on, such that a first electrode of the storage capacitor Cst has a sum voltage (Vdata + Vth) of a data voltage Vdata and a threshold voltage Vth, and a second electrode of the storage capacitor Cst has a reference voltage Vref. As a result, the storage capacitor Cst stores the compensated data voltage.

[0118] During a third time period TP3 that overlaps with the first time period TP1 and is wider than the first time period TP1, the first MUX signal MUX1 has a low-level voltage and a plurality of first MUX transistors MT1 are turned on. During a fifth time period TP5 that overlaps with the third time period TP3, first red image data R1, third red image data R3, and fifth red image data R5 (RGB1(R)) are input to a first latch LT1. As a result, during the fifth time period TP5, a first red data voltage Vr1, a third red data voltage Vr3, and a fifth red data voltage Vr5 are sequentially transmitted to first red sub-pixels SPr1, third red sub-pixels SPr3, and fifth red sub-pixels SPr5 of a first horizontal pixel row, a second horizontal pixel row, and a third horizontal pixel row, respectively.

[0119] During a fourth time period TP4 that connects the third time period TP3 and overlaps with the second time period TP2, the second MUX signal MUX2 has a low-level voltage and a plurality of second MUX transistors MT2 are turned on. During a sixth time period TP6 that overlaps with the fourth time period TP4, second red image data R2, fourth red image data R4, and sixth red image data R6 (RGB2(R)) are input to a second latch LT2. As a result, a second red data voltage Vr2, a fourth red data voltage Vr4, and a sixth red data voltage Vr6 are sequentially transmitted to second red sub-pixels SPr2, fourth red sub-pixels SPr4, and sixth red sub-pixels SPr6 of the first horizontal pixel row, the second horizontal pixel row, and the third horizontal pixel row, respectively.

[0120] Therefore, in the first horizontal pixel row, during the fifth time period TP5, the first red data voltage Vr1, the first green data voltage Vg1, and the first blue data voltage Vb1 are simultaneously transmitted to the first red sub-pixel SPr1, the first green sub-pixel SPg1, and the first blue sub-pixel SPb1, respectively. In the first horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the second red data voltage Vr2, the second green data voltage Vg2, and the second blue data voltage Vb2 are simultaneously transmitted to the second red sub-pixel SPr2, the second green sub-pixel SPg2, and the second blue sub-pixel SPb2, respectively.

[0121] In the second horizontal pixel row, during the fifth time period TP5, the fourth red data voltage Vr4, the fourth green data voltage Vg4, and the fourth blue data voltage Vb4 are simultaneously transmitted to the fourth red sub-pixel SPr4, the fourth green sub-pixel SPg4, and the fourth blue sub-pixel SPb4, respectively. In the second horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the third red data voltage Vr3, the third green data voltage Vg3, and the third blue data voltage Vb3 are simultaneously transmitted to the third red sub-pixel SPr3, the third green sub-pixel SPg3, and the third blue sub-pixel SPb3, respectively.

[0122] In the third horizontal pixel row, during the fifth time period TP5, the fifth red data voltage Vr5, the fifth green data voltage Vg5, and the fifth blue data voltage Vb5 are simultaneously transmitted to the fifth red sub-pixel SPr5, the fifth green sub-pixel SPg5, and the fifth blue sub-pixel SPb5, respectively. In the third horizontal pixel row, during the sixth time period TP6 after the fifth time period TP5, the sixth red data voltage Vr6, the sixth green data voltage Vg6, and the sixth blue data voltage Vb6 are simultaneously transmitted to the sixth red sub-pixel SPr6, the sixth green sub-pixel SPg6, and the sixth blue sub-pixel SPb6, respectively.

[0123] In the display device 210 according to the second embodiment of the present invention, data voltages are applied to sub-pixels of two adjacent pixels in a plurality of horizontal pixel rows having a square waveform as shown in Figure 7 and Figure 9 shown.

[0124] For odd horizontal pixel rows including the first, third, and fifth horizontal pixel rows, the data voltage is first transmitted to the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb of the left pixel among two adjacent pixels, and secondly the data voltage is transmitted to the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb of the right pixel among two adjacent pixels. For even horizontal pixel rows including the second, fourth, and sixth horizontal pixel rows, the data voltage is first transmitted to the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb of the right pixel among two adjacent pixels, and secondly the data voltage is transmitted to the red sub-pixel SPr, green sub-pixel SPg, and blue sub-pixel SPb of the left pixel among two adjacent pixels.

[0125] Since the charging time of the data voltage applied first is longer than the charging length of the data voltage applied secondly, the data voltage applied first can emit light with a higher brightness than the light emitted by the data voltage applied secondly. However, since the application order of the data voltages for odd horizontal pixel rows and even horizontal pixel rows is opposite to each other, high brightness and low brightness are uniformly mixed within the entire display panel 250, and the brightness deviation is minimized.

[0126] In the display device 210 according to the second embodiment of the present invention, a plurality of data voltages sequentially output from one output terminal (one channel) of the data driving unit 230 are sequentially transmitted to two sub-pixels of the same color of two adjacent pixels in the same horizontal pixel row through a plurality of first MUX switches MT1 and a plurality of second MUX switches MT2 of the display panel 250.

[0127] Therefore, since the number of output terminals (pin numbers) of the data driving unit 230 is reduced and the number of digital-to-analog converters is reduced, the required number of data driving units (integrated circuits) 230 is reduced and the manufacturing cost is lowered.

[0128] In Figure 9 Since the order of applying the data voltage to two sub-pixels of the same color of two adjacent pixels in the odd horizontal pixel row is opposite to the order of applying the data voltage to two sub-pixels of the same color of two adjacent pixels in the even horizontal pixel row, the application order of the data voltage to the entire display panel 250 becomes uniform. As a result, the brightness deviation is reduced and deterioration such as vertical line stains is prevented.

[0129] In addition, when an optical compensation is performed on the display device 210 according to the second embodiment of the present invention using a brightness detection device such as a camera, it is not necessary to consider due to Figure 9Luminance non-uniformity caused by the luminance deviation shown. As a result, an optical compensation can be performed using a luminance detection device having a second resolution lower than the first resolution corresponding to the sub-pixels, thereby eliminating the limitation on the luminance detection device.

[0130] Figure 10 is a plan view showing red, green, and blue sub-pixels of a display device according to a second embodiment of the present invention; Figure 11 is a view showing a parasitic capacitance between a transmission line and a data line in a display device according to a second embodiment of the present invention.

[0131] In Figure 10 and Figure 11 a display device 210 according to a second embodiment of the present invention includes a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb, and each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb includes first to tenth transistors T1 to T10, a storage capacitor Cst, and a light-emitting diode Del.

[0132] The first transistor T1 of the switching transistor can be connected between the data voltage Vdata and the second transistor T2 and the fourth transistor T4, and can be switched according to the n-th gate voltage Scan(n).

[0133] The second transistor T2 of the driving transistor can be connected between the first transistor T1 and the fourth transistor T4, the third transistor T3 and the fifth transistor T5, and can be switched according to the voltage of the first electrode of the storage capacitor Cst.

[0134] The third transistor T3 can be connected between the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the light-emitting diode Del, and can be switched according to the n-th emission voltage Em(n).

[0135] The fourth transistor T4 can be connected between the first transistor T1, the second transistor T2, the seventh transistor T7, and the high-level voltage VDD, and can be switched according to the n-th emission voltage EM(n).

[0136] The fifth transistor T5 can be connected between the second transistor T2, the third transistor T3, and the eighth transistor T8, and can be switched according to the n-th gate voltage Scan(n).

[0137] The sixth transistor T6 can be connected between the third transistor T3 and the eighth transistor T8, and can be switched according to the n-th gate voltage Scan(n).

[0138] The seventh transistor T7 can be connected between the fourth transistor T4, the high-level voltage VDD, the storage capacitor Cst, the ninth transistor T9, and the tenth transistor T10, and can be switched according to the nth emission voltage Em(n).

[0139] The eighth transistor T8 can be connected between the storage capacitor Cst, the sixth transistor T6, and the initialization voltage Vini, and can be switched according to the (n - 1)th gate voltage Scan(n - 1).

[0140] The ninth transistor T9 can be connected between the storage capacitor Cst, the seventh transistor T7, the tenth transistor T10, and the reference voltage Vref, and can be switched according to the nth gate voltage Scan(n).

[0141] The tenth transistor T10 can be connected between the storage capacitor Cst, the seventh transistor T7, the ninth transistor T9, and the reference voltage Vref, and can be switched according to the (n - 1)th gate voltage Scan(n - 1).

[0142] In the display device 210, in order to simplify the driving elements, the first nodes N1 of adjacent red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb are connected through the transmission line TL, and the reference voltage Vref is provided to the red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb through a pair of the ninth transistor T9 and the tenth transistor T10. As a result, the transmission line TL and the data line DL of each of the red sub-pixels SPr, green sub-pixels SPg, and blue sub-pixels SPb overlap each other to form a parasitic capacitance Cpara.

[0143] Here, the first node N1 has a floating state during a period when the light-emitting diode Del does not emit light due to the duty ratio. However, after the first red data voltage Vr1, the first green data voltage Vg1, and the first blue data voltage Vb1 are simultaneously transmitted to the first red sub-pixel SPr1, the first green sub-pixel SPg1, and the first blue sub-pixel SPb1 through the data line DL during the third time period TP3, the second red data voltage Vr2, the second green data voltage Vg2, and the second blue data voltage Vb2 are simultaneously transmitted to the second red sub-pixel SPr2, the second green sub-pixel SPg2, and the second blue sub-pixel SPb2 through the data line DL during the fourth time period TP4. As a result, a situation where the data voltage charged into the sub-pixel is changed due to the coupling of the current data voltage via the parasitic capacitance Cpara is prevented. Since the data voltage is simultaneously transmitted to the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb of one pixel, the coupling generated by the parasitic capacitance Cpara between the transmission line TL commonly connected to the pixel and the data lines DL of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb is prevented. As a result, a change in the charged data voltage is prevented, and the color perception difference is minimized.

[0144] In addition, in the display device 210 according to the second embodiment of the present invention, since the application order of the data voltage is opposite according to the horizontal pixel rows, the periods of the first MUX signal MUX1 and the second MUX signal MUX2 are increased. As a result, the power consumption is reduced, and the sensing period is shortened.

[0145] A flexible touch display device including the display devices according to the first and second embodiments of the present invention will be described below.

[0146] Figure 12A is a view showing a data driving unit of the display device according to the first and second embodiments of the present invention; Figure 12B is a view showing the display device according to the first and second embodiments of the present invention; Figure 12C is a view showing a flexible touch display device including the display device according to the first and second embodiments of the present invention.

[0147] In Figure 12A the data driving unit 130 of the display device 110 according to the first embodiment of the present invention includes a display driving circuit DIC of an integrated circuit (IC) and a chip-on-film COF on which the integrated circuit is mounted, and the data driving unit 230 of the display device 210 according to the second embodiment of the present invention includes a touch driving circuit TIC and a display driving circuit DIC of an integrated circuit (IC) and a chip-on-film COF on which the integrated circuit is mounted.

[0148] Since the display driving circuit DIC of the data driving unit 230 according to the second embodiment of the present invention includes a smaller number of digital-to-analog converters than the display driving circuit DIC of the data driving unit 130 according to the first embodiment, the display driving circuit DIC of the data driving unit 230 according to the second embodiment has a smaller size than the display driving circuit DIC of the data driving unit 130 according to the first embodiment. As a result, the remaining space can be utilized for the touch driving circuit TIC, and the display driving circuit DIC and the touch driving circuit TIC can be formed as one integrated circuit.

[0149] In the display device 110 according to Figure 12B the first embodiment of the present invention, the data driving unit 130 for image display and the display driving unit including the flexible printed circuit board PCB1 are connected to the upper part of the display panel, and the touch driving unit for touch sensing and the touch driving unit including the second printed circuit board PCB2 are connected to the lower part of the display panel. The first printed circuit board PCB1 and the second printed circuit board PCB2 are electrically connected to each other for signal transmission.

[0150] In the display device 210 according to Figure 12B the second embodiment of the present invention, the data driving unit 230 for image display and the touch display driving unit including the first printed circuit board PCB1 are connected to the upper part of the display panel, and no printed circuit board is connected to the lower part of the display panel.

[0151] In Figure 12C when the display device 110 according to the first embodiment of the present invention is applied to a rollable touch display device, the first printed circuit board PCB1 is connected to the rolled end of the display panel, and the second printed circuit board PCB2 is connected to the unrolled end of the display panel.

[0152] The second printed circuit board PCB2 connected to the rolled end of the display panel may interfere with the operation of the rollable touch display device, making it difficult to connect the first printed circuit board PCB1 and the second printed circuit board PCB2.

[0153] When the display device 210 according to the second embodiment of the present invention is applied to a rollable touch display device, the first printed circuit board PCB1 can be connected to the rolled end of the display panel, and no printed circuit board is connected to the unrolled end of the display panel. As a result, the rollable touch display device can be operated freely, and the electrical connection of two separate printed circuit boards can be omitted.

[0154] Therefore, in the display device according to the present invention, since the data voltages sequentially output from one output terminal of the data driving unit are supplied to two sub-pixels of the same color of the display panel by using a multiplexer, the number of digital-to-analog converters in the data driving unit is reduced, and the size and number of the data driving unit are decreased. As a result, the manufacturing cost is reduced.

[0155] In addition, since the data voltages output from the data driving unit are sequentially supplied to the sub-pixels of the same color in the first row and the first column, the first row and the second column, the second row and the second column, and the second row and the first column of the display panel by using a multiplexer, the luminance deviation is reduced and deterioration such as vertical line stains is prevented. As a result, the luminance uniformity is improved, the optical compensation is optimized, and the power consumption is reduced due to the reduction of the switching of the input signals input to the multiplexer.

[0156] It will be apparent to those of ordinary skill in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention is intended to cover all modifications and variations of the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A timing control unit for generating image data, a data control signal, and a gate control signal; A data driver for generating a data voltage using the image data and the data control signal; A gate driver for generating a gate voltage using the gate control signal; A display panel including a plurality of sub-pixels and displaying an image using the data voltage and the gate voltage; And A plurality of first MUX switches and a plurality of second MUX switches for sequentially transmitting the data voltage to two sub-pixels of the same color among the plurality of sub-pixels, Wherein the data driver includes: A plurality of latches for receiving and outputting the image data; A plurality of first source switches and a plurality of second source switches for sequentially transmitting the image data output from the plurality of latches; and A plurality of digital-to-analog converters for converting the image data transmitted through the plurality of first source switches and the plurality of second source switches into the data voltage and sequentially outputting the data voltage, Wherein the image data includes first to sixth red image data, first to sixth green image data, and first to sixth blue image data, Wherein the plurality of latches includes: A first latch for receiving and sequentially outputting first red image data, third red image data, and fifth red image data; A second latch for receiving and sequentially outputting second red image data, fourth red image data, and sixth red image data; A third latch for receiving and sequentially outputting first green image data, third green image data, and fifth green image data; A fourth latch for receiving and sequentially outputting second green image data, fourth green image data, and sixth green image data; A fifth latch for receiving and sequentially outputting first blue image data, third blue image data, and fifth blue image data; and A sixth latch for receiving and sequentially outputting second blue image data, fourth blue image data, and sixth blue image data.

2. The display device according to claim 1, wherein the plurality of digital-to-analog converters include: A first red digital-to-analog converter for receiving first to sixth red image data; A first green digital-to-analog converter for receiving first to sixth green image data; And a first blue digital-to-analog converter for receiving first to sixth blue image data.

3. The display device according to claim 2, wherein the first red digital-to-analog converter receives the first red image data, the third red image data, and the fifth red image data of the first latch through the first source switch, and receives the second red image data, the fourth red image data, and the sixth red image data of the second latch through the second source switch, Wherein the first green digital-to-analog converter receives the first green image data, the third green image data, and the fifth green image data of the third latch through the first source switch, and receives the second green image data, the fourth green image data, and the sixth green image data of the fourth latch through the second source switch, The first blue digital-to-analog converter receives the first blue image data, the third blue image data, and the fifth blue image data of the fifth latch through the first source switch, and receives the second blue image data, the fourth blue image data, and the sixth blue image data of the sixth latch through the second source switch.

4. The display device according to claim 1, wherein the plurality of first source switches and the plurality of second source switches sequentially transmit first red image data, second red image data, third red image data, fourth red image data, fifth red image data, and sixth red image data to the first red digital-to-analog converter; The first green image data, the second green image data, the third green image data, the fourth green image data, the fifth green image data, and the sixth green image data are sequentially transmitted to the first green digital-to-analog converter; And the first blue image data, the second blue image data, the third blue image data, the fourth blue image data, the fifth blue image data, and the sixth blue image data are sequentially transmitted to the first blue digital-to-analog converter.

5. The display device according to claim 1, wherein each of the plurality of sub-pixels includes: The first to tenth transistors; The storage capacitor; And the light-emitting diode.

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