Circuit arrangement and display system

Abstract

To provide a circuit arrangement that can maintain the continuity of synchronization in switching of images.SOLUTION: A selection circuit 150 selects one of internal image data IMA and input image data IMB and outputs it as selected image data IMS. An output circuit 130 outputs output image data IMQ based on the selected image data IMS. A control circuit 140 controls an internal image data output circuit 190 to output the internal image data IMA at a frame rate different from that of the input image data IMB, in a switching period TIMX from the internal image data IMA to the input image data IMB. The control circuit 140 controls the selection circuit 150 to switch from the internal image data IMA to the input image data IMB, in an overlapping period of a vertical blanking period of the internal image data IMA and a vertical blanking period of the input image data IMB.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a circuit device, a display system, and the like.

Background Art

[0002] Patent Document 1 discloses a display system including a switching circuit that switches asynchronous video signals. The switching circuit outputs a video signal synchronized with a vertical synchronization signal VS3 during a certain period after power-on, and outputs a composite video signal synchronized with a vertical synchronization signal VS4 after the switching signal is switched.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, since the vertical synchronization signal VS3 and the vertical synchronization signal VS4 are asynchronous, there is a problem that the continuity of synchronization is impaired when switching video signals. That is, there is no continuity of synchronization between the last synchronization timing of the vertical synchronization signal VS3 before switching and the first synchronization timing of the vertical synchronization signal VS4 after switching. In a display device that receives image data without continuity of synchronization, synchronization becomes unstable and the image is distorted, or measures such as performing black display during a period without continuity of synchronization are taken, which may result in poor appearance of the display.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a circuit device including an internal image data output circuit that outputs internal image data, an input circuit that receives input image data, a selection circuit that selects either the internal image data or the input image data and outputs it as selected image data, an output circuit that outputs output image data based on the selected image data, and a control circuit. The control circuit controls the internal image data output circuit to output the internal image data at a frame rate different from that of the input image data during a switching period from the internal image data to the input image data, and controls the selection circuit to switch from the internal image data to the input image data during an overlapping period between the vertical blanking period of the internal image data and the vertical blanking period of the input image data.

[0006] Another aspect of the present disclosure relates to a display system including the above circuit device and a display device that displays an image based on the output image data.

Brief Description of the Drawings

[0007]

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Modes for Carrying Out the Invention

[0008] Hereinafter, preferred embodiments of the present disclosure will be described in detail. Note that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in the embodiments are essential constituent elements.

[0009] 1. Electronic device, display system FIG. 1 is a configuration example of an electronic device and a display system. The electronic device 400 includes an image output device 20 and a display system 300. The display system 300 includes a circuit device 100 and a display device 200.

[0010] The image output device 20 is a device that transmits input image data IMB to the circuit device 100. Examples of such a device include a camera, a repeater, a splitter, or a microprocessor. The camera captures an image and transmits the image data. The repeater is a device that performs buffering of the input image data. The splitter is a device that divides and transmits the input image data. The microprocessor transmits, for example, image data read from a memory, or performs image processing on the image data read from a memory or input from the outside and then transmits it.

[0011] The circuit device 100 acquires internal image data inside the circuit device 100, receives the input image data IMB from the image output device 20, switches between the internal image data and the input image data IMB, and outputs them as output image data IMQ. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. The circuit device 100 is, for example, a dedicated IC for video switching, or an IC that performs an overlay in addition to video switching, or an IC that incorporates the function of a display controller in addition to video switching.

[0012] The display device 200 receives the output image data IMQ and displays an image corresponding to the output image data IMQ. The display device 200 is, for example, an in-vehicle display device such as a head-up display, a center information display, a cluster panel, a navigation system, or an electronic mirror. Alternatively, the display device 200 may be a television device or a monitor of an information processing terminal. The display device 200 includes a display panel and a display driver that drives the display panel. When the display device 200 is a head-up display, the display device 200 may include a projection optical system that projects an image displayed on the display panel and a light source for projection.

[0013] As an example, the electronic device 400 is an in-vehicle device, the internal image data is image data for displaying the brand logo of an automobile or a device, etc., and the image output device 20 is a SoC that outputs a navigation image or the like. The display device 200 is a head-up display or a center information display that displays information to the passengers. At this time, the circuit device 100 may output a brand logo or the like at the time of starting the in-vehicle device and switch from the brand logo or the like to a navigation image or a meter display or the like after a predetermined time has elapsed.

[0014] 2. Circuit device FIG. 2 is a configuration example of the circuit device. The circuit device 100 includes an internal image data output circuit 190, a memory 195, an input circuit 120, an output circuit 130, a control circuit 140, a selection circuit 150, and a register 180.

[0015] Memory 195 stores the internal image data IMA. Memory 195 may be a non-volatile memory such as an EEPROM or an OTP memory, or may be a volatile memory such as an SRAM or a DRAM. EEPROM is the abbreviation of Electrically Erasable Programmable Read-Only Memory. OTP is the abbreviation of One Time Programmable. SRAM is the abbreviation of Static Random Access Memory. DRAM is the abbreviation of Dynamic Random Access Memory.

[0016] The internal image data output circuit 190 reads the internal image data IMA from the memory 195 and outputs the internal image data IMA at the frame rate set by the control circuit 140. Specifically, the internal image data output circuit 190 generates a timing control signal based on the timing control information set by the control circuit 140, and outputs the internal image data IMA together with the timing control signal. The timing control signal includes, for example, a dot clock, a horizontal synchronization signal, and a vertical synchronization signal. Hereinafter, the internal image data IMA including the timing control signal will simply be referred to as the internal image data IMA. The same applies to the input image data IMB and the output image data IMQ.

[0017] Also, when switching between the internal image data IMA and the input image data IMB, the internal image data output circuit 190 adjusts the frame rate of the internal image data output circuit 190 so that the internal image data IMA and the input image data IMB are switched during the vertical blanking period. This frame rate adjustment will be described later with reference to FIG. 4.

[0018] The input circuit 120 is an image interface circuit that receives the input image data IMB and converts the received input image data IMB into a format used inside the circuit device 100. The internal image data IMA and the input image data IMB are asynchronous. Asynchronous means that the timing control signals are not synchronized. For example, the synchronization timing of the vertical synchronization signals is independent of each other, or the frame rates are different. The specifications of the image interface can be various, such as those where the image data and the timing control signals are transmitted and received as individual signals, those where all or part of the timing control signals are embedded in the image data, those where the timing control signals are demodulated from the image data, or those where the image data and the timing control signals are transmitted and received by packet communication. The specifications of the image interface can be, for example, Open LVDS Display Interface, DisplayPort, or Display Serial Interface 2 of Mobile Industry Processor Interface. The image data format used inside the circuit device 100 can also be various as described above. As an example, it is a format in which the RGB image data and the timing control signals are transmitted as individual signals.

[0019] The selection circuit 150 selects either the internal image data IMA or the input image data IMB and outputs the selected image data as the selected image data IMS. Hereinafter, the case where the selection circuit 150 mainly switches from the internal image data IMA to the input image data IMB will be mainly described, but the selection circuit 150 may also switch from the input image data IMB to the internal image data IMA. Even in the latter case, the frame rate adjustment and the switching during the vertical blanking period described later in FIG. 4 are the same.

[0020] The output circuit 130 outputs the output image data IMQ based on the selected image data IMS. The selected image data IMS is the internal image data IMA without frame rate adjustment, the internal image data IMA with frame rate adjustment, or the input image data IMB. The output circuit 130 outputs it as the output image data IMQ without changing the frame rate of these images.

[0021] Register 180 stores adjustment data 181 for adjusting the frame rate of the internal image data IMA. For example, an external processing device of the circuit device 100 writes the adjustment data 181 into the register 180 via an interface circuit (not shown). Alternatively, the circuit device 100 may include a non-volatile memory (not shown) that stores the adjustment data 181, and the adjustment data 181 may be loaded from the non-volatile memory into the register 180.

[0022] Based on the adjustment data 181 stored in the register 180, the control circuit 140 controls the internal image data output circuit 190, the selection circuit 150, and the output circuit 130. Specifically, the control circuit 140 controls the frame rate adjustment by the internal image data output circuit 190, the selection timing of the image data by the selection circuit 150, and the generation of the synchronization signal of the output image data IMQ by the output circuit 130, based on the frame rate indicated by the adjustment data 181.

[0023] The adjustment data 181 is data indicating at least one of the vertical blanking period and the horizontal blanking period. Based on the control from the control circuit 140, the internal image data output circuit 190 generates the horizontal synchronization signal and the vertical synchronization signal of the internal image data IMA so as to be the blanking period indicated by the adjustment data 181. Since the total number of pixels in a frame is changed by changing the blanking period, the frame rate of the internal image data IMA is changed. The adjustment data 181 may be data indicating the blanking period itself, or may be data indicating the additional amount with respect to the blanking period of the internal image data IMA for which the frame rate is not adjusted. Specific examples of how to change the blanking period will be described after FIG. 5.

[0024] FIG. 3 is a detailed configuration example of the output circuit. The output circuit 130 includes a buffer memory 131, an overlay circuit 135, a synchronization signal generation circuit 133, and an output interface circuit 134. Note that the configuration of the output circuit 130 is not limited to FIG. 3, and for example, the overlay circuit 135 may be omitted.

[0025] The buffer memory 131 buffers the selected image data IMS. The buffer memory 131 absorbs, for example, the delay in the overlay process in the overlay circuit 135 and the like.

[0026] The overlay circuit 135 performs an overlay process on the image data from the buffer memory 131. The overlay circuit 135 overlays predetermined image data on the overlay area for both the internal image data IMA and the input image data IMB. The predetermined image data is, for example, a warning light in a moving body such as an automobile, an icon indicating the state of the electronic device 400 or the moving body on which the electronic device 400 is mounted, or an icon indicating information of an indicator provided on the moving body. However, the predetermined image data is not limited to these and may be image data for displaying any display object. The overlay area is an area smaller than the image size and may be set at any position within the image. The overlay circuit 135 may perform an overlay process on only one of the internal image data IMA and the input image data IMB. Also, the overlay circuit 135 may make at least one of the overlay area and the predetermined image different between the internal image data IMA and the input image data IMB. Hereinafter, the image data after the overlay process will also be referred to as the internal image data IMA and the input image data IMB.

[0027] The synchronization signal generation circuit 133 generates a synchronization signal for the output image data IMQ. Specifically, it generates a synchronization signal for the output image data IMQ based on the dot clock used inside the circuit device 100. The synchronization signal generation circuit 133 generates a synchronization signal for the output image data IMQ so that the output image data IMQ is output at the same frame rate as the frame rate of the image data input from the overlay circuit 135. The synchronization signal input to the synchronization signal generation circuit 133 and the synchronization signal of the output image data IMQ may have their timings changed as long as their frame rates are the same. That is, the timing of the synchronization signal of the output image data IMQ may be any timing according to the image interface standard of the output interface circuit 134, etc., and may be different from the timing of the synchronization signal inside the circuit device 100. Specifically, since the frame rate is determined by the total number of pixels in the frame, the horizontal blanking period or the vertical blanking period may be changed as long as the total number of pixels in the frame is maintained.

[0028] The output interface circuit 134 uses the synchronization signal generated by the synchronization signal generation circuit 133 to output the internal image data IMA or the input image data IMB as the output image data IMQ. The output interface circuit 134 is an image interface circuit that performs conversion from the image data format used inside the circuit device 100 to the transmission standard of the output image data IMQ. The image interface standard and the image data format used inside the circuit device 100 are as described in the input circuit 120. However, the image interface standard of the output interface circuit 134 may be different from the image interface standard of the input circuit 120.

[0029] The control circuit 140 controls the synchronization signal generation circuit 133. Since the control circuit 140 controls the internal image data output circuit 190 and the selection circuit 150, it knows the frame rate of the image input to the synchronization signal generation circuit 133. The control circuit 140 outputs to the synchronization signal generation circuit 133 the frame rate information of the image input to the synchronization signal generation circuit 133, or the timing information of the synchronization signal corresponding to the frame rate. The synchronization signal generation circuit 133 generates a synchronization signal for the output image data IMQ based on the frame rate information or the synchronization signal timing information from the control circuit 140.

[0030] Note that the selection circuit 150 and the control circuit 140 in FIG. 2, and the overlay circuit 135 and the synchronization signal generation circuit 133 in FIG. 3 are constituted by logic circuits. Each of the selection circuit 150, the control circuit 140, the overlay circuit 135, and the synchronization signal generation circuit 133 may be configured as an individual logic circuit. Alternatively, the logic circuit may be a processor. The circuit device 100 may include a memory that stores a program describing the processing of each part of the selection circuit 150, the control circuit 140, the overlay circuit 135, and the synchronization signal generation circuit 133. The processor may realize the processing of each part by executing the program. The processor may include, for example, one or more of a CPU, a GPU, a microcomputer, a DSP, an ASIC, or an FPGA. CPU is the abbreviation of Central Processing Unit. GPU is the abbreviation of Graphics Processing Unit. DSP is the abbreviation of Digital Signal Processor. ASIC is the abbreviation of Application Specific Integrated Circuit. FPGA is the abbreviation of Field Programmable Gate Array.

[0031] FIG. 4 is a timing chart for explaining the operation of the circuit device. FIG. 4 shows an example in which the frame rate of the internal image data IMA without frame rate adjustment and the frame rate of the input image data IMB are the same or substantially the same, and the vertical synchronization timing is different.

[0032] Let the image data in each frame of the internal image data IMA be IMA1, IMA2, ···. The image data is transmitted such as the active period of IMA1, the vertical blanking period, the active period of IMA2, the vertical blanking period, ···. Similarly, let the image data in each frame of the input image data IMB be IMB1, IMB2, ···. The image data is transmitted such as the active period of IMB1, the vertical blanking period, the active period of IMB2, the vertical blanking period, ···.

[0033] The switching period TIMX is a period provided before switching from the internal image data IMA to the input image data IMB, and is a period in which the frame rate of the internal image data IMA is adjusted. Specifically, the switching period TIMX is the period from the start of the frame of the first internal image data IMA after the image switching is started to the timing when the selection circuit 150 switches from the internal image data IMA to the input image data IMB. The start timing of the image switching may be input from outside the control circuit 140 or may be generated by the control circuit 140. The start timing of the image switching may be arbitrary. As an example, when the display system 300 operates according to a predetermined procedure at the power-on, reset, or restart of the display system 300, when the predetermined procedure becomes a step of image switching, the control circuit 140 starts the image switching.

[0034] FIG. 4 shows an example in which the image switching is started before the start of the frame of IMA2. Before the switching period TIMX, the internal image data output circuit 190 outputs IMA1 in the normal frame period TFA. In the switching period TIMX, the internal image data output circuit 190 outputs IMA2, IMA3, IMA4 in a frame period TFX longer than the frame period TFB of the input image data IMB. Thereby, the frame rate of the internal image data IMA becomes slower than the frame rate of the input image data IMB. After the switching period TIMX, the internal image data output circuit 190 outputs IMA5, IMA6 in the normal frame period TFA.

[0035] The selection circuit 150 selects the internal image data IMA before the switching period TIMX and during the switching period TIMX. During the switching period TIMX, since the frame rate of the internal image data IMA is slower than that of the input image data IMB, the time difference between the vertical synchronization timing of the internal image data IMA and the vertical synchronization timing of the input image data IMB becomes smaller. When the vertical blanking period of the internal image data IMA overlaps with the vertical blanking period of the input image data IMB, the selection circuit 150 switches from the internal image data IMA to the input image data IMB during the overlapping period. In the example of FIG. 4, the switching is performed during the overlapping period between the vertical blanking period between IMA4 and IMA5 of the internal image data IMA and the vertical blanking period between IMB5 and IMB6 of the input image data IMB.

[0036] The output circuit 130 outputs the image data selected by the selection circuit 150 without changing the frame rate. That is, when the selection circuit 150 selects the internal image data IMA, the output circuit 130 outputs IMA1 of the frame period TFA and outputs IMA2, IMA3, and IMA4 of the frame period TFX. When the selection circuit 150 selects the input image data IMB, the output circuit 130 outputs IMB6 and IMB7 of the frame period TFB.

[0037] As described above, in the output image data IMQ, the internal image data IMA and the input image data IMB are switched during the vertical blanking period. Thereby, it is possible to avoid image distortion or non-display period in the switching of asynchronous images and provide a good-looking image to the user.

[0038] In this embodiment, the circuit device 100 includes an internal image data output circuit 190, an input circuit 120, a selection circuit 150, an output circuit 130, and a control circuit 140. The internal image data output circuit 190 outputs internal image data IMA. The input circuit 120 receives input image data IMB. The selection circuit 150 selects either the internal image data IMA or the input image data IMB and outputs it as selected image data IMS. The output circuit 130 outputs output image data IMQ based on the selected image data IMS. The control circuit 140 controls the internal image data output circuit 190 to output the internal image data IMA at a frame rate different from that of the input image data IMB during the switching period TIMX from the internal image data IMA to the input image data IMB. The control circuit 140 controls the selection circuit 150 to switch from the internal image data IMA to the input image data IMB during the overlapping period of the vertical blanking period of the internal image data IMA and the vertical blanking period of the input image data IMB.

[0039] According to this embodiment, during the switching period TIMX, since the internal image data IMA is output at a frame rate different from that of the input image data IMB, the time difference between the vertical synchronization timing of the internal image data IMA and the vertical synchronization timing of the input image data IMB becomes smaller. Then, as the time difference becomes smaller, an overlapping period occurs between the vertical blanking period of the internal image data IMA and the vertical blanking period of the input image data IMB. During this overlapping period, by switching from the internal image data IMA to the input image data IMB, the switching between the internal image data IMA and the input image data IMB is performed during the vertical blanking period. Thereby, image distortion or non-display periods during the switching of asynchronous images can be avoided, and a good-looking image can be provided to the user.

[0040] Also, as described with reference to FIG. 4 and the like, the control circuit 140 may control the output circuit 130 to output the output image data IMQ at the frame rate of the internal image data IMA set to a frame rate different from that of the input image data IMB during the switching period TIMX. After the switching period TIMX, the control circuit 140 may control the output circuit 130 to output the output image data IMQ at the frame rate of the input image data IMB.

[0041] According to the present embodiment, the output image data IMQ is output while maintaining the frame rate of the internal image data IMA and the frame rate of the input image data IMB in the selected image data IMS. In the selected image data IMS, the continuity of synchronization is maintained by frame rate adjustment and image switching during the vertical blanking period. Since the output image data IMQ is output without changing the frame rate, the continuity of synchronization is also maintained in the output image data IMQ.

[0042] Also, as will be described later with reference to FIGS. 5 to 10, the control circuit 140 may set the frame rate of the internal image data IMA by adjusting the length of the vertical blanking period, the length of the horizontal blanking period, or the lengths of the vertical and horizontal blanking periods of the internal image data IMA during the switching period TIMX.

[0043] Further, the circuit device 100 may include a register 180 that stores the adjustment data 181 for the frame rate of the internal image data IMA. The control circuit 140 may set the length of the vertical blanking period, the length of the horizontal blanking period, or the lengths of the vertical and horizontal blanking periods of the internal image data IMA based on the adjustment data 181 during the switching period TIMX.

[0044] The frame rate is determined by the total number of pixels in the frame including the blanking area. That is, (total number of horizontal pixels) × (total number of vertical pixels) is the total number of pixels in the frame. According to this embodiment, by adjusting the length of the horizontal blanking period, the total number of horizontal pixels is changed, and by adjusting the length of the vertical blanking period, the total number of vertical pixels is changed. Thereby, the total number of pixels in the frame is changed and the frame rate is adjusted.

[0045] Note that in FIG. 6, the length of the vertical blanking period is adjusted, in FIGS. 7 and 8, the length of the horizontal blanking period is adjusted, and in FIGS. 9 and 10, the lengths of the vertical blanking period and the horizontal blanking period are adjusted.

[0046] Also in this embodiment, the control circuit 140 may set the frame rate of the internal image data IMA to a frame rate slower than the frame rate of the input image data IMB during the switching period TIMX.

[0047] According to this embodiment, as the vertical synchronization timing of the internal image data IMA gradually lags, it approaches the vertical synchronization timing of the input image data IMB. Then, when the time difference in the vertical synchronization timing becomes small, an overlapping period occurs between the vertical blanking period of the internal image data IMA and the vertical blanking period of the input image data IMB.

[0048] Also in this embodiment, the internal image data IMA may be logo image data, icon image data, or black image data.

[0049] According to this embodiment, when switching from logo image data, icon image data, or black image data to asynchronous input image data IMB with a different display content, image distortion or non-display periods can be avoided, and a good-looking image can be provided to the user.

[0050] Also, in this embodiment, the output circuit 130 may include an overlay circuit 135 that overlays predetermined image data on the overlay area of the output image data IMQ.

[0051] The overlay circuit 135 may overlay the predetermined image data on the overlay area both before and after the switching from the internal image data IMA to the input image data IMB.

[0052] The internal image data IMA may be logo image data, icon image data, or black image data. The predetermined image data may be warning light image data.

[0053] According to this embodiment, the predetermined image data can be overlaid on the output image data IMQ and displayed. By performing the overlay before and after the switching, the predetermined image data can be consistently overlaid and displayed from before being switched to the input image data IMB. For example, it becomes possible to always present important displays to the user. For example, from when logo image data, icon image data, or black image data is being displayed at the startup of the display system 300, after being switched to the input image data IMB, the warning light image can be consistently presented to the user.

[0054] Also, in this embodiment, the circuit device 100 may include a register 180 that stores adjustment data 181 for the frame rate of the internal image data IMA. The internal image data output circuit 190 may generate a timing control signal based on the frame rate setting from the control circuit 140 based on the adjustment data 181, and output the internal image data IMA based on the timing control signal.

[0055] According to this embodiment, by the internal image data output circuit 190 generating a timing control signal based on the frame rate setting from the control circuit 140 based on the adjustment data 181, in the switching period TIMX, the internal image data IMA can be output at the frame rate set by the adjustment data 181.

[0056] Also, in the present embodiment, the output circuit 130 may output the output image data IMQ based on a dot clock signal of the same frequency regardless of whether the selection circuit 150 selects the internal image data IMA or the input image data IMB. "Outputting the output image data IMQ based on a dot clock signal of the same frequency" means, for example, outputting the output image data IMQ based on a common and same dot clock signal regardless of which image data is selected.

[0057] According to the present embodiment, when switching between the internal image data IMA and the input image data IMB, the output circuit 130 controls the display timing based on a dot clock signal of the same frequency. As a result, even if the internal image data IMA and the input image data IMB are asynchronous, in the output image data IMQ, the image is switched during the vertical blanking period by the display timing control managed by the dot clock signal of the same frequency.

[0058] 3. Frame Rate Adjustment Hereinafter, an example of the frame rate adjustment performed by the internal image data output circuit 190 will be described.

[0059] FIG. 5 is an example of image data without frame rate adjustment. HSYNC indicates a horizontal synchronization signal, and VSYNC indicates a vertical synchronization signal. Here, the image data is illustrated as two-dimensional data corresponding to the display state, HSYNC is illustrated in association with the horizontal scanning direction in the display state, and VSYNC is illustrated in association with the vertical scanning direction. The area and period in the two-dimensional data can be associated with each other by the period of the dot clock. Hereinafter, there may be cases where the area and period are not distinguished in the description.

[0060] The active area ACAR shown in FIG. 5 is the area displayed on the display device 200. The horizontal active pixel number HAC is the number of pixels in the active area ACAR in the horizontal scanning direction. The vertical active pixel number VAC is the number of pixels in the active area ACAR in the vertical scanning direction.

[0061] The blanking area BLAR is the area other than the active area ACAR among all the areas corresponding to the frame, and includes the horizontal blanking period and the vertical blanking period. The horizontal blanking period is the period other than the active period in the horizontal scanning period where the active area ACAR exists. The vertical blanking period is the period where the active area ACAR does not exist in the vertical scanning period. The total horizontal pixel number HTT is the number of pixels in the horizontal scanning direction of all the areas including the blanking area BLAR and the active area ACAR. The total vertical pixel number VTT is the number of pixels in the vertical scanning direction of all the areas including the blanking area BLAR and the active area ACAR.

[0062] Figure 6 is the first example of frame rate adjustment. The internal image data output circuit 190 slows down the frame rate of the internal image data IMA in the switching period TIMX by increasing the total vertical pixel number VTT.

[0063] AD_BLAR indicates the increased portion of the blanking area BLAR. The number of pixels of the increased portion AD_BLAR in the horizontal scanning direction is the total horizontal pixel number HTT. If the number of pixels of the increased portion AD_BLAR in the vertical scanning direction is ADy, the vertical scanning period becomes longer by HTT×ADy×(the period of the dot clock). As a result, the frame rate becomes slower.

[0064] The adjustment data 181 may be data indicating, for example, the total vertical pixel number VTT, or may be data indicating the number of pixels ADy of the increased portion AD_BLAR in the vertical scanning direction.

[0065] Figure 7 is the second example of frame rate adjustment. The internal image data output circuit 190 slows down the frame rate of the internal image data IMA in the switching period TIMX by increasing the total horizontal pixel number HTT.

[0066] The number of pixels of the increase AD_BLAR in the vertical scanning direction is the total number of vertical pixels VTT. If the number of pixels of the increase AD_BLAR in the horizontal scanning direction is ADx, the vertical scanning period is increased by ADx × VTT × (dot clock period). As a result, the frame rate becomes slower.

[0067] The adjustment data 181 may be data indicating, for example, the total number of horizontal pixels HTT, or may be data indicating the number of pixels ADx of the increase AD_BLAR in the horizontal scanning direction.

[0068] Figure 8 shows a third example of frame rate adjustment. The internal image data output circuit 190 increases the total number of horizontal pixels HTT and combines a plurality of total numbers of horizontal pixels HTT to slow down the frame rate of the internal image data IMA during the switching period TIMX.

[0069] The number of pixels of the increase AD_BLAR in the vertical scanning direction is the total number of vertical pixels VTT. The number of pixels of the increase AD_BLAR in the horizontal scanning direction is different for each horizontal scanning period. In the example of Figure 8, the number of pixels of the increase AD_BLAR in each horizontal scanning period is either ADx1 or ADx2. ADx1 and ADx2 are different. However, the number of pixels of the increase AD_BLAR in each horizontal scanning period may be any of three or more types of pixel numbers. Since the vertical scanning period is increased by (total number of AD_BLAR pixels) × (dot clock period), the frame rate becomes slower. By combining a plurality of total numbers of horizontal pixels HTT, the frame rate can be finely adjusted compared to Figure 6 or Figure 7.

[0070] The adjustment data 181 may be data indicating, for example, the total number of horizontal pixels HTT in each horizontal scanning period, or may be data indicating the number of pixels of the increase AD_BLAR in the horizontal scanning direction in each horizontal scanning period.

[0071] FIG. 9 shows a fourth example of frame rate adjustment. The internal image data output circuit 190 slows down the frame rate of the internal image data IMA during the switching period TIMX by increasing the total horizontal pixel count HTT and the total vertical pixel count VTT.

[0072] Let the number of pixels of the increase amount AD_BLAR in the horizontal scanning direction be ADx, and the number of pixels of the increase amount AD_BLAR in the vertical scanning direction be ADy. Since the vertical scanning period becomes longer by HTT×VTT - {(HTT - ADx)×(VTT - ADy)}×(dot clock period), the frame rate becomes slower.

[0073] The adjustment data 181 may be data indicating, for example, the total horizontal pixel count HTT and the total vertical pixel count VTT, or may be data indicating the number of pixels ADx of the increase amount AD_BLAR in the horizontal scanning direction and the number of pixels ADy of the increase amount AD_BLAR in the vertical scanning direction.

[0074] FIG. 10 shows a fifth example of frame rate adjustment. The internal image data output circuit 190 increases the total horizontal pixel count HTT and the total vertical pixel count VTT, and combines a plurality of total horizontal pixel counts HTT to slow down the frame rate of the internal image data IMA during the switching period TIMX.

[0075] AD_BLAR1 and AD_BLAR2 indicate the increase amounts of the blanking area BLAR. AD_BLAR1 is an area corresponding to the increase in the total horizontal pixel count HTT. Let the number of pixels of the increase amount AD_BLAR1 in the horizontal scanning direction be ADx. AD_BLAR2 is an area corresponding to the increase in the total vertical pixel count VTT. Let the number of pixels of the increase amount AD_BLAR2 in the vertical scanning direction be ADy. However, in the increase amount AD_BLAR2, a horizontal scanning period with the total horizontal pixel count HTT and a horizontal scanning period with the total horizontal pixel count HTT2 are mixed. FIG. 12 shows an example where the total horizontal pixel count is HTT2 in the last horizontal scanning period. HTT2 < HTT. FIG. 12 shows an example where HTT - HTT2 > ADx, but HTT - HTT2 ≤ ADx may also be possible.

[0076] The adjustment data 181 may be data indicating, for example, the total number of horizontal pixels HTT, the total number of vertical pixels VTT, and the total number of horizontal pixels HTT2 in the last horizontal scanning period. Alternatively, the adjustment data 181 may be data indicating the number of pixels ADx of the additional component AD_BLAR in the horizontal scanning direction, the number of pixels ADy of the additional component AD_BLAR in the vertical scanning direction, and the total number of horizontal pixels HTT2 in the last horizontal scanning period.

[0077] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modified examples are intended to be included within the scope of the present disclosure. For example, in the specification or the drawings, a term described together with at least one broader or synonymous different term may be replaced with that different term anywhere in the specification or the drawings. Also, all combinations of the present embodiment and the modified examples are included within the scope of the present disclosure. Further, the configurations and operations of the electronic device, display system, display device, circuit device, image output device, input circuit, internal image data output circuit, memory, selection circuit, output circuit, control circuit, register, etc. are not limited to those described in the present embodiment, and various modified implementations are possible.

Explanation of Reference Numerals

[0078] 20... Image output device, 100... Circuit device, 120... Input circuit, 130... Output circuit, 131... Buffer memory, 133... Synchronization signal generation circuit, 134... Output interface circuit, 135... Overlay circuit, 140... Control circuit, 150... Selection circuit, 180... Register, 181... Adjustment data, 190... Internal image data output circuit, 195... Memory, 200... Display device, 300... Display system, 400... Electronic device, IMA... Internal image data, IMB... Input image data, IMQ... Output image data, IMS... Selected image data, TIMX... Switching period

Claims

1. An internal image data output circuit that outputs internal image data, An input circuit that receives input image data, A selection circuit that selects either the internal image data or the input image data and outputs it as selected image data, An output circuit that outputs output image data based on the selected image data, A control circuit, Comprising, The control circuit, In the switching period from the internal image data to the input image data, controls the internal image data output circuit to output the internal image data at a frame rate different from that of the input image data, In the overlapping period of the vertical blanking period of the internal image data and the vertical blanking period of the input image data, controls the selection circuit to switch from the internal image data to the input image data. A circuit device characterized by this.

2. In the circuit device according to Claim 1, The control circuit, In the switching period, controls the output circuit to output the output image data at the frame rate of the internal image data set to a frame rate different from that of the input image data, After the switching period, controls the output circuit to output the output image data at the frame rate of the input image data. A circuit device characterized by this.

3. In the circuit device according to Claim 1, The control circuit, In the switching period, sets the frame rate of the internal image data by adjusting the length of the vertical blanking period, the length of the horizontal blanking period, or the length of the vertical blanking period and the length of the horizontal blanking period of the internal image data. A circuit device characterized by this.

4. In the circuit device according to Claim 3, Including a register that stores adjustment data for the frame rate of the internal image data, The control circuit, In the switching period, sets the length of the vertical blanking period, the length of the horizontal blanking period, or the length of the vertical blanking period and the length of the horizontal blanking period of the internal image data based on the adjustment data. A circuit device characterized by this.

5. In the circuit device according to Claim 1, The control circuit, In the switching period, sets the frame rate of the internal image data to a frame rate slower than the frame rate of the input image data. A circuit device characterized by this.

6. The circuit device according to claim 1, wherein the internal image data is logo image data, icon image data, or black image data.

7. The circuit device according to claim 1, wherein the output circuit includes an overlay circuit that overlays predetermined image data on an overlay area of the output image data.

8. The circuit device according to claim 7, wherein the overlay circuit overlays the predetermined image data on the overlay area both before and after the switching from the internal image data to the input image data.

9. The circuit device according to claim 8, wherein the internal image data is logo image data, icon image data, or black image data, and the predetermined image data is warning light image data.

10. The circuit device according to claim 1, including a register that stores adjustment data for the frame rate of the internal image data, wherein the internal image data output circuit generates a timing control signal based on a frame rate setting from the control circuit based on the adjustment data, and outputs the internal image data based on the timing control signal.

11. The circuit device according to claim 1, wherein the output circuit outputs the output image data based on a dot clock signal of the same frequency regardless of whether the selection circuit selects the internal image data or the input image data.

12. A display system, comprising: the circuit device according to any one of claims 1 to 11; and a display device that displays an image based on the output image data.

Images