Method and system for predicting service life of high-capacity NAND flash memory
Through the method based on physical characteristics and multivariate linear regression, the complexity problem of 3D NAND Flash lifetime prediction is solved, providing a fast, accurate and suitable life prediction method for resource-constrained environments, suitable for life prediction of 3D NAND Flash.
Patent Information
- Application Number
- CN202510421333.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-07-08
AI Technical Summary
The existing 3D NAND Flash life prediction relies on complex machine algorithms, with high computational complexity, large resource requirements, and limited model generalization capabilities, making it difficult to meet the needs of real-time and cross-chip applicability.
Using a non-machine learning method based on physical characteristics and multivariate linear regression, by calculating the read operation frequency and bit error rate of the storage system, the change trend of the bit error rate with the number of P/E cycles and read operations is fitted, and prediction is made with real-time data feedback.
It achieves fast and accurate life prediction, with an error rate of less than 15%, is suitable for resource-constrained environments and has good cross-chip applicability.
Smart Images
Figure CN120279970A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of 3D NAND Flash, and particularly relates to a method and system for predicting the lifespan of 3D NAND Flash. Background Art
[0002] Flash memory has gradually become the most important data storage support due to its low cost and high performance. With the growth of data storage requirements, the flash memory structure has evolved from traditional planar NAND to a three-dimensional stacked architecture, achieving greater unit density and lower bit cost. However, compared with traditional planar NAND Flash, the reliability characteristics of 3D NAND Flash have changed significantly.
[0003] Due to the adoption of a vertical stacked structure, 3D NAND Flash introduces new challenges while increasing storage density, such as increased crosstalk between cells and more complex data retention problems. This structure leads to uneven electron distribution in the charge trapping layer, increasing interference between adjacent cells, especially in high-density storage arrays. In addition, as the number of programming / erasing (P / E) cycles increases and the read operation frequency rises, the threshold voltage distribution of storage cells changes faster, and the bit error rate also climbs rapidly, posing a greater test to the reliability of 3D NAND Flash during use.
[0004] The reliability of flash memory is intuitively manifested as the raw bit error rate of a given area and the error correction ability of that area. The raw bit error rate (RBER) of 3D NAND Flash refers to the probability of data bit errors without any error correction, which is an important indicator to measure the reliability of NAND Flash memory. To reduce the bit error rate, modern 3D NAND Flash usually integrates advanced error correction coding (ECC) mechanisms, such as low-density parity-check codes (LDPC), which can effectively identify and correct data errors within a certain range.
[0005] The main reasons for data bit errors include: First, during programming and erasing, 3D NAND Flash undergoes electron tunneling effects, which may cause the insulation layer to degrade over time, leading to increased interference between cells and ultimately an increase in the bit error rate; Second, frequent read operations may change the states of neighboring storage cells, especially in high-density three-dimensional storage arrays, where this phenomenon is more significant. Read interference can cause data bit flips, thus increasing the bit error rate.
[0006] Currently, the lifespan prediction of 3D NAND Flash mainly relies on machine learning and deep learning methods, such as artificial neural networks, Transformer models, and kernel extreme learning machines. Although these algorithms can provide relatively high prediction accuracy, they suffer from problems such as high computational complexity, the need for a large amount of training data and computing resources, and are difficult to meet real-time requirements. In addition, the model generalization ability is limited, and there are significant differences in lifespan characteristics between different chips, which restricts the promotion ability of the model. More importantly, existing models often need to obtain lifespan prediction data through a large number of wear tests, which is not only time-consuming but also occupies a large amount of storage space. Summary of the Invention
[0007] The present invention aims to solve the problem of relying on complex machine algorithms in the existing 3D NAND Flash lifespan prediction technology, and provides a high-capacity NAND flash lifespan prediction method with high prediction efficiency and accuracy, which is based on the physical characteristics and non-machine learning of multiple linear regression. At the same time, a system for implementing this method is provided.
[0008] The high-capacity NAND flash lifespan prediction method of the present invention includes the following steps:
[0009] (1) Calculate the frequency of the current read operation of the storage system, and judge whether the data is hot data according to a preset standard;
[0010] (2) Mark the hot data as data to be predicted, record its error rate, collect the initial error rate RBER|pe = 0k at different P / E cycle numbers pe, and based on the initial error rate in the low wear state, fit the trend of the error rate changing with the P / E cycle number pe and the read operation number rd, and determine the maximum read operation number at this P / E cycle number;
[0011] (3) According to the predicted maximum wear times and the read operation number threshold, and compare with the actual wear situation of the current data. When approaching or reaching the preset safety limit, send a warning signal to the user.
[0012] The preset standard in the step (1) is that if the read operation command is accessed more than 10 times within one hour, the data is identified as hot data.
[0013] In the step (2), the trend of the error rate changing with the P / E cycle number and the read operation number is fitted by using the multiple linear regression method.
[0014] The process of fitting the trend of the error rate changing with the P / E cycle number and the read operation number rd in the step (2) is as follows:
[0015] ①Collect the initial bit error rates under different P / E cycle numbers. Under the condition of low P / E cycle numbers, fit the straight-line slope A and intercept B under different wear degrees through experimental data;
[0016] ②Use the straight-line intercept B = X*pe + Y*RBER| pe＝0k +Z and the straight-line slope A = (L*pe + M*(X*pe + Y*RBER| pe＝0k +Z)+N) to calculate the specific values of L, M, N, X, Y, and Z. L, M, N, X, Y, and Z are constants determined by experiments;
[0017] ③Use the formula RBER(pe, rd) = (L*pe + M*(X*pe + Y*RBER| pe＝0k +Z)+N)*rd + X*pe + Y*RBER| pe＝0k +Z to calculate the bit error rate under this P / E cycle number condition and obtain the change trend of the bit error rate with the number of read operations rd; RBER| pe＝0k is the initial bit error rate corresponding to different P / E cycle numbers when only one read operation is performed; pe and RBER| pe＝0k are known quantities, and rd is the independent variable.
[0018] In step (2), feedback processing is performed according to real-time data to correct the prediction result.
[0019] In step (3), the safety limit refers to the maximum P / E cycle number and the number of read operations that the chip can withstand.
[0020] In actual operation, in order to obtain the straight-line slope, intercept, and initial bit error rate in the low-wear state, relevant data needs to be collected under a certain number of P / E cycles and read operations. These data are used to calibrate the model parameters to ensure prediction accuracy.
[0021] For the system implementing the above-mentioned large-capacity NAND flash memory life prediction method, the following technical solutions are adopted:
[0022] The system includes a data status judgment module, a bit error prediction module, and a life warning module;
[0023] The data status judgment module is used to receive the read operation command of the storage system, calculate the frequency of the read operation, judge the data type according to the preset standard, and transfer the bit error rate of the hot data to the bit error prediction module;
[0024] The bit error prediction module, based on the initial bit error rate in the low-wear state, fits the change trend of the bit error rate with the P / E cycle number and the number of read operations, determines the maximum number of read operations under this P / E cycle number; calculates the bit error rate under specific conditions; performs feedback processing according to real-time data to correct the prediction result;
[0025] The lifetime warning module receives the maximum number of wear times and the read operation times threshold from the error code prediction module, and compares them with the actual wear condition of the current data. When approaching or reaching the preset safety limit (the maximum number of P / E cycles and read operation times that the chip can withstand), it sends a warning signal to the user.
[0026] The error code prediction module regularly checks the new data generated during actual operation and uses this new data to re-evaluate the model parameters to ensure that the prediction model can provide real-time feedback to guarantee the accuracy of the prediction results.
[0027] The above method analyzes the data changes under a small number of P / E (programming / erasing) cycles and read operation times, quickly and accurately predicts the change trend of the error code rate with the read operation times under different wear levels, so as to effectively predict the short-term service life of 3D NAND Flash. And this method can also perform feedback processing based on real-time data to correct the prediction, providing efficient technical support for the reliability management of the storage system.
[0028] The method of the present invention can complete the high-precision prediction of the remaining life of 3D NAND Flash within a short time with an error rate lower than 15%. Compared with traditional methods, the present invention not only improves the prediction speed, but also does not require a large amount of training data or a complex model training process, and is especially suitable for resource-constrained environments. In addition, the design based on the physical model makes this method have good cross-chip applicability, reduces the need for customization for specific hardware, and greatly improves its practical value. Brief Description of the Drawings
[0029] Figure 1 It is a schematic diagram of the architecture of the large-capacity NAND flash lifetime prediction system of the present invention.
[0030] Figure 2 It is a flow chart of error code prediction.
[0031] Figure 3 It is a schematic diagram of the fitting curve of the error code rate with the read operation times after the initial programming operation.
[0032] Figure 4 It is a schematic diagram of the change curve of the error code rate with the read operation times after the initial programming operation.
[0033] Figure 5 It is a schematic diagram of the change curve of the error code rate with the read operation times under different wear levels.
[0034] Figure 6 It is a fitting schematic diagram of values A and B under different wear levels.
[0035] Figure 7It is a schematic diagram comparing the predicted value and the actual value of the error rate of an actual 3D NAND Flash particle when the number of P / E cycles is 3k. Detailed implementation mode
[0036] The large-capacity NAND flash memory life prediction system in the present invention, as Figure 1 shown, includes a data status judgment module, an error code prediction module, and a life warning module. Before using the error rate prediction method of the present invention, the storage system needs to be initialized, including installing a data status judgment module, an error code prediction module, and a life warning module, ensuring normal communication between modules, and collecting data under low wear times and low read operation times for preliminary calibration of model parameters. The following combines the functions of each module to detail the process of the large-capacity NAND flash memory life prediction method of the present invention.
[0037] 1. The data status judgment module is responsible for receiving the read operation command of the system, calculating the frequency of the read operation, and judging the data type according to a preset standard.
[0038] When the storage system receives a request for a read operation, the data status judgment module performs the following tasks:
[0039] ① Calculate the frequency of the current read operation;
[0040] ② According to the preset standard, judge whether the data is "hot data" or "cold data", and mark the "hot data" as the data to be predicted;
[0041] Set that if the read operation command is accessed more than 10 times within one hour, the data is identified as "hot data"; if it is not more than 10 times, the data is identified as "cold data" and no processing is performed;
[0042] ③ For the data block identified as "hot data", record its error rate and other information, and pass it to the error code prediction module; for "cold data", no processing is performed.
[0043] 2. The error code prediction module, based on the initial error rate under the low wear state, uses the multiple linear regression method to fit the trend of the error rate changing with the number of P / E cycles and the number of read operations; calculates the error rate under specific conditions: performs feedback processing according to real-time data and corrects the prediction result.
[0044] After receiving data from other modules, the error code prediction module performs error rate prediction according to the following steps. For details, see Figure 2 the process given.
[0045] Step 1: Collect the initial error rate at different numbers of P / E cycles (the error rate in the unworn state: RBER| pe＝0k) Under the condition of a low number of P / E cycles, the straight-line slope A and intercept B under different degrees of wear are fitted through experimental data.
[0046] Figure 3 The fitted curve of the bit error rate versus the number of read operations after the initial programming operation is given. Figure 4 The curve of the change of the bit error rate versus the number of read operations after the initial programming operation is given.
[0047] For the curve of the change of the bit error rate versus the number of read operations under different degrees of wear, see Figure 5 . For the fitting of the A and B values under different degrees of wear, see Figure 6 .
[0048] Step 2: Use the straight-line intercept B = X*pe + Y*RBER| pe＝0k +Z and the straight-line slope A = (L*pe + M*(X*pe + Y*RBER| pe＝0k +Z)+N) to calculate the specific values of L, M, N, X, Y, and Z.
[0049] Step 3: Use the formula RBER(pe, rd) = (L*pe + M*(X*pe + Y*RBER| pe＝0k +Z)+N)*rd + X*pe + Y*RBER| pe＝0k +Z. According to the known values of pe (number of P / E cycles) and RBER|pe = 0k (initial bit error rate), calculate the change trend of the bit error rate versus the number of read operations under this condition of the number of P / E cycles.
[0050] Step 4: Determine the maximum number of read operations under this condition of the number of P / E cycles and send this signal to the life warning module. To ensure the accuracy of the prediction result, the bit error prediction module should regularly check the new data generated during actual operation and use these new data to re-evaluate the model parameters to ensure that the prediction model can provide real-time feedback.
[0051] 3. Life warning module, which receives the maximum number of wear times and the threshold of the number of read operations from the bit error prediction module, compares with the actual wear condition of the current data, and when approaching or reaching the preset safety limit, sends a warning signal to the user.
[0052] The life warning module compares the cumulative number of read operations of the current data with the maximum number of read operations sent by the bit error prediction module. If it is close to or exceeds the safety limit, that is, the maximum number of P / E cycles and the number of read operations that the chip can withstand, it sends a warning notice to the user, suggesting taking corresponding maintenance measures, see Figure 1 .
[0053] The implementation method of the present invention will be described in detail below based on an actual test system and a 3D NAND Flash memory test chip. The particles used are three types of 3D charge trapping type TLC NAND flash memory particles. The same operation steps are performed on the three different TLC NAND flash memory particles.
[0054] First, by performing multiple read operations on flash memory cells with different wear levels, multiple sets of bit error rate linear slope and intercept values are obtained. Figure 5 The curves of the bit error rate varying with the number of read operations under different wear levels are given. Figure 6 The A and B fitting values under different wear levels are given.
[0055] According to B = X * pe + Y * RBER| pe＝0k + Z and the linear slope A = (L * pe + M * (X * pe + Y * RBER| pe＝0k + Z) + N), the specific values of L, M, N, X, Y, and Z are calculated.
[0056] Using the formula RBER(pe, rd) = (L * pe + M * (X * pe + Y * RBER| pe＝0k + Z) + N) * rd + X * pe + Y * RBER| pe＝0k + Z, based on the known pe (P / E cycle number) and RBER|pe = 0k (initial bit error rate) values, the variation trend of the bit error rate with the number of read operations under this P / E cycle number condition is calculated.
[0057] The predicted variation trend is compared with the actual bit error variation trend. As Figure 7 shown, it can be seen that the error rate of this prediction method is lower than 15% and does not require a large amount of training data and a complex model training process.
[0058] The present invention is efficient, accurate, and easy to implement. Verified by a series of laboratory tests, this method can complete the high-precision prediction of the remaining life of 3D NAND Flash within a short time with an error rate lower than 15%, and has good cross-chip applicability.
Claims
1. A method for predicting the lifespan of a large-capacity NAND flash memory, characterized in that, It includes the following steps: (1) Calculate the current read operation frequency of the storage system, and judge whether the data is hot data according to the preset standard; (2) Mark the hot data as the data to be predicted, record its error rate, collect the initial error rate RBER|pe = 0k under different P / E cycle numbers pe, and based on the initial error rate under the low wear state, fit the trend of the error rate changing with the P / E cycle number pe and the read operation number rd, and determine the maximum read operation number under this P / E cycle number; (3) According to the predicted maximum wear times and the read operation number threshold, and compare with the actual wear situation of the current data. When approaching or reaching the preset safety limit, send a warning signal to the user.
2. The method for predicting the lifespan of a large-capacity NAND flash memory according to claim 1, wherein In the step (1), the preset standard is that if the read operation command is accessed more than 10 times within one hour, then the data is identified as hot data.
3. The method for predicting the lifespan of a large-capacity NAND flash memory according to claim 1, wherein, In the step (2), the method of using multiple linear regression is adopted to fit the trend of the error rate changing with the P / E cycle number and the read operation number.
4. The method for predicting the lifespan of a large-capacity NAND flash memory according to claim 1, characterized in that In the step (2), the process of fitting the trend of the error rate changing with the P / E cycle number and the read operation number rd is as follows: ① Collect the initial error rates under different P / E cycle numbers. Under the condition of low P / E cycle numbers, fit the straight-line slope A and intercept B under different wear degrees through experimental data; ②Use the straight-line intercept B = X * pe + Y * RBER| pe＝0k + Z and the straight-line slope A = (L * pe + M * (X * pe + Y * RBER| pe＝0k + Z) + N) to calculate the specific values of L, M, N, X, Y, and Z. L, M, N, X, Y, and Z are constants determined by experiments; ③ Use the formula RBER(pe, rd) = (L * pe + M * (X * pe + Y * RBER| pe＝0k + Z) + N) * rd + X * pe + Y * RBER| pe＝0k + Z to calculate the bit error rate under the condition of the P / E cycle count, and obtain the change trend of the bit error rate with the number of read operations rd; RBER| pe＝0k is the initial bit error rate corresponding to different P / E cycle counts when only one read operation is performed; pe and RBER| pe＝0k are known quantities, and rd is the independent variable.
5. The method for predicting the lifespan of a large-capacity NAND flash memory according to claim 1, wherein In the step (2), feedback processing is performed according to the real-time data, and the prediction result is corrected.
6. The method for predicting the lifespan of a large-capacity NAND flash memory according to claim 1, characterized in that, In the step (3), the safety limit refers to the maximum P / E cycle number and the read operation number that the chip can withstand.
7. A large-capacity NAND flash memory life prediction system that implements the large-capacity NAND flash memory life prediction method according to any one of claims 1-6, characterized in that, It includes a data status judgment module, an error code prediction module, and a life warning module; The data status judgment module is used to receive the read operation command of the storage system, calculate the frequency of the read operation, judge the data type according to the preset standard, and transfer the error rate of the hot data to the error code prediction module; The error code prediction module, based on the initial error rate under the low wear state, fits the trend of the error rate changing with the P / E cycle number and the read operation number, and determines the maximum read operation number under this P / E cycle number; Calculate the error rate under specific conditions; Perform feedback processing according to the real-time data, and correct the prediction result; The life warning module receives the maximum wear times and the read operation number threshold from the error code prediction module, and compares with the actual wear situation of the current data. When approaching or reaching the preset safety limit, send a warning signal to the user.
8. The large-capacity NAND flash memory life prediction system according to claim 7, characterized in that, The error code prediction module regularly checks the new data generated during the actual operation, and uses these new data to re-evaluate the model parameters to ensure that the prediction model can perform real-time feedback.