Substrate chip packaging structure and preparation method thereof

Abstract

In order to solve the problems of poor heat dissipation and function influence caused by heat conduction between chips in the existing chip packaging structure, the invention provides a substrate chip packaging structure, which comprises a substrate, a control chip, a storage chip, a heat conduction layer, an aerogel layer, an intermediate sheet and a packaging adhesive layer, a groove is formed in the substrate, the control chip is embedded in the groove, the heat conduction layer covers the surfaces of the control chip and the substrate, the aerogel layer is located on the side, away from the control chip, of the heat conduction layer, and the interposer is located on the side, away from the heat conduction layer, of the aerogel layer. The aerogel layer is arranged on the substrate, the storage chip is located on the side, away from the aerogel layer, of the interposer, the packaging adhesive layer is arranged on the substrate, the heat conduction layer is partially located in the packaging adhesive layer, and the heat conduction layer partially extends and is exposed out of the packaging adhesive layer. Meanwhile, the invention further discloses a preparation method of the substrate chip packaging structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and particularly relates to a substrate chip packaging structure and a preparation method thereof. Background Art

[0002] In modern electronic devices, as the functional integration degree continues to increase, the performance requirements for chips are becoming increasingly stringent, and the problem of chip space occupation on the circuit board is becoming more and more prominent. Traditional chips are usually installed on the circuit board in a planar layout. Since the function of a single chip is limited, a large number of chips need to be arranged side by side to achieve complex functions, resulting in a significant increase in the area of the circuit board, making it difficult to meet the design requirements of miniaturization and light weight for portable electronic devices, high-density servers, etc.

[0003] To solve the problem of chip space occupation, the prior art has developed two main technical solutions: embedding chips in the substrate and the three-dimensional stacking architecture of chip packaging. The technology of embedding chips in the substrate embeds the chips inside the substrate. Although it reduces the planar occupation area of the circuit board to a certain extent, since the chips are wrapped by the substrate, heat is difficult to dissipate effectively, easily causing local overheating of the chips, resulting in performance degradation or even damage.

[0004] The three-dimensional stacking architecture of chip packaging significantly improves the integration degree within the same projected area by vertically stacking multiple chips. However, this architecture also faces severe heat dissipation challenges. In the three-dimensional stacking architecture, the control chip, as the core unit of the system operation, needs to process a large amount of data and instructions, and its heat generation is much higher than that of other chips. And, due to design considerations such as wiring and signal transmission, the control chip is usually arranged at the bottom of the stacking structure. During the heat dissipation process, the heat dissipated by the control chip needs to pass through multiple layers of stacked chips and packaging materials to conduct to the external heat dissipation device, with extremely high thermal resistance. These high temperatures will not only limit the performance of the control chip itself, but also seriously affect the normal operation of adjacent chips. Especially for memory chips that are extremely sensitive to temperature, the heat dissipated by the control chip will cause the working temperature of the memory chips to rise significantly, resulting in a decrease in the stability of stored data, a decrease in the read and write speed, and even a risk of data loss, greatly restricting the performance of the three-dimensional stacking architecture chips and the expansion of the application range. Summary of the Invention

[0005] Aiming at the problems of poor heat dissipation in the existing chip packaging structure and the functional influence caused by heat conduction between chips, the present invention provides a substrate chip packaging structure and a preparation method thereof.

[0006] The technical solutions adopted by the present invention to solve the above technical problems are as follows: On the one hand, the present invention provides a substrate chip packaging structure, including a substrate, a control chip, a memory chip, a heat conductive layer, an aerogel layer, an intermediate sheet and a packaging adhesive layer, wherein a groove is opened on one side surface of the substrate, the control chip is embedded in the groove, the heat conductive layer covers the surface of the control chip and the substrate, a cavity is formed inside the heat conductive layer, a capillary structure is formed on the inner wall of the cavity, a phase change medium is filled in the cavity, the aerogel layer is located on a side of the heat conductive layer away from the control chip, the intermediate sheet is located on a side of the aerogel layer away from the heat conductive layer, the memory chip is located on a side of the intermediate sheet away from the aerogel layer, the packaging adhesive layer is arranged on the substrate, the control chip, the memory chip, the aerogel layer and the intermediate sheet are all located inside the packaging adhesive layer, the heat conductive layer is partially located inside the packaging adhesive layer, and the heat conductive layer partially extends and is exposed from the packaging adhesive layer.

[0007] Optionally, there are multiple memory chips, and the multiple memory chips are stacked in a stepped manner to form a stepped surface on one side of the multiple memory chips respectively. The memory chip is provided with at least one first solder pad at the position of the step surface, and the first solder pads of two adjacent memory chips are interconnected by a first lead. At least one second solder pad is provided on the surface of the intermediate film facing away from the aerogel layer, and at least one second solder pad is connected to at least one first solder pad by a second lead. A third solder pad is provided on the other side surface of the intermediate film corresponding to the second solder pad, and the second solder pad is electrically connected to the third solder pad. A connecting solder ball is provided between the third solder pad and the substrate to electrically connect them to each other.

[0008] Optionally, the substrate includes a hollow substrate and a multi-layer bottom substrate, the multi-layer bottom substrates are stacked, the hollow substrate is stacked on the bottom substrate located at the top, and the hollow substrate is hollowed out corresponding to the position of the control chip to form the groove, the surface of the bottom substrate is provided with a first circuit pattern, the bottom surface of the hollow substrate is provided with a second circuit pattern, the top surface of the hollow substrate is provided with a fourth solder pad at a position not covering the thermal conductive layer, the connecting solder balls are respectively connected to the third solder pad and the fourth solder pad, the bottom surface of the control chip is provided with a welding terminal, a plurality of first metallized through holes are provided in the bottom substrate, the first circuit pattern, the second circuit pattern and the welding terminal are electrically connected by the first metallized through holes, a plurality of second metallized through holes are provided inside the hollow substrate, and the second metallized through holes are used to electrically connect the second circuit pattern and the fourth solder pad.

[0009] Optionally, the aerogel layer includes silica aerogel and inorganic particles and a glass fiber layer located in the silica aerogel.

[0010] Optionally, the heat conduction layer is a copper layer, grid-shaped grooves are formed on the inner wall of the cavity, the capillary structure is located inside the inner wall of the cavity and the grid-shaped grooves, the capillary structure is a cluster-shaped nickel layer, and the boiling point of the phase change working fluid is 40-90 °C.

[0011] Optionally, the heat conduction layer is exposed on the surface of the encapsulation adhesive layer and the surface of the encapsulation adhesive layer is covered with a graphene coating.

[0012] On the other hand, the present invention provides a preparation method of the substrate chip packaging structure as described above, including the following operations: Embed the control chip into the groove on one side surface of the substrate; Cover the heat conduction layer on the surfaces of the control chip and the substrate; Place an aerogel layer on the side of the heat conduction layer away from the control chip; Weld the interposer to the surface of the substrate, and clamp and fix the heat conduction layer and the aerogel layer; Place the storage chip on the top surface of the interposer; Use encapsulation adhesive to encapsulate the control chip, the storage chip, the aerogel layer, the heat conduction layer and the interposer to form an encapsulation adhesive layer. At the same time, part of the heat conduction layer is exposed from the encapsulation adhesive layer.

[0013] Optionally, the preparation method of the heat conduction layer includes the following operations: Use a copper layer as the base material, and etch grid-shaped grooves on one side surface of the copper layer by laser etching; Perform mask protection on the other side surface of the copper layer, place the copper layer in a nitric acid solution for activation treatment, and wash with water; Use the activated copper layer as the cathode and place it in an electroplating solution for electroplating treatment to form a cluster-shaped nickel layer on one side surface of the copper layer and in the grid-shaped grooves. The electroplating solution includes the following components: Nickel salt 2-5 g / L, ammonium salt 40-80 g / L; The current density of the electroplating treatment is 12-20 A / dm 2 ; After the electroplating treatment, perform plasma hydroxylation treatment on the cluster-shaped nickel layer; Remove the mask from the copper layer, fold the copper layer with the cluster-shaped nickel layer as the inner side, and perform primary welding on the edge of the copper layer by laser welding and reserve the liquid injection port. Perform vacuum pumping and phase change working fluid injection on the liquid injection port, and perform secondary welding on the liquid injection port to form a sealed cavity filled with phase change working fluid inside the copper layer.

[0014] Optionally, the preparation method of the aerogel layer includes the following operations: Mix tetraethyl orthosilicate, ethanol, and water in a molar ratio of 1:(7 - 20):(3 - 8), add acid to adjust the pH value to 2 - 6, and stir at 40 - 80 °C for 200 - 500 min to obtain silica sol; Add ammonia water and inorganic particles, adjust the pH value of the silica sol to 6.5 - 8, and mix the silica sol with the glass fiber layer to obtain a gel layer; Subject the gel layer to hydrophobic modification in a hydrophobic modification liquid, where the hydrophobic modification liquid includes ethanol and hexamethyldisilazane, and the mass percentage of hexamethyldisilazane is 1% - 10%; Dry the gel layer after hydrophobic modification to obtain an aerogel layer.

[0015] Optionally, after forming the encapsulation adhesive layer, the following operations are further included: Coat graphene coating on the surface of the heat conduction layer exposed on the surface of the encapsulation adhesive layer and the surface of the encapsulation adhesive layer, and cure to obtain a graphene coating.

[0016] According to the substrate chip packaging structure provided by the present invention, on the one hand, the control chip and the storage chip are integrally packaged on the same substrate; on the other hand, the control chip is embedded in the substrate; this structure makes full use of the vertical space of the substrate, breaks through the physical limit of traditional planar packaging, the signal transmission distance is shortened by more than 90% compared with PCB wiring, greatly reducing latency and signal loss, and achieving multi-dimensional optimization in terms of integration, performance, power consumption, cost, etc. To solve the problem of poor heat dissipation caused by high integration, a heat conduction layer with a cavity is provided on the top of the control chip with a large amount of heat generation. When the control chip works and generates heat, the phase change working medium in the heat conduction layer absorbs heat and vaporizes and diffuses. At the position exposed on the encapsulation adhesive layer, the phase change working medium in the heat conduction layer condenses and liquefies to release heat, and at the same time, through the capillary action of the capillary structure in the cavity, it absorbs and conducts to the position of the control chip, forming an efficient heat dissipation cycle, effectively reducing the temperature of the control chip. At the same time, to avoid the problem of the influence of the heat conduction of the control chip on the function of the storage chip, an aerogel layer is provided between the heat conduction layer and the interposer. The aerogel layer has a low thermal conductivity and can effectively block the influence of heat conduction upward on the function of the storage chip. Furthermore, through the cooperation of the heat conduction layer and the aerogel layer, the directional heat dissipation efficiency of the substrate chip packaging structure can be improved on the premise of reducing the influence between chips. Description of the Drawings

[0017] Figure 1 is a schematic structural diagram of the substrate chip packaging structure provided by the present invention; Figure 2 is a top view of multiple storage chips provided by the present invention; Figure 3 is a schematic diagram of the inner wall structure of the copper layer provided by the present invention.

[0018] The reference numerals in the accompanying drawings of the specification are as follows: 1. Substrate; 11. Hollow substrate; 111. Second circuit pattern; 112. Second metallized via; 113. Fourth pad; 12. Bottom substrate; 13. Groove; 14. Insulating layer; 121. First circuit pattern; 122. First metallized via; 123. Solder ball; 2. Thermal conductive layer; 21. Cavity; 22. Mesh-like groove; 3. Aerogel layer; 4. Interposer; 5. Memory chip; 51. First pad; 52. First lead; 53. Second lead; 6. Encapsulation adhesive layer; 7. Graphene coating; 8. Connecting solder ball; 9. Control chip; 91. Welding endpoint. Detailed implementation manners

[0019] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] See Figure 1 As shown, an embodiment of the present invention provides a substrate chip packaging structure, including a substrate 1, a control chip 9, a memory chip 5, a thermal conductive layer 2, an aerogel layer 3, an interposer 4 and an encapsulation adhesive layer 6. A groove 13 is formed on one side surface of the substrate 1, the control chip 9 is embedded in the groove 13, the thermal conductive layer 2 covers the surfaces of the control chip 9 and the substrate 1, a cavity 21 is formed inside the thermal conductive layer 2, a capillary structure is formed on the inner wall of the cavity 21, a phase change working fluid is filled in the cavity 21, the aerogel layer 3 is located on the side of the thermal conductive layer 2 away from the control chip 9, the interposer 4 is located on the side of the aerogel layer 3 away from the thermal conductive layer 2, the memory chip 5 is located on the side of the interposer 4 away from the aerogel layer 3, the encapsulation adhesive layer 6 is disposed on the substrate 1, the control chip 9, the memory chip 5, the aerogel layer 3 and the interposer 4 are all located inside the encapsulation adhesive layer 6, and a part of the thermal conductive layer 2 is located inside the encapsulation adhesive layer 6, and a part of the thermal conductive layer 2 extends and exposes outside the encapsulation adhesive layer 6.

[0021] In the substrate chip package structure, on the one hand, the control chip 9 and the memory chip 5 are integrally packaged on the same substrate 1; on the other hand, the control chip 9 is embedded in the substrate 1. This structure makes full use of the vertical space of the substrate 1, breaks through the physical limit of traditional planar packaging, and the signal transmission distance is shortened by more than 90% compared with PCB wiring, greatly reducing latency and signal loss, achieving multi-dimensional optimization in terms of integration, performance, power consumption, cost, etc. To solve the problem of poor heat dissipation caused by high integration, a heat conduction layer 2 with a cavity 21 is provided on the top of the control chip 9 with a large amount of heat generation. When the control chip 9 operates and generates heat, the phase change working fluid in the heat conduction layer 2 absorbs heat and vaporizes and diffuses. At the position exposed to the encapsulation adhesive layer 6, the phase change working fluid in the heat conduction layer 2 condenses and liquefies to release heat, and at the same time, through the capillary action of the capillary structure in the cavity 21, it absorbs and conducts to the position of the control chip 9, forming an efficient heat dissipation cycle, effectively reducing the temperature of the control chip 9. At the same time, to avoid the problem of the influence of the heat conduction of the control chip 9 on the function of the memory chip 5, an aerogel layer 3 is provided between the heat conduction layer 2 and the interposer 4. The aerogel layer 3 has a low thermal conductivity and can effectively block the influence of heat conduction upward on the function of the memory chip 5. Furthermore, through the cooperation of the heat conduction layer 2 and the aerogel layer 3, the directional heat dissipation efficiency of the substrate chip package structure can be improved on the premise of reducing the influence between chips.

[0022] In some embodiments, the part of the heat conduction layer 2 exposed to the encapsulation adhesive layer 6 can be connected to other external heat dissipation devices to improve the heat dissipation efficiency.

[0023] In some embodiments, the number of the memory chips 5 is multiple, and the multiple memory chips 5 are arranged in a stepped and staggered stacked manner, so that stepped surfaces are respectively formed on one side of the multiple memory chips 5. At least one first pad 51 is provided at the position of the stepped surface of the memory chip 5. The first pads 51 between two adjacent memory chips 5 are connected to each other by a first lead 52. At least one second pad is provided on the surface of the interposer 4 facing away from the aerogel layer 3. At least one second pad and at least one first pad 51 are connected to each other by a second lead 53. A third pad is provided on the other surface of the interposer 4 corresponding to the second pad. The second pad is electrically connected to the third pad. A connection solder ball 8 is provided between the third pad and the substrate 1 to be electrically connected to each other.

[0024] The multiple memory chips 5 are arranged in a stepped and staggered stacked manner, increasing the integration degree of the memory chips 5 and reducing signal interference; through the electrical connection structure of the first pad 51, the second pad, the third pad, the leads and the connection solder ball 8, the stable signal transmission between the memory chip 5, the substrate 1 and the control chip 9 is ensured, and the reliability of data transmission is improved.

[0025] As Figure 2 shown, a plurality of first pads 51 are provided at the position of the storage chip 5 on the stepped surface. Specifically, the first pads 51 are located on the surface of the first stepped surface facing away from the interposer 4, and the first pads 51 of the plurality of storage chips 5 are arranged in one-to-one correspondence to form a matrix arrangement structure of multiple rows and multiple columns. The first pads 51 in the same column are sequentially welded and connected through the first leads 52. Correspondingly, the interposer 4 is provided with a plurality of second pads at the arrangement extension positions corresponding to the plurality of first pads 51. The second pads on the interposer 4 are welded and connected to the first pads 51 closest to the second pads through the second leads 53. The interposer 4 is electrically connected to the substrate 1 through the connection solder balls 8, and the substrate 1 is electrically connected to the control chip 9, so as to realize the control of the read and write operations of the control chip 9 on the storage chip 5.

[0026] In some embodiments, the substrate 1 includes a hollow substrate 11 and multiple layers of bottom substrates 12. The multiple layers of bottom substrates 12 are stacked, the hollow substrate 11 is stacked on the topmost bottom substrate 12, and the hollow substrate 11 is hollowed out at the position corresponding to the control chip 9 to form the groove 13. The surface of the bottom substrate 12 is provided with a first circuit pattern 121, the bottom surface of the hollow substrate 11 is provided with a second circuit pattern 111, and a fourth pad 113 is provided at the position on the top surface of the hollow substrate 11 where the heat conduction layer 2 is not covered. The connection solder balls 8 are respectively connected to the third pad and the fourth pad 113. The bottom surface of the control chip 9 is provided with welding endpoints 91. A plurality of first metallized vias 122 are provided in the bottom substrate 12, and the first circuit pattern 121, the second circuit pattern 111 and the welding endpoints 91 are electrically connected by the first metallized vias 122. A plurality of second metallized vias 112 are provided inside the hollow substrate 11, and the second metallized vias 112 are used to electrically connect the second circuit pattern 111 and the fourth pad 113.

[0027] The structure design of the substrate using the hollow substrate 11 and multiple layers of bottom substrates 12 ensures strength and stability, provides space for the embedding of the control chip 9 and reduces costs at the same time; the circuit connection realized through the first metallized vias 122 and the second metallized vias 112 ensures efficient signal transmission between the control chip 9, the storage chip 5 and the substrate 1, and improves the electrical performance of the packaging structure.

[0028] In some embodiments, both the hollow substrate 11 and the bottom substrate 12 are polyimide boards.

[0029] In some embodiments, an insulating layer 14 is further provided between the interposer 4 and the substrate 1, and the insulating layer 14 surrounds the outer periphery of the connection solder balls 8.

[0030] The insulating layer 14 is used to avoid electrical interference between the connecting solder balls 8 and other structures.

[0031] In some embodiments, a plurality of solder balls 123 are provided at the bottom of the substrate 1.

[0032] In some embodiments, the insulating layer 14 is selected from silicone resins.

[0033] In some embodiments, the aerogel layer 3 includes silica aerogel and inorganic particles and glass fiber layers located in the silica aerogel.

[0034] The silica aerogel contains a large number of nano-pores that trap gas therein, thereby achieving a better thermal conduction isolation effect. The inorganic particles and the glass fiber layers are used to support the silica aerogel, reducing its deformation and gas loss after being compressed. The combination of silica aerogel, inorganic particles, and glass fiber layers not only ensures excellent heat insulation performance but also enhances mechanical strength and structural stability.

[0035] In some embodiments, the heat conducting layer 2 is a copper layer. A grid-like groove 22 is formed on the inner wall of the cavity 21. The capillary structure is located inside the inner wall of the cavity 21 and the grid-like groove 22. The capillary structure is a cluster-like nickel layer, and the boiling point of the phase change working fluid is 40 - 90 °C.

[0036] As Figure 3 shown, it is a schematic diagram of the unfolded inner wall of the copper layer.

[0037] In this embodiment, the heat conducting layer 2 is obtained by folding and closing a copper layer to form its cavity 21. The heat conducting layer 2 is a flat sheet-like structure. Therefore, the cavity 21 is also a flat cavity, and it is easy for the two opposite inner walls in the cavity 21 to come into contact with each other, affecting the flow of the phase change working fluid and thus affecting heat dissipation. To avoid this problem, the present invention further improves the structure of the heat conducting layer 2. A grid-like groove 22 is provided on the inner wall of the cavity 21. Even when the two opposite inner walls in the cavity 21 are in contact, the phase change working fluid can still flow through the grid-like groove 22, ensuring the flow of the phase change working fluid. More importantly, a cluster-like nickel layer is provided inside the inner wall of the cavity 21 and the grid-like groove 22. Compared with other existing capillary structures, the cluster-like nickel layer has a large number of nickel structures in a cluster shape, and a large number of micron-sized network-like grooves are formed between the cluster-shaped nickel structures, which can play a good capillary absorption effect on the liquid phase change working fluid, quickly absorb the liquid phase change working fluid from the high-concentration area (the part of the heat conducting layer 2 exposed to the encapsulation adhesive layer 6) to the low-concentration area (the part of the heat conducting layer 2 in contact with the control chip 9), and improve the heat dissipation cycle efficiency.

[0038] In this embodiment, the phase change working fluid is ethanol.

[0039] In some embodiments, the heat conductive layer 2 is exposed on the surface of the packaging glue layer 6 , and the surface of the packaging glue layer 6 is covered with a graphene coating 7 .

[0040] The graphene coating 7 can effectively increase the heat dissipation area of ​​the portion of the heat-conducting layer 2 exposed to the packaging glue layer 6, thereby improving the heat dissipation efficiency without additionally increasing the volume of the overall packaging structure. At the same time, the graphene coating 7 has a good electromagnetic shielding effect. According to the electromagnetic principle, due to the high conductivity of the graphene coating 7, under the action of the external electromagnetic signal, the free electrons in the conductor will move in a directional manner under the action of the electric field force. On the outer surface of the graphene coating 7, a charge distribution opposite to the external electric field will be induced, thereby generating an electromagnetic field opposite to the incident electromagnetic wave, reducing the intensity of the electromagnetic wave passing through the graphene coating 7, achieving the effect of signal shielding, reducing external electromagnetic interference, and improving the stability of the operation of the storage chip 5 and the control chip 9.

[0041] Another embodiment of the present invention provides a method for preparing the substrate chip packaging structure as described above, comprising the following operations: The control chip 9 is embedded in the groove 13 on one side surface of the substrate 1; Covering the heat-conducting layer 2 on the surfaces of the control chip 9 and the substrate 1; An aerogel layer 3 is placed on the side of the heat conducting layer 2 facing away from the control chip 9; The intermediate sheet 4 is welded to the surface of the substrate 1, and the thermal conductive layer 2 and the aerogel layer 3 are clamped and fixed; Placing the memory chip 5 on the top surface of the interposer 4; The control chip 9 , the memory chip 5 , the aerogel layer 3 , the heat-conducting layer 2 and the intermediate chip 4 are encapsulated with encapsulating glue to form an encapsulating glue layer 6 . Meanwhile, a portion of the heat-conducting layer 2 is exposed from the encapsulating glue layer 6 .

[0042] The method for preparing the substrate chip packaging structure of the present invention has simple steps and is easy to operate, can ensure accurate installation and connection between the components of the packaging structure, ensure the stability and reliability of the packaging structure, and is conducive to large-scale production.

[0043] In some embodiments, the method for preparing the thermal conductive layer 2 includes the following operations: A copper layer is used as a substrate, and grid-shaped grooves 22 are etched on one surface of the copper layer by laser etching; The other side of the copper layer is protected by masking, and the copper layer is placed in a nitric acid solution for activation treatment, and then washed with water; The activated copper layer is placed in an electroplating solution as a cathode for electroplating, and a clustered nickel layer is formed on one side surface of the copper layer and in the grid-like grooves 22. The electroplating solution includes the following components: Nickel salt 2-5 g / L, ammonium salt 40-80 g / L; The current density of electroplating treatment is 12~20A / dm 2 ; After the electroplating treatment, the clustered nickel layer is subjected to plasma hydroxylation treatment; The mask of the copper layer is removed, and the copper layer is folded with the clustered nickel layer as the inner side. The edge of the copper layer is initially welded by laser welding and the injection port is retained. The injection port is evacuated and the phase change working fluid is injected. The injection port is welded for a second time to form a closed cavity 21 filled with the phase change working fluid inside the copper layer.

[0044] In the present invention, when the electroplating treatment is performed, a relatively low concentration of nickel salt is required in the electroplating solution, because when the nickel salt concentration is low, nickel ions and hydrogen ions compete and precipitate simultaneously on the surface of the copper layer during the electroplating process, and the precipitated hydrogen bubbles affect the precipitation position of the nickel element, thereby forming a clustered nickel structure.

[0045] When the phase change fluid is an alcohol (such as ethanol), since there is a certain contact angle between nickel and alcohol, it is not conducive to the diffusion of the phase change fluid on the clustered nickel layer. In order to improve the affinity between the clustered nickel layer and the phase change fluid, the clustered nickel layer is subjected to plasma hydroxylation treatment after being prepared, so that the surface of the clustered nickel layer has hydroxyl groups, and there is a hydrogen bond connection between the hydroxyl groups of the alcohol, which can effectively improve the affinity between the clustered nickel layer and the alcohol phase change fluid, thereby improving the diffusion efficiency of the phase change fluid on the surface of the clustered nickel layer and improving the heat dissipation effect.

[0046] In some embodiments, the concentration of the nitric acid solution is 50-300 g / L, and the soaking time is 2-5 min.

[0047] In some embodiments, the nickel salt is selected from nickel chloride, and the ammonium salt is selected from ammonium chloride.

[0048] In some embodiments, the method for preparing the aerogel layer 3 comprises the following operations: Mix ethyl orthosilicate, ethanol and water in a molar ratio of 1:(7-20):(3-8), add acid to adjust the pH value to 2-6, and stir at 40-80°C for 200-500 minutes to obtain silica sol; Ammonia water and inorganic particles are added to adjust the pH value of the silica sol to 6.5-8, and the silica sol is mixed with the glass fiber layer to obtain a gel layer; The gel layer is placed in a hydrophobic modification liquid for hydrophobic modification. The hydrophobic modification liquid includes ethanol and hexamethyldisilazane. Among them, the mass percentage of hexamethyldisilazane is 1% - 10%, and the rest is ethanol; The hydrophobic modified gel layer is dried to obtain an aerogel layer 3.

[0049] In some embodiments, the inorganic particles are titanium dioxide.

[0050] In some embodiments, the drying is carried out by supercritical carbon dioxide drying.

[0051] In some embodiments, after forming the encapsulation glue layer 6, the following operations are further included: A graphene coating is applied to the surface of the heat conduction layer 2 exposed on the surface of the encapsulation glue layer 6 and the surface of the encapsulation glue layer 6, and cured to obtain a graphene coating 7.

[0052] The present invention is further illustrated by the following examples.

[0053] Example 1 This example is used to illustrate the preparation method of the substrate chip packaging structure disclosed by the present invention, including the following operation steps: 1). Preparation of the heat conduction layer: A copper layer is used as the substrate, and grid-shaped grooves are etched on one side surface of the copper layer by laser etching; The other side surface of the copper layer is protected by a mask, and the copper layer is placed in a nitric acid solution for activation treatment, and then washed with water; The activated copper layer is used as the cathode and placed in an electroplating solution for electroplating treatment, and a cluster-shaped nickel layer is formed on one side surface of the copper layer and in the grid-shaped grooves. The electroplating solution includes the following components: Nickel chloride 3g / L, ammonium chloride 50g / L; The current density of the electroplating treatment is 15A / dm 2 ; After the electroplating treatment, the cluster-shaped nickel layer is subjected to plasma hydroxylation treatment; The mask of the copper layer is removed, the copper layer is folded with the cluster-shaped nickel layer as the inner side, and the edge of the copper layer is initially welded by laser welding and the liquid injection port is reserved. The liquid injection port is evacuated and ethanol is injected, and the liquid injection port is secondarily welded to form a sealed cavity filled with ethanol inside the copper layer.

[0054] 2). Preparation of the aerogel layer: Tetraethyl orthosilicate, ethanol, and water are mixed at a molar ratio of 1:10:5, hydrochloric acid is added to adjust the pH value to 4, and stirred at 50°C for 400 min to obtain silica sol; Add ammonia water and titanium dioxide, adjust the pH value of the silica sol to 7, mix the silica sol with the glass fiber layer to obtain a gel layer; Subject the gel layer to hydrophobic modification in a hydrophobic modification liquid, the hydrophobic modification liquid includes ethanol and hexamethyldisilazane, wherein the mass percentage of hexamethyldisilazane is 5%, and the rest is ethanol; Dry the hydrophobic-modified gel layer to obtain an aerogel layer.

[0055] 3), Preparation of the substrate chip packaging structure Embed the control chip into the groove on one surface of the substrate, and attach a first temperature sensor to the side wall of the control chip; Cover the surface of the control chip and the substrate with a heat conduction layer; Place the aerogel layer on the side of the heat conduction layer away from the control chip; Weld the interposer to the surface of the substrate through connecting solder balls, and clamp and fix the heat conduction layer and the aerogel layer; After arranging multiple storage chips in a stepped staggered stack, place them on the top surface of the interposer, and attach a second temperature sensor to the side wall of the storage chip; Use encapsulation glue to encapsulate the control chip, storage chip, aerogel layer, heat conduction layer and interposer to form an encapsulation glue layer. At the same time, part of the heat conduction layer is exposed from the encapsulation glue layer; Coat the surface of the heat conduction layer exposed from the encapsulation glue layer and the surface of the encapsulation glue layer with graphene coating, and cure to obtain a graphene coating.

[0056] Example 2 This example is used to illustrate the preparation method of the substrate chip packaging structure disclosed in the present invention, including most of the operation steps in Example 1, the difference is: In step 1), the electroplating operation of the cluster nickel layer and the plasma hydroxylation treatment are not carried out.

[0057] Example 3 This example is used to illustrate the preparation method of the substrate chip packaging structure disclosed in the present invention, including most of the operation steps in Example 1, the difference is: In step 1), the plasma hydroxylation treatment is not carried out.

[0058] Example 4 This example is used to illustrate the preparation method of the substrate chip packaging structure disclosed in the present invention, including most of the operation steps in Example 1, the difference is: In step 3), the coating operation of the graphene coating is not carried out.

[0059] Comparative Example 1 This comparative example is used to compare and illustrate the preparation method of the substrate chip packaging structure disclosed in the present invention, including most of the operation steps in Example 1. The differences are as follows: Step 1) is not carried out; In step 3), the heat-conducting layer is not added, and the aerogel layer is directly arranged on the top surface of the control chip.

[0060] Comparative Example 2 This comparative example is used to compare and illustrate the preparation method of the substrate chip packaging structure disclosed in the present invention, including most of the operation steps in Example 1. The differences are as follows: Step 2) is not carried out; In step 3), the aerogel layer is not added, and the interposer is directly arranged on the top surface of the heat-conducting layer.

[0061] Performance Test The following performance tests are carried out on the prepared substrate chip packaging structure: Connect the substrate chip packaging structure to a power supply and an external control device, perform the same read and write operations on the substrate chip packaging structure. After 1 h, the surface temperatures of the control chip and the storage chip are respectively detected by the first temperature sensor and the second temperature sensor, and the obtained test results are filled in Table 1.

[0062] Table 1 It can be seen from the test results in Table 1 that by using the packaging structure provided by the present invention, the heat conduction efficiency between the internal chip and the external environment can be significantly improved, thereby enhancing the cooling effect on the storage chip and the control chip. This design can effectively prevent the performance of the chip from being affected due to excessive internal temperature during operation, which has a positive significance for extending the service life of the chip. At the same time, the packaging structure provided by the present invention can effectively reduce the heat conduction from the control chip to the storage chip.

[0063] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A substrate chip packaging structure, characterized in that, It includes a substrate, a control chip, a memory chip, a heat conduction layer, an aerogel layer, an intermediate sheet and a packaging adhesive layer. A groove is formed on one side surface of the substrate. The control chip is embedded in the groove. The heat conduction layer covers the surfaces of the control chip and the substrate. A cavity is formed inside the heat conduction layer. A capillary structure is formed on the inner wall of the cavity. A phase change working fluid is filled in the cavity. The aerogel layer is located on one side of the heat conduction layer away from the control chip. The intermediate sheet is located on one side of the aerogel layer away from the heat conduction layer. The memory chip is located on one side of the intermediate sheet away from the aerogel layer. The packaging adhesive layer is arranged on the substrate. The control chip, the memory chip, the aerogel layer and the intermediate sheet are all located inside the packaging adhesive layer. A part of the heat conduction layer is located inside the packaging adhesive layer, and a part of the heat conduction layer extends and exposes outside the packaging adhesive layer.

2. The substrate chip package structure according to claim 1, wherein The number of the memory chips is multiple. The multiple memory chips are arranged in a stepped and staggered manner. Step surfaces are respectively formed on one side of the multiple memory chips. At least one first pad is arranged at the position of the step surface of the memory chip. The first pads between two adjacent memory chips are connected to each other through a first lead. At least one second pad is arranged on one side surface of the intermediate sheet away from the aerogel layer. At least one second pad and at least one first pad are connected to each other through a second lead. A third pad is arranged on the other side surface of the intermediate sheet corresponding to the second pad. The second pad is electrically connected to the third pad. A connection solder ball is arranged between the third pad and the substrate for electrical connection.

3. The substrate chip package structure according to claim 2, wherein The substrate includes a hollowed-out substrate and multiple bottom substrates. The multiple bottom substrates are stacked. The hollowed-out substrate is stacked on the top bottom substrate. The hollowed-out substrate is hollowed out at the position corresponding to the control chip to form the groove. A first circuit pattern is arranged on the surface of the bottom substrate. A second circuit pattern is arranged on the bottom surface of the hollowed-out substrate. A fourth pad is arranged on the top surface of the hollowed-out substrate at the position where the heat conduction layer is not covered. The connection solder balls respectively connect the third pad and the fourth pad. A welding end point is arranged on the bottom surface of the control chip. Multiple first metallized vias are arranged in the bottom substrate. The first circuit pattern, the second circuit pattern and the welding end point are electrically connected through the first metallized vias. Multiple second metallized vias are arranged inside the hollowed-out substrate. The second metallized vias are used for electrically connecting the second circuit pattern and the fourth pad.

4. The substrate chip package structure according to claim 1, wherein, The aerogel layer includes silica aerogel, inorganic particles and a glass fiber layer located in the silica aerogel.

5. The substrate chip package structure according to claim 1, wherein The heat conduction layer is a copper layer. A grid-shaped groove is formed on the inner wall of the cavity. The capillary structure is located inside the inner wall of the cavity and the grid-shaped groove. The capillary structure is a cluster-shaped nickel layer. The boiling point of the phase change working fluid is 40~90°C.

6. The substrate chip package structure according to claim 1, wherein, The surface of the heat conduction layer exposed outside the packaging adhesive layer and the surface of the packaging adhesive layer are covered with a graphene coating.

7. The manufacturing method of the substrate chip packaging structure according to any one of claims 1 to 6, characterized in that, The following operations are included: Embed the control chip in the groove on one side surface of the substrate; Covering the surfaces of the control chip and the substrate with a heat-conducting layer; An aerogel layer is placed on the side of the heat conductive layer facing away from the control chip; The intermediate sheet is welded to the surface of the substrate, and the heat conductive layer and the aerogel layer are clamped and fixed; placing a memory chip on the top surface of the interposer; The control chip, the memory chip, the aerogel layer, the heat-conducting layer and the intermediate chip are encapsulated by using encapsulating glue to form an encapsulating glue layer, and at the same time, the heat-conducting layer is partially exposed from the encapsulating glue layer.

8. The manufacturing method of the substrate chip package structure according to claim 7, characterized in that, The preparation method of the thermal conductive layer comprises the following operations: A copper layer is used as a substrate, and grid-shaped grooves are etched on one surface of the copper layer by laser etching; The other side of the copper layer is protected by masking, and the copper layer is placed in a nitric acid solution for activation treatment, and then washed with water; The activated copper layer is placed in an electroplating solution as a cathode for electroplating, and a clustered nickel layer is formed on one side surface of the copper layer and in the grid-shaped grooves. The electroplating solution includes the following components: Nickel salt 2-5 g / L, ammonium salt 40-80 g / L; The current density of the electroplating treatment is 12 - 20 A / dm 2 ; After the electroplating treatment, the clustered nickel layer is subjected to plasma hydroxylation treatment; The mask of the copper layer is removed, and the copper layer is folded with the clustered nickel layer as the inner side. The edge of the copper layer is initially welded by laser welding and the injection port is retained. The injection port is evacuated and the phase change working fluid is injected. The injection port is welded for a second time to form a closed cavity filled with the phase change working fluid inside the copper layer.

9. The manufacturing method of the substrate chip package structure according to claim 7, characterized in that, The preparation method of the aerogel layer comprises the following operations: Mix ethyl orthosilicate, ethanol and water in a molar ratio of 1:(7-20):(3-8), add acid to adjust the pH value to 2-6, and stir at 40-80°C for 200-500 minutes to obtain silica sol; Ammonia water and inorganic particles are added to adjust the pH value of the silica sol to 6.5-8, and the silica sol is mixed with the glass fiber layer to obtain a gel layer; The gel layer is placed in a hydrophobic modification liquid for hydrophobic modification, wherein the hydrophobic modification liquid comprises ethanol and hexamethyldisilazane, wherein the mass percentage of hexamethyldisilazane is 1% to 10%; The hydrophobically modified gel layer is dried to obtain an aerogel layer.

10. The manufacturing method of the substrate chip packaging structure according to claim 7, characterized in that, After forming the encapsulation glue layer, the following operations are also included: A graphene coating is coated on the surface of the heat-conducting layer exposed from the packaging adhesive layer and on the surface of the packaging adhesive layer, and is cured to obtain a graphene coating.

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