Gate drive circuit
By using the level displacement, buffering, pull-down and push-pull modules designed by the 4H-SiC enhanced NMOS tube in the gate driving circuit, the problem of poor stability of the silicon-based gate driving circuit at high temperatures is solved, and long-term stable operation and high-performance power module applications are realized.
Patent Information
- Application Number
- CN202510178131.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-18
- Publication Date
- 2025-07-08
AI Technical Summary
The existing silicon-based gate driving circuits are difficult to operate stably for a long time under high temperature conditions. The process maturity between silicon carbide devices is large, resulting in large performance differences, and it is difficult to apply as switching devices to gate driving circuits to improve high-temperature operation stability.
The level displacement module, high-side buffer module, low-side buffer module, pull-down module and push-pull module are designed using 4H-SiC enhanced NMOS tube. By optimizing the inverter unit and power supply voltage design, the reliability and stability of the module in high-temperature environment are improved.
It realizes the long-term stable operation of the gate driving circuit in high temperature state, improves driving capacity and switching speed, reduces parasitic capacitance inductance, and is suitable for high-performance power modules in hybrid electric vehicles and traction drive systems.
Smart Images
Figure CN120281302A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular, to a gate driving circuit. Background Art
[0002] The gate driving circuit based on the existing silicon (Si)-based devices is difficult to operate stably for a long time at high temperatures. Although silicon carbide (SiC) devices have many obvious advantages, since SiC devices are mainly used as power devices, the design emphasis of their processes is different, resulting in a large difference in the process maturity between different SiC devices (such as P-type SiC devices, N-type SiC devices, enhancement-mode SiC devices, and depletion-mode SiC devices), so that the performance differences between different SiC devices are large, and it is difficult to be used as a switching device in the gate driving circuit to improve its operating stability at high temperatures.
[0003] In summary, there is a need to provide a gate driving circuit that can operate stably for a long time at high temperatures. Summary of the Invention
[0004] To solve the above problems, the present application provides a gate driving circuit, including: a level shift module, a high-side buffer module, a low-side buffer module, a pull-down module, and a push-pull module; the level shift module, the high-side buffer module, the low-side buffer module, the pull-down module, and the push-pull module all include 4H-SiC enhancement-mode NMOS transistors.
[0005] One end of the level shift module is connected to the input voltage signal terminal, and the other end is connected to the high-side buffer module.
[0006] The other end of the high-side buffer module is connected to the first end of the pull-down module.
[0007] One end of the low-side buffer module is connected to the power supply terminal, and the other end is connected to the second end of the pull-down module.
[0008] The third end of the pull-down module is connected to the first end of the push-pull module, and the second end is also connected to the second end of the push-pull module.
[0009] Preferably, the pull-down module includes: a first resistor and a first NMOS transistor; wherein, the first NMOS transistor is the 4H-SiC enhancement-mode NMOS transistor.
[0010] One end of the first resistor is connected to the high-side buffer module, and the other end is connected to the drain of the first NMOS transistor and the first end of the push-pull module.
[0011] The gate of the first NMOS transistor is connected to the low-side buffer module and the second end of the push-pull module, and the source is connected to the ground terminal.
[0012] Preferably, the level shift module includes: a second NMOS transistor, a third NMOS transistor, and a second resistor; wherein, the second NMOS transistor and the third NMOS transistor are 4H-SiC enhancement-mode NMOS transistors;
[0013] The source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the drain is connected to one end of the second resistor and the high-side buffer module, and the gate is connected to the first power supply voltage terminal;
[0014] The gate of the third NMOS transistor is connected to the input voltage signal terminal, and the source is connected to the ground terminal;
[0015] The other end of the second resistor is connected to the second power supply voltage terminal.
[0016] Preferably, the level shift module further includes: a first diode; the cathode of the first diode is connected to the drain of the second NMOS transistor, and the anode is connected to the first power supply voltage terminal.
[0017] Preferably, the low-side buffer module includes: three series-connected low-side inverter units.
[0018] Preferably, one low-side inverter unit includes: a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all 4H-SiC enhancement-mode NMOS transistors;
[0019] The gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, the sources of the fourth NMOS transistor and the fifth NMOS transistor are both connected to the ground terminal, the drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, and the gate of the fourth NMOS transistor is the input terminal of the low-side inverter unit;
[0020] The drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor, and the drain of the fifth NMOS transistor is the output terminal of the low-side inverter unit;
[0021] The gate of the sixth NMOS transistor is connected to the first power supply voltage terminal, and the drain is connected to the gate of the seventh NMOS transistor and the source of the eighth NMOS transistor;
[0022] The drain of the seventh NMOS transistor is connected to the first power supply voltage terminal, and the gates and drains of the eighth NMOS transistors are both connected to the second power supply voltage terminal.
[0023] Preferably, the high-side buffer module includes: three serially connected high-side inverter units.
[0024] Preferably, one of the high-side inverter units includes: a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor; the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are all 4H-SiC enhancement-mode NMOS transistors;
[0025] The gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, the sources of the ninth NMOS transistor and the tenth NMOS transistor are both connected to the first power supply voltage terminal, the drain of the ninth NMOS transistor is connected to the source of the eleventh NMOS transistor, and the gate of the ninth NMOS transistor is the input terminal of the high-side inverter unit;
[0026] The drain of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor, and the drain of the tenth NMOS transistor is the output terminal of the high-side inverter unit;
[0027] The gate of the eleventh NMOS transistor is connected to the second power supply voltage terminal, and the drain is connected to the gate of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor;
[0028] The drain of the twelfth NMOS transistor is connected to the second power supply voltage terminal, and the gates and drains of the thirteenth NMOS transistor are both connected to the third power supply voltage terminal.
[0029] Preferably, the output voltage of the second power supply voltage terminal is twice the output voltage of the first power supply voltage terminal; the output voltage of the third power supply voltage terminal is three times the output voltage of the first power supply voltage terminal.
[0030] Preferably, the push-pull module includes: a fourteenth NMOS transistor and a fifteenth NMOS transistor; the fourteenth NMOS transistor and the fifteenth NMOS transistor are 4H-SiC enhancement-mode NMOS transistors;
[0031] The gate of the fourteenth NMOS transistor is connected to the third terminal of the pull-down module, the source is connected to the drain of the fifteenth NMOS transistor, the drain is connected to the first power supply voltage terminal, and the drain of the fourteenth NMOS transistor is the output voltage signal terminal;
[0032] The gate of the fifteenth NMOS transistor is connected to the second end of the pull-down module, and the source is connected to the ground terminal.
[0033] The advantages of this application are as follows: By using 4H-SiC enhancement-mode NMOS transistors, the reliability and stability of the level-shifting module, high-side buffer module, low-side buffer module, pull-down module, and push-pull module in a high-temperature environment are improved, enabling the gate drive circuit to operate stably for a long time at high temperatures. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of this application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:
[0035] Figure 1 is a schematic diagram of a gate drive circuit provided by this application;
[0036] Figure 2 is a schematic diagram of the pull-down module and push-pull module of a gate drive circuit provided by this application;
[0037] Figure 3 is a schematic diagram of the low-side inverter unit of a gate drive circuit provided by this application;
[0038] Figure 4 is a schematic diagram of the high-side inverter unit of a gate drive circuit provided by this application;
[0039] Figure 5 is a schematic diagram of the pull-down structure of a gate drive circuit provided by this application;
[0040] Figure 6 is a schematic diagram of the level-shifting module of a gate drive circuit provided by this application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0041] Hereinafter, the exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully communicated to those skilled in the art.
[0042] Compared with Si-based structures, silicon carbide (SiC) devices have many obvious advantages, including higher operating voltages, higher thermal conductivities, and higher junction operating temperatures. These characteristics make SiC devices functionally suitable for compact high-performance power modules, including power inverters and traction drive systems for hybrid electric vehicles.
[0043] Designing a SiC-based drive circuit integrated with SiC power devices can, on the one hand, reduce the parasitic capacitance and inductance brought by leads and improve the power conversion efficiency. On the other hand, it can directly enable the drive circuit and the driven SiC power devices to work together in a high-temperature (greater than 150 °C) and high-irradiation environment. Compared with Si-based drive circuits, there is no need for excessive isolation and protection.
[0044] However, although significant progress has been made in SiC CMOS structures, since SiC MOS has mainly been used as a power device, many contemporary SiC designs focus on NMOS-based designs. The more mature process makes SiC NMOS perform better than PMOS in terms of temperature bias instability and gate oxide reliability at high temperatures. However, since the gate drive circuit requires many different switching devices to control the switching of the circuit between conduction and turn-off (disconnection), different NMOS and PMOS transistors are usually used simultaneously. Therefore, when using SiC PMOS transistors, the performance of the gate drive circuit operating at high temperatures will decrease, which is a problem that needs to be solved currently.
[0045] Embodiments of the present application design the level shift module 100, high-side buffer module 200, low-side buffer module 300, pull-down module 400, and push-pull module 500, so that all the MOS transistors in the gate drive circuit are 4H-SiC enhancement-mode MOS transistors, thereby achieving higher stability under high-temperature and long-term operating conditions.
[0046] Embodiments of the present application propose a gate drive circuit, as Figure 1 shown, including: a level shift module 100, a high-side buffer module 200, a low-side buffer module 300, a pull-down module 400, and a push-pull module 500; the level shift module 100, high-side buffer module 200, low-side buffer module 300, pull-down module 400, and push-pull module 500 all include 4H-SiC enhancement-mode NMOS transistors. One end of the level shift module 100 is connected to the input voltage signal terminal IN, and the other end is connected to the high-side buffer module 200; the other end of the high-side buffer module 200 is connected to the first end of the pull-down module 400; one end of the low-side buffer module 300 is connected to the power supply terminal, and the other end is connected to the second end of the pull-down module 400; the third end of the pull-down module 400 is connected to the first end of the push-pull module 500, and the second end is also connected to the second end of the push-pull module 500.
[0047] The pull-down module 400 of the embodiment of the present application can form a pull-down structure at the gate potential of the high-side output transistor (the fourteenth NMOS transistor M14). The level shift module 100 can convert the 0-20V low-voltage square wave signal input from the input voltage signal terminal IN into a 20-40V high-voltage signal; both the high-side buffer module 200 and the low-side buffer module 300 are composed of three specially designed inverters connected in series, and the sizes of the three inverters increase gradually to improve the driving ability; the push-pull module 500 outputs a signal to drive the load, and at the same time, the pull-down module 400 ensures that the high-side NMOS (the fourteenth NMOS transistor M14) of the output stage is normally turned off and avoids the generation of punch-through current damage to the circuit due to the simultaneous conduction of the upper and lower transistors (the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15).
[0048] As Figure 2 shown, the push-pull module 500 includes: the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15; the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15 are 4H-SiC enhancement-mode NMOS transistors. The gate of the fourteenth NMOS transistor M14 is connected to the third terminal of the pull-down module 400, the source is connected to the drain of the fifteenth NMOS transistor M15, the drain is connected to the first power supply voltage terminal VDD, and the drain of the fourteenth NMOS transistor M14 is the output voltage signal terminal OUT. The gate of the fifteenth NMOS transistor M15 is connected to the second terminal of the pull-down module 400, and the source is connected to the ground terminal GND.
[0049] Among them, the output voltage signal terminal OUT is connected to the load.
[0050] As Figure 2 shown, the pull-down module 400 includes: the first resistor R1 and the first NMOS transistor M1; among them, the first NMOS transistor M1 is a 4H-SiC enhancement-mode NMOS transistor.
[0051] One end of the first resistor R1 is connected to the high-side buffer module 200, and the other end is connected to the drain of the first NMOS transistor M1 and the first terminal of the push-pull module 500. The gate of the first NMOS transistor M1 is connected to the low-side buffer module 300 and the second terminal of the push-pull module 500, and the source is connected to the ground terminal GND.
[0052] The low-side buffer module 300 includes: three series-connected low-side inverter units.
[0053] As Figure 3As shown, a low-side inverter unit includes: a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, and an eighth NMOS transistor M8; the fourth NMOS transistor M4, the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, and the eighth NMOS transistor M8 are all 4H-SiC enhancement-mode NMOS transistors.
[0054] The gate of the fourth NMOS transistor M4 is connected to the gate of the fifth NMOS transistor M5. The source of the fourth NMOS transistor M4 and the source of the fifth NMOS transistor M5 are both connected to the ground terminal GND. The drain of the fourth NMOS transistor M4 is connected to the source of the sixth NMOS transistor M6. The gate of the fourth NMOS transistor M4 is the input terminal of the low-side inverter unit. The drain of the fifth NMOS transistor M5 is connected to the source of the seventh NMOS transistor M7. The drain of the fifth NMOS transistor M5 is the output terminal of the low-side inverter unit. The gate of the sixth NMOS transistor M6 is connected to the first power supply voltage terminal VDD. The drain is connected to the gate of the seventh NMOS transistor M7 and the source of the eighth NMOS transistor M8. The drain of the seventh NMOS transistor M7 is connected to the first power supply voltage terminal VDD. The gate and the drain of the eighth NMOS transistor M8 are both connected to the second power supply voltage terminal 2VDD.
[0055] Among them, the IN_L terminal is the input terminal of the low-side inverter unit, and the OUT_L terminal is the output terminal of the low-side inverter unit.
[0056] The high-side buffer module 200 includes: three serially connected high-side inverter units.
[0057] As Figure 4 shown, a high-side inverter unit includes: a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13; the ninth NMOS transistor M9, the tenth NMOS transistor M10, the eleventh NMOS transistor M11, the twelfth NMOS transistor M12, and the thirteenth NMOS transistor M13 are all 4H-SiC enhancement-mode NMOS transistors.
[0058] The gate of the ninth NMOS transistor M9 is connected to the gate of the tenth NMOS transistor M10. The sources of the ninth NMOS transistor M9 and the tenth NMOS transistor M10 are both connected to the first power supply voltage terminal VDD. The drain of the ninth NMOS transistor M9 is connected to the source of the eleventh NMOS transistor M11. The gate of the ninth NMOS transistor M9 is the input terminal of the high-side inverter unit. The drain of the tenth NMOS transistor M10 is connected to the source of the twelfth NMOS transistor M12. The drain of the tenth NMOS transistor M10 is the output terminal of the high-side inverter unit. The gate of the eleventh NMOS transistor M11 is connected to the second power supply voltage terminal 2VDD, and the drain is connected to the gate of the twelfth NMOS transistor M12 and the source of the thirteenth NMOS transistor M13. The drain of the twelfth NMOS transistor M12 is connected to the second power supply voltage terminal 2VDD. The gate and drain of the thirteenth NMOS transistor M13 are both connected to the third power supply voltage terminal 3VDD.
[0059] Among them, the IN_H terminal is the input terminal of the high-side inverter unit, and the OUT_H terminal is the output terminal of the high-side inverter unit.
[0060] The output voltage of the second power supply voltage terminal 2VDD is twice the output voltage of the first power supply voltage terminal VDD; the output voltage of the third power supply voltage terminal 3VDD is three times the output voltage of the first power supply voltage terminal VDD.
[0061] The power supply voltages applied to the high-side inverter unit and the low-side inverter unit are different. Now, taking the low-side inverter unit as an example, it will be further described.
[0062] Since multiple inverters will be connected in series later, it is very important to improve the noise margin of a single inverter for the stable operation of the inverter chain. Compared with a simple diode-loaded inverter, a pre-stage circuit composed of the fourth NMOS transistor M4, the sixth NMOS transistor M6, and the eighth NMOS transistor M8 and an external power supply of 40V (output through the second power supply voltage terminal 2VDD) are added, thus solving the problem that the output high level of the diode-loaded inverter can only reach VDD - VGS14 (0 to 14V). At room temperature, the threshold voltage of the N-type SiC MOS is about 6V. When the output is close to the high level, an over-drive voltage of about 8V can still be provided for the upper transistor (the seventh NMOS transistor M7) of the output transistor. Since the over-drive voltage will increase as the temperature rises, the pulling-up ability of the upper transistor, that is, the seventh NMOS transistor M7, is ensured. The gate voltage applied to the sixth NMOS transistor M6 is 20V, and its function is the same as that of the second NMOS transistor M2 inserted in the level-shifting circuit.
[0063] The high-side buffer module 200 is composed of three such high-side inverter units with gradually increasing sizes (width-to-length ratios) connected in series.
[0064] Meanwhile, to prevent the gate voltages of some MOS transistors in the high-side buffer module 200 from exceeding 20V during operation after the high-side power supply voltage is increased to 40V and 60V, which may affect the reliability of the gate oxide, the potential of the "ground" terminal of the inverter used in the high-side circuit is 20V (output through the first power supply voltage terminal VDD). At the same time, to ensure that the upper transistor of the output stage, the fourteenth NMOS transistor M14, can be turned off normally and the output potential can be quickly pulled down to ground, a pull-down structure composed of the first NMOS transistor M1 and the first resistor R1 is added. When the low-side buffer module 300 outputs a high level, the first NMOS transistor M1 is turned on. At this time, the first NMOS transistor M1, the first resistor R1, and the tenth NMOS transistor M10 in the last-stage high-side inverter unit in the high-side buffer module 200 form a pull-down structure as shown in Figure 5 That is, the tenth NMOS transistor M10 with its gate-source shorted becomes a clamping diode with a conduction voltage drop of about 0.7V, causing the gate voltage of the fourteenth NMOS transistor M14 to be clamped. At this time, the first resistor R1 is added, and the voltage drop across the first resistor R1 is used to lower the gate voltage of the fourteenth NMOS transistor M14 to 0V. At the same time, due to the addition of a level-shifting structure (level-shifting module 100) and the first resistor R1 in the high-side circuit, there is a small delay in the signal transmission compared to the lower transistor (the fifteenth NMOS transistor M15). When the input signal jumps from a high level to a low level, the turn-on signal of the lower transistor (the fifteenth NMOS transistor M15) will be slightly faster than the turn-off signal of the upper transistor (the fourteenth NMOS transistor M14). At this time, this pull-down structure can also turn on the first NMOS transistor M1 when the turn-on signal of the fifteenth NMOS transistor M15 arrives, thereby turning off the fourteenth NMOS transistor M14. This can improve the switching efficiency and prevent the simultaneous conduction of the fourteenth NMOS transistor M14 and the fifteenth NMOS transistor M15, which may damage the circuit due to a through-circuit.
[0065] As shown in Figure 6 the level-shifting module 100 includes: a second NMOS transistor M2, a third NMOS transistor M3, and a second resistor R2. Among them, the second NMOS transistor M2 and the third NMOS transistor M3 are 4H-SiC enhancement-mode NMOS transistors.
[0066] The source of the second NMOS transistor M2 is connected to the drain of the third NMOS transistor M3, the drain is connected to one end of the second resistor R2 and the high-side buffer module 200, and the gate is connected to the first power supply voltage terminal VDD. The gate of the third NMOS transistor M3 is connected to the input voltage signal terminal IN, and the source is connected to the ground terminal GND;
[0067] The other end of the second resistor R2 is connected to the second power supply voltage terminal 2VDD.
[0068] Among them, the power supply voltage output by the first power supply voltage terminal VDD is 20V.
[0069] As Figure 2 shown, the level shift module 100 further includes: a first diode D1; the cathode of the first diode D1 is connected to the drain of the second NMOS transistor M2, and the anode is connected to the first power supply voltage terminal VDD.
[0070] Among them, the first diode D1 is a clamping diode.
[0071] The level shift module 100 can boost an input voltage signal of 0 to 20V to 20 to 40V at room temperature. On the basis of a conventional level shift circuit, the level shift module 100 inserts a second NMOS transistor M2 between the third NMOS transistor M3 and the output, and applies a gate voltage of 20V to the second NMOS transistor M2, so as to avoid excessive gate-drain voltage in the off state of the third NMOS transistor M3 by making the third NMOS transistor M3 and the second NMOS transistor M2 "share" the 40V voltage drop equally.
[0072] At high temperatures, the threshold voltage of the SiC MOS transistor decreases, the channel carrier mobility increases, and the current-carrying capacity of the switching transistor increases. The boosted low level will be lower than 20V, which does not affect the normal switching of the high-side inverter unit in the subsequent high-side buffer module 200, but will cause the gate-source voltage difference of one of the MOS transistors (the eleventh NMOS transistor M11) to exceed 20V, affecting the reliability. Therefore, at the output, the first diode D1 serves as a clamping diode, and the conduction voltage drop of the first diode D1 is about 0.5V to limit the lowest level.
[0073] In the embodiments of the present application, the circuit connection is simple, and all MOS transistors are 4H-SiC enhancement-mode NMOS. The reliability and stability of the level shift module, the high-side buffer module, the low-side buffer module, the pull-down module, and the push-pull module in a high-temperature environment are improved by 4H-SiC enhancement-mode NMOS transistors, enabling the gate drive circuit to operate stably for a long time at high temperatures. Considering that the SiC MOS transistor is affected by mobility and has a weak current-carrying capacity, in order for the gate drive circuit to drive a large load and achieve a fast switching speed, the embodiments of the present application apply a sufficient overdrive voltage when each switching transistor (NMOS transistor) is turned on, thereby improving the driving ability. Since the degradation rate of the gate oxide of the SiC MOS transistor will increase with the increase of the gate voltage, and the risk of gate oxide breakdown will also increase, therefore, the embodiments of the present application ensure that the maximum gate voltage during the operation of each switching transistor does not exceed 20V, thereby improving the reliability. All MOS transistors in the embodiments of the present application are N-type MOS transistors based on 4H-SiC enhancement-mode CMOS process. The gate drive circuit composed of them has high reliability and can maintain high driving ability and operating stability in a wide temperature range.
[0074] As described above, it is only the preferred specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the said claims.
Claims
1. A gate driving circuit, characterized in that, Including: A level shift module, a high-side buffer module, a low-side buffer module, a pull-down module, and a push-pull module; the level shift module, the high-side buffer module, the low-side buffer module, the pull-down module, and the push-pull module all include 4H-SiC enhancement-mode NMOS transistors; One end of the level shift module is connected to the input voltage signal terminal, and the other end is connected to the high-side buffer module; The other end of the high-side buffer module is connected to the first end of the pull-down module; One end of the low-side buffer module is connected to the power supply terminal, and the other end is connected to the second end of the pull-down module; The third end of the pull-down module is connected to the first end of the push-pull module, and the second end is also connected to the second end of the push-pull module.
2. The gate driving circuit according to claim 1, wherein The pull-down module includes: a first resistor and a first NMOS transistor; wherein, the first NMOS transistor is the 4H-SiC enhancement-mode NMOS transistor; One end of the first resistor is connected to the high-side buffer module, and the other end is connected to the drain of the first NMOS transistor and the first end of the push-pull module; The gate of the first NMOS transistor is connected to the low-side buffer module and the second end of the push-pull module, and the source is connected to the ground terminal.
3. The gate driving circuit according to claim 1, characterized in that, The level shift module includes: a second NMOS transistor, a third NMOS transistor, and a second resistor; wherein, the second NMOS transistor and the third NMOS transistor are the 4H-SiC enhancement-mode NMOS transistors; The source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the drain is connected to one end of the second resistor and the high-side buffer module, and the gate is connected to the first power supply voltage terminal; The gate of the third NMOS transistor is connected to the input voltage signal terminal, and the source is connected to the ground terminal; The other end of the second resistor is connected to the second power supply voltage terminal.
4. The gate driving circuit according to claim 3, characterized in that, The level shift module further includes: a first diode; the cathode of the first diode is connected to the drain of the second NMOS transistor, and the anode is connected to the first power supply voltage terminal.
5. The gate driving circuit according to claim 1, characterized in that The low-side buffer module includes: three series-connected low-side inverter units.
6. The gate driving circuit according to claim 5, wherein One low-side inverter unit includes: a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all the 4H-SiC enhancement-mode NMOS transistors; The gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are both connected to the ground terminal, the drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, and the gate of the fourth NMOS transistor is the input terminal of the low-side inverter unit; The drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor, and the drain of the fifth NMOS transistor is the output terminal of the low-side inverter unit; The gate of the sixth NMOS transistor is connected to the first power supply voltage terminal, and the drain is connected to the gate of the seventh NMOS transistor and the source of the eighth NMOS transistor; The drain of the seventh NMOS transistor is connected to the first power supply voltage terminal, and the gate and drain of the eighth NMOS transistor are both connected to the second power supply voltage terminal.
7. The gate driving circuit according to claim 1, wherein The high-side buffer module includes: three serially connected high-side inverter units.
8. The gate driving circuit according to claim 7, wherein One high-side inverter unit includes: a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor; the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are all 4H-SiC enhancement-mode NMOS transistors; The gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, the source of the ninth NMOS transistor and the source of the tenth NMOS transistor are both connected to the first power supply voltage terminal, the drain of the ninth NMOS transistor is connected to the source of the eleventh NMOS transistor, and the gate of the ninth NMOS transistor is the input terminal of the high-side inverter unit; The drain of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor, and the drain of the tenth NMOS transistor is the output terminal of the high-side inverter unit; The gate of the eleventh NMOS transistor is connected to the second power supply voltage terminal, and the drain is connected to the gate of the twelfth NMOS transistor and the source of the thirteenth NMOS transistor; The drain of the twelfth NMOS transistor is connected to the second power supply voltage terminal, and the gate and drain of the thirteenth NMOS transistor are both connected to the third power supply voltage terminal.
9. The gate driving circuit according to claim 8, wherein The output voltage of the second power supply voltage terminal is twice the output voltage of the first power supply voltage terminal; the output voltage of the third power supply voltage terminal is three times the output voltage of the first power supply voltage terminal.
10. The gate driving circuit according to claim 1, wherein The push-pull module includes: a fourteenth NMOS transistor and a fifteenth NMOS transistor; the fourteenth NMOS transistor and the fifteenth NMOS transistor are 4H-SiC enhancement-mode NMOS transistors; The gate of the fourteenth NMOS transistor is connected to the third terminal of the pull-down module, the source is connected to the drain of the fifteenth NMOS transistor, the drain is connected to the first power supply voltage terminal, and the drain of the fourteenth NMOS transistor is the output voltage signal terminal; The gate of the fifteenth NMOS transistor is connected to the second terminal of the pull-down module, and the source is connected to the ground terminal.