Low-crosstalk high-isolation multi-choice video switch circuit
Through the combination of T-switch and channel selection control circuit, the problem of low isolation at high frequencies of traditional CMOS analog switches is solved, and a video switching circuit with low crosstalk and high isolation is realized, which is suitable for high-frequency signal transmission.
Patent Information
- Application Number
- CN202510556631.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-07-08
AI Technical Summary
Traditional CMOS analog switches have low isolation at high frequencies, resulting in serious signal crosstalk, affecting system accuracy and visual experience.
It adopts a T-type switch structure, consisting of complementary T-type PMOS and NMOS switches, and combines with a channel selection control circuit to generate a non-overlapping clock control signal, ensuring that each switch is independently turned on within different time periods, reducing parasitic capacitive coupling.
It improves the switch off isolation, reduces signal crosstalk, ensures full signal transmission and no level loss, and is suitable for high-frequency application scenarios.
Smart Images
Figure CN120281857A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of analog circuits, and particularly to a multi - select - one video switch circuit with low crosstalk and high isolation. Background Art
[0002] In many large - scale integrated circuit systems and electronic systems, high - performance analog switches are often required. Using switches, specific functions such as signal switching, control, and gating can be completed. The performance requirements for switches are: high isolation, good frequency response characteristics, wide dynamic range, and small non - linear distortion. In recent years, video analog switches have been increasingly widely used in video systems.
[0003] The structure of traditional analog switches is relatively simple. As Figure 1 shown, by paralleling an N - channel and a P - channel MOSFET, signals can flow bidirectionally. Theoretically, the on - resistance of a CMOS transmission gate is very low, and the resistance when off is as high as several thousand megohms or more. Therefore, it is often used as a non - contact bidirectional analog switch. Since the NMOS transistor has good transmission performance for low - level input signals and the PMOS transistor has good transmission performance for high - level input signals, signals can be transmitted with full amplitude without loss of level.
[0004] In modern analog switch applications, in order to obtain good linearity and high transmission frequency, a very low on - resistance is required. This means that the aspect ratio of the transistor needs to be increased during design, but this will also cause the output capacitance of the transistor to increase accordingly. When traditional CMOS analog switches are applied in some high - frequency situations, when the switch is turned off, signals will be coupled to the output through the parasitic capacitance of the MOS transistor, and this phenomenon will become more serious as the frequency increases.
[0005] As the frequency of video signals continues to increase, traditional switches cannot meet the application requirements in some performance aspects (low isolation, serious crosstalk). Especially when users are constantly pursuing a better visual experience, excellent off - state isolation can eliminate the ghosting of the display. Therefore, a new type of analog switch with higher frequency characteristics has become the main development trend. Summary of the Invention
[0006] The purpose of the present invention is to provide a multi - select - one video switch circuit with low crosstalk and high isolation to solve the problem that when the traditional CMOS analog switch is turned off, higher - frequency signals will be coupled to the output through the parasitic capacitance of the transmission MOS transistor, reducing the off - state isolation, interfering with the next - stage system, and causing errors in the system accuracy.
[0007] To solve the above - mentioned technical problems, the present invention provides a multi - select - one video switch circuit with low crosstalk and high isolation, including:
[0008] The T-type switch is composed of two complementary T-type PMOS and NMOS switches, achieving high off-state isolation.
[0009] The channel selection control circuit includes a decoder circuit and channel control switches. After the N-bit logic signal passes through the decoder circuit, one output pulse control signal is selected, and through the channel control switches, non-overlapping clock control signals are generated to control the corresponding T-type switches to conduct, realizing the selective output of video signals; the other unselected T-type switches are turned off.
[0010] In one embodiment, the T-type switch includes: NMOS transistor M0, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, PMOS transistor M5, resistor R L , capacitor C L , and two complementary switch logic control signals V1 and V2;
[0011] The source terminal of NMOS transistor M0 is grounded, the gate terminal is connected to control signal V2, and the drain terminal is simultaneously connected to the source terminals of NMOS transistor M2 and NMOS transistor M3, and this connection point is point A; the gate terminals of NMOS transistor M2 and NMOS transistor M3 are both connected to control signal V1;
[0012] The drain terminal of PMOS transistor M4 is simultaneously connected to the drain terminal of NMOS transistor M2 and signal input terminal V in , the drain terminal of PMOS transistor M5 is simultaneously connected to the drain terminal of NMOS transistor M3 and signal output terminal V out , the gate terminals of PMOS transistor M4 and PMOS transistor M5 are both connected to control signal V2, the source terminals of PMOS transistor M4 and PMOS transistor M5 are both connected to the drain terminal of NMOS transistor M1, and this connection point is point B, the gate terminal of NMOS transistor M1 is connected to control signal V2, and the source terminal is grounded;
[0013] Resistor R L 's first end is simultaneously connected to the drain terminal of NMOS transistor M3 and the drain terminal of PMOS transistor M5, and the second end is grounded;
[0014] Capacitor C L 's first end is simultaneously connected to the drain terminal of NMOS transistor M3 and the drain terminal of PMOS transistor M5, and the second end is grounded.
[0015] In one embodiment, when control signal V1 is at a high level and control signal V2 is at a low level, NMOS transistors M2, M3, PMOS transistors M4, M5 conduct, NMOS transistors M0, M1 are turned off, the switch is opened, and the signal is transmitted from input terminal V in to output terminal V out ;
[0016] When the control signal V1 is at a low level and the control signal V2 is at a high level, the NMOS transistors M2, M3, PMOS transistors M4, M5 are turned off, and the NMOS transistors M0, M1 are turned on. The levels at points A and B are pulled down to the ground, and the overall T-shaped switch is turned off. The signal from the input terminal V in cannot be transmitted to the output terminal V out ;
[0017] When the input signal frequency is high, the signal is coupled through the parasitic capacitance of the MOS itself. At this time, the NMOS transistors M0, M1 are turned on, and the coupled signal is discharged to the ground through the on-resistances of the NMOS transistors M0, M1, improving the off isolation. By using complementary T-shaped NMOS and PMOS transistors in parallel for transmission, the signal can be transmitted with full amplitude and without loss of level, reducing the on-resistance.
[0018] In one embodiment, the channel control switch includes inverters INV1 to INV7, NOR gate ONR2_1, and NOR gate ONR2_2;
[0019] The input terminal of the inverter INV1 is connected to the CLK clock signal, and the output terminal is connected to the first input terminal of the NOR gate ONR2_1. The second input terminal of the NOR gate ONR2_1 is connected to the output terminal of the inverter INV6. The output terminal of the NOR gate ONR2_1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3. The output terminal of the inverter INV3 is simultaneously connected to the input terminal of the inverter INV4 and the first input terminal of the NOR gate ONR2_2. The output terminal of the inverter INV4 outputs the CLK1 clock signal;
[0020] The second input terminal of the NOR gate ONR2_2 is connected to the CLK clock signal. The output terminal of the NOR gate ONR2_2 is connected to the input terminal of the inverter INV5. The output terminal of the inverter INV5 is connected to the input terminal of the inverter INV6. The output terminal of the inverter INV6 is connected to the input terminal of the inverter INV7. The output terminal of the inverter INV7 outputs the CLK2 clock signal;
[0021] Among them, the CLK1 clock signal and the CLK2 clock signal are non-overlapping pulse clock signals and serve as the control signals for the subsequent T-shaped switch.
[0022] A multiplexer video switch circuit with low crosstalk and high isolation provided by the present invention consists of a T-shaped switch and a channel selection control circuit. The proposed T-shaped switch is composed of two complementary T-shaped PMOS and NMOS switches, achieving high off-state isolation and overcoming the disadvantages of traditional analog switch structures with low isolation at high frequencies and signal crosstalk in multi-channel multiplexing. The proposed channel selection control circuit includes a decoder circuit and a channel control switch, which can generate non-overlapping clock control signals to select one path for video signal output, ensuring that another switch cannot be turned on before a certain switch is turned off, thus preventing signal crosstalk between channels. The correctness of the theoretical derivation is verified by actual test results. The video analog switch has stable performance and high reliability, and has broad application prospects. Description of the Drawings
[0023] Figure 1 is a schematic diagram of a traditional CMOS analog switch structure.
[0024] Figure 2 is a schematic diagram of the overall structure of the multiplexer video switch circuit with low crosstalk and high isolation provided by the present invention.
[0025] Figure 3 is a schematic diagram of the T-shaped switch structure.
[0026] Figure 4 is a schematic diagram of the channel control switch circuit.
[0027] Figure 5 is a schematic diagram of non-overlapping channel control signals. Detailed Embodiments
[0028] The following further details a multiplexer video switch circuit with low crosstalk and high isolation provided by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0029] The present invention provides a multiplexer video switch circuit with low crosstalk and high isolation, and its overall structure is as Figure 2 shown, consisting of a T-shaped switch, a decoder circuit, and a channel control switch. An N-bit logic signal can control 2 N channels of video analog signals; within a certain time period, the decoder circuit selects one path to output a pulse control signal, and through the channel control switch, non-overlapping clock control signals can be generated to control the corresponding T-shaped switch to conduct, realizing the selective output of video signals. Other unselected T-shaped switches are turned off.
[0030] Please refer to Figure 3Schematic diagram of the structure of a T-shaped switch, the structure of which includes: NMOS transistor M0, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, PMOS transistor M5, and resistor R L , capacitor C L , and two complementary switch logic control signals V1 and V2.
[0031] The source terminal of NMOS transistor M0 is grounded, the gate terminal is connected to control signal V2, and the drain terminal is simultaneously connected to the source terminals of NMOS transistor M2 and NMOS transistor M3, and this connection point is point A; the gate terminals of NMOS transistor M2 and NMOS transistor M3 are both connected to control signal V1;
[0032] The drain terminal of PMOS transistor M4 is simultaneously connected to the drain terminal of NMOS transistor M2 and signal input terminal V in , the drain terminal of PMOS transistor M5 is simultaneously connected to the drain terminal of NMOS transistor M3 and signal output terminal V out , the gate terminals of PMOS transistor M4 and PMOS transistor M5 are both connected to control signal V2, the source terminals of PMOS transistor M4 and PMOS transistor M5 are both connected to the drain terminal of NMOS transistor M1, and this connection point is point B, the gate terminal of NMOS transistor M1 is connected to control signal V2, and the source terminal is grounded; resistor R L The first end is simultaneously connected to the drain terminal of NMOS transistor M3 and the drain terminal of PMOS transistor M5, and the second end is grounded; capacitor C L The first end is simultaneously connected to the drain terminal of NMOS transistor M3 and the drain terminal of PMOS transistor M5, and the second end is grounded.
[0033] When V1 is at a high level and V2 is at a low level, NMOS transistors M2, M3, PMOS transistors M4, M5 are turned on, and NMOS transistors M0, M1 are turned off, the switch is opened, and the signal is transmitted from input terminal V in to output terminal V out .
[0034] When V1 is at a low level and V2 is at a high level, NMOS transistors M2, M3, PMOS transistors M4, M5 are turned off, and NMOS transistors M0, M1 are turned on, and the levels of point A and point B are pulled down to ground. The overall CMOS switch is turned off, and the signal cannot be transmitted from input terminal V in to output terminal V out。When the input signal frequency is relatively high, the signal is coupled through the parasitic capacitance of the MOS itself. At this time, NMOS transistor M0 and NMOS transistor M1 are turned on, and the coupled signal is discharged to the ground through the on-resistances of NMOS transistor M0 and NMOS transistor M1, which can greatly improve the off isolation. By adopting the parallel transmission of complementary T-shaped NMOS and PMOS transistors, the signal can obtain full-amplitude transmission without loss of level, and the on-resistance is also greatly reduced.
[0035] The circuit structure of the channel control switch is as Figure 4 shown, including inverters INV1 to INV7, NOR gate ONR2_1, and NOR gate ONR2_2; the input terminal of inverter INV1 is connected to the CLK clock signal, and the output terminal is connected to the first input terminal of NOR gate ONR2_1. The second input terminal of NOR gate ONR2_1 is connected to the output terminal of inverter INV6. The output terminal of NOR gate ONR2_1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3. The output terminal of inverter INV3 is simultaneously connected to the input terminal of inverter INV4 and the first input terminal of NOR gate ONR2_2. The output terminal of inverter INV4 outputs the CLK1 clock signal; the second input terminal of NOR gate ONR2_2 is connected to the CLK clock signal, and the output terminal of NOR gate ONR2_2 is connected to the input terminal of inverter INV5. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6. The output terminal of inverter INV6 is connected to the input terminal of inverter INV7. The output terminal of inverter INV7 outputs the CLK2 clock signal; where the CLK1 clock signal and the CLK2 clock signal are non-overlapping pulse clock signals and are used as the control signals for the subsequent T-shaped switches.
[0036] Input the CLK clock signal to generate non-overlapping pulse clock signals CLK1 and CLK2 as the control signals for the subsequent T-shaped switches. Ensure that another switch will not be turned on before a certain switch is turned off, thus ensuring that signals between channels will not cause crosstalk.
[0037] The channel selection control signal generated by the channel control switch is as Figure 5 shown. During the switch conduction and the switching process of each channel, the control signals of each channel are independent of each other and there is no overlapping timing, that is, within a certain time period, only one video signal is allowed to be output, avoiding signal crosstalk caused by multiple channels being turned on simultaneously.
[0038] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A multi - selectable video switch circuit with low crosstalk and high isolation, characterized in that, Including: A T-type switch, which is composed of two complementary T-type PMOS and NMOS switches, achieving high off-state isolation; A channel selection control circuit, including a decoder circuit and a channel control switch. After the N-bit logic signal passes through the decoder circuit, one output pulse control signal is selected, and through the channel control switch, a non-overlapping clock control signal is generated to control the conduction of the corresponding T-type switch, realizing the selective output of the video signal; other unselected T-type switches are turned off.
2. The multiplexer video switch circuit with low crosstalk and high isolation as claimed in claim 1, wherein, The T-shaped switch includes: NMOS transistor M0, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, PMOS transistor M5, and resistor R L , capacitor C L , and two complementary switch logic control signals V1 and V2; The source terminal of NMOS transistor M0 is grounded, the gate terminal is connected to the control signal V2, and the drain terminal is simultaneously connected to the source terminals of NMOS transistor M2 and NMOS transistor M3, and this connection point is point A; the gate terminals of NMOS transistor M2 and NMOS transistor M3 are both connected to the control signal V1; The drain terminal of PMOS transistor M4 is connected to the drain terminal of NMOS transistor M2 and the signal input terminal V simultaneously. in The drain terminal of PMOS transistor M5 is connected to the drain terminal of NMOS transistor M3 and the signal output terminal V simultaneously. out The gate terminals of PMOS transistor M4 and PMOS transistor M5 are both connected to the control signal V2. The source terminals of PMOS transistor M4 and PMOS transistor M5 are both connected to the drain terminal of NMOS transistor M1, and this connection point is point B. The gate terminal of NMOS transistor M1 is connected to the control signal V2, and the source terminal is grounded. Resistor R L The first end is connected to the drain of NMOS transistor M3 and the drain of PMOS transistor M5 at the same time, and the second end is grounded; Capacitor C L The first terminal of which is connected to the drain terminal of NMOS transistor M3 and the drain terminal of PMOS transistor M5 simultaneously, and the second terminal is grounded.
3. The multiplexer video switch circuit with low crosstalk and high isolation as claimed in claim 2, wherein When the control signal V1 is at a high level and the control signal V2 is at a low level, the NMOS transistor M2, the NMOS transistor M3, the PMOS transistor M4, and the PMOS transistor M5 are turned on, the NMOS transistors M0 and M1 are turned off, the switch is opened, and the signal is transmitted from the input terminal V in to the output terminal V out ; When the control signal V1 is at a low level and the control signal V2 is at a high level, the NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, and PMOS transistor M5 are turned off, and the NMOS transistors M0 and M1 are turned on. The levels at points A and B are pulled down to ground, the overall T-type switch is turned off, and the signal cannot be transmitted from the input terminal V in to the output terminal V out ; When the input signal frequency is high, the signal is coupled through the parasitic capacitance of the MOS itself. At this time, NMOS transistor M0 and NMOS transistor M1 are turned on, and the coupled signal is discharged to the ground through the on-resistances of NMOS transistor M0 and NMOS transistor M1, improving the off-state isolation; by using complementary T-type NMOS and PMOS transistors in parallel transmission, the signal obtains full-amplitude transmission without level loss, reducing the on-resistance.
4. The multiplexer video switch circuit with low crosstalk and high isolation as claimed in claim 1, wherein The channel control switch includes inverters INV1 to INV7, NOR gate ONR2_1, and NOR gate ONR2_2; The input terminal of inverter INV1 is connected to the CLK clock signal, the output terminal is connected to the first input terminal of NOR gate ONR2_1, the second input terminal of NOR gate ONR2_1 is connected to the output terminal of inverter INV6, the output terminal of NOR gate ONR2_1 is connected to the input terminal of inverter INV2, the output terminal of inverter INV2 is connected to the input terminal of inverter INV3, the output terminal of inverter INV3 is simultaneously connected to the input terminal of inverter INV4 and the first input terminal of NOR gate ONR2_2, and the output terminal of inverter INV4 outputs the CLK1 clock signal; The second input terminal of NOR gate ONR2_2 is connected to the CLK clock signal, the output terminal of NOR gate ONR2_2 is connected to the input terminal of inverter INV5, the output terminal of inverter INV5 is connected to the input terminal of inverter INV6, the output terminal of inverter INV6 is connected to the input terminal of inverter INV7, and the output terminal of inverter INV7 outputs the CLK2 clock signal; Among them, the CLK1 clock signal and the CLK2 clock signal are non-overlapping pulse clock signals and are used as the control signals for the subsequent T-type switches.