Anti-radiation gallium nitride transistor based on outer layer shielding and manufacturing method thereof

Abstract

The invention discloses an anti-radiation gallium nitride transistor based on outer layer shielding and a manufacturing method thereof, the anti-radiation gallium nitride transistor comprises a substrate, an intrinsic gallium nitride layer and an intrinsic aluminum gallium nitride layer, a source electrode, a p-GaN layer and a drain electrode are arranged on the intrinsic aluminum gallium nitride layer in parallel, and a grid electrode is arranged on the p-GaN layer; a dielectric layer is arranged around the p-GaN layer, the source electrode, the grid electrode and the drain electrode, and an anti-radiation layer is arranged on the dielectric layer. By constructing a composite protection system of physical shielding of the external anti-radiation layer and synergistic reinforcement of the dielectric layer, a barrier is actively constructed on an incident path of high-energy particles, radiation damage is inhibited from the source, and the anti-radiation performance of the gallium nitride transistor is remarkably improved; in addition, monolithic integration of the shielding layer and the device structure is realized based on an in-situ growth process of an organic chemical vapor deposition method, and the interface state problem introduced by a traditional bonding process is avoided; and meanwhile, the GaN mutation heterojunction prepared by MOCVD is good in interface steepness, and the prepared transistor is high in stability and is more suitable for extreme environments such as space and the like.

Description

Technical Field

[0001] The present invention relates to an anti-radiation gallium nitride transistor based on outer shielding and a manufacturing method thereof, belonging to the technical field of integrated circuit devices. Background Art

[0002] In the space radiation environment, the ionization effect caused by high-energy charged particles (such as protons, heavy ions) and neutrons penetrating semiconductor devices is the core cause of the performance degradation and even permanent failure of gallium nitride (GaN) devices. Specifically, the electron-hole pairs generated by the incidence of high-energy particles will trigger the charge aggregation effect, causing single-event effects (SEE) such as current pulses and threshold voltage drift, seriously affecting the reliability of the device.

[0003] Currently, the mainstream anti-radiation technologies mainly rely on the electron regulation mechanism. For example: 1. Electric field regulation: Optimize the electric field distribution through the field plate structure to reduce the influence of ionized charges on the channel; 2. Interface trap control: Design defect states at the heterojunction interface to capture holes and reduce charge accumulation; 3. Doping optimization: Adjust the material doping concentration to enhance the carrier recombination efficiency.

[0004] However, the above methods essentially belong to passive compensation strategies, which can only alleviate the subsequent effects of ionization damage and cannot block the energy deposition of high-energy particles from the source. In addition, the traditional bonding process is prone to introducing interface state defects when integrating the external protective layer, resulting in a decrease in device stability and making it difficult to meet the long-term reliability requirements of the space extreme environment. Summary of the Invention

[0005] In order to solve the above problems, the present invention provides an anti-radiation gallium nitride transistor based on outer shielding and a manufacturing method thereof. The present invention actively constructs a barrier on the incident path of high-energy particles by constructing a composite protection system of "physical shielding of an external anti-radiation layer - synergistic reinforcement of a dielectric layer", that is, introducing a new anti-radiation protection layer, and realizing high-energy particle capture through element doping, suppressing radiation damage from the source, and significantly improving the anti-radiation performance of the gallium nitride transistor.

[0006] In the first aspect, the present invention provides an anti-radiation gallium nitride transistor based on outer shielding, including a substrate, an intrinsic gallium nitride layer, and an intrinsic aluminum gallium nitride layer arranged in sequence from bottom to top. An anode, a p-GaN layer, and a drain are arranged in parallel on the intrinsic aluminum gallium nitride layer. The p-GaN layer is located between the anode and the drain, and a gate is arranged on the p-GaN layer. A dielectric layer is arranged around the p-GaN layer, the anode, the gate, and the drain, and an anti-radiation layer is arranged on the dielectric layer.

[0007] In one embodiment of the present invention, the anti-irradiation layer is made of any one of boron carbide, nickel-based alloy, and perovskite, and its thickness is 1 to 100 nm; the dielectric layer is made of any one of Si3N4, Al2O3, MgO, and SiO2, and its thickness is 1 to 100 nm; the substrate is made of any one of sapphire, SiC, GaN, and Si; the intrinsic gallium nitride layer is made of any one of GaN, AlN, AlGaN, InGaN, and InAlN, and its thickness is 1 to 10 μm; the intrinsic aluminum gallium nitride layer is made of any one of GaN, AlN, AlGaN, InGaN, and InAlN, and its thickness is 5 to 100 nm; the thickness of the p-GaN layer is 1 - 200 nm.

[0008] Second, the present invention provides a manufacturing method of an anti-irradiation gallium nitride transistor based on an outer layer shield, including the following steps:

[0009] S201. Provide a substrate, and grow an intrinsic gallium nitride layer and an intrinsic aluminum gallium nitride layer on the substrate by metal-organic chemical vapor deposition.

[0010] S202. Deposit source and drain metals on the intrinsic aluminum gallium nitride layer by magnetron sputtering.

[0011] S203. Epitaxially grow a p-GaN layer on the intrinsic aluminum gallium nitride layer by atomic layer deposition, and the p-GaN layer is located between the source and the drain.

[0012] S204. Deposit gate metal on the p-GaN layer by magnetron sputtering and perform annealing.

[0013] S205. Epitaxially grow a dielectric layer on the device obtained in step S204 by atomic layer deposition.

[0014] S206. Grow an anti-irradiation layer on the dielectric layer by multi-source co-evaporation PVD technology.

[0015] S207. Remove the dielectric above part of the gate, source, and drain by dry etching or wet etching.

[0016] S208. Prepare metal PADs for the gate, source, and drain by magnetron sputtering.

[0017] In one embodiment of the present invention, step S201 specifically includes: providing a substrate, cleaning the substrate, first placing the silicon wafer in a 1% ammonium fluoride buffer solution to remove the surface oxide layer and inorganic impurities; then cleaning the substrate with pure water; then soaking the substrate in acetone and isopropyl alcohol in sequence, and ultrasonically cleaning for 3 - 5 minutes; finally rinsing the substrate with pure water and drying the substrate with a nitrogen gun.

[0018] Using the organic chemical vapor deposition method, a layer of 5 μm GaN and 20 nm AlGaN is grown on a substrate; first, trimethylgallium and ammonia are introduced into the reaction chamber, where the flow rate of trimethylgallium is 25 μmol / min, the flow rate of ammonia is 3.5 slm, the temperature is 1050 °C to 1070 °C, the pressure is 100 Mbar, and an intrinsic gallium nitride layer is deposited; then trimethylaluminum is introduced into the reaction chamber with a flow rate of 3 - 4 μmol / min, and an intrinsic aluminum gallium nitride layer is continuously deposited on the intrinsic gallium nitride layer.

[0019] In an embodiment of the present invention, the step S202 specifically includes: first, the prepared device is placed in a vacuum chamber and evacuated by the vacuum chamber, then Ti, Al, Ni, and Au metal targets are sequentially placed in the sputtering gun, and an arc discharge is generated by a high-voltage power supply, so that the metal atoms on the surface of the target are evaporated and deposited on the surface of the intrinsic aluminum gallium nitride layer; finally, annealing is performed at 850 °C in an atmosphere of argon as a protective gas; the drain and source form an ohmic contact with the intrinsic aluminum gallium nitride layer.

[0020] In an embodiment of the present invention, the step S203 specifically includes: first, the reaction chamber is evacuated to a high vacuum state to ensure the cleanliness during the atomic deposition process, then the substrate is heated to 300 °C by a heating system to promote the attachment and growth of the GaN material. In the sputtering system, the GaN material is sputtered into an atomic state and deposited on the intrinsic aluminum gallium nitride layer; finally, annealing is performed in a nitrogen atmosphere at 850 °C.

[0021] In an embodiment of the present invention, the step S204 specifically includes: first, the prepared device is placed in a vacuum chamber and evacuated by the vacuum chamber, then Ti, Al, Ni, and Au metal targets are sequentially placed in the sputtering gun, and an arc discharge is generated by a high-voltage power supply, so that the metal atoms on the surface of the target are evaporated and deposited on the surface of the p-GaN layer; finally, annealing is performed at 850 °C in an atmosphere of argon as a protective gas.

[0022] In an embodiment of the present invention, the step S205 specifically includes: first, the reaction chamber is evacuated to a high vacuum state to ensure the cleanliness and accuracy during the atomic deposition process, then the substrate is heated to 300 °C to promote the attachment and growth of the material. In the sputtering system, the dielectric thin film material is sputtered into an atomic state and deposited on the device; finally, the device is rapidly annealed at 850 °C.

[0023] In an embodiment of the present invention, the step S206 specifically includes: loading CsPbBr3 target and B2O3 doping source respectively in a vacuum chamber by using double evaporation boats, controlling the B concentration gradient by means of alternate exposure of baffles, setting a boron doping concentration gradient of 5%-15% in the perovskite film along the thickness direction, maintaining the perovskite lattice stability in the bottom low-doped region with 5% B, and enhancing the defect capture ability through B-Pb bonds in the top high-doped region with 15% B; depositing an amorphous-nanocrystalline hybrid layer, a columnar crystal transition layer, and a surface dense layer successively from bottom to top to form a density gradient structure from loose to dense.

[0024] In a third aspect, the present invention provides an anti-irradiation implementation method for a gallium nitride transistor based on an outer layer shield, including the following steps:

[0025] The anti-irradiation layer material has a high atomic binding energy and a tight atomic structure. When high-energy particles hit the surface of the anti-irradiation layer, the anti-irradiation material can block the deep penetration of the particles;

[0026] When high-energy particles interact with the atoms in the anti-irradiation layer, through processes such as inter-atomic collisions and scattering, the energy of the particles gradually loses; due to the action of the anti-irradiation layer atoms, the movement direction of the particles changes, thereby reducing the probability of their entering the active region of the device, reducing the impact of high-energy particles on the device, and improving the anti-irradiation performance of the device;

[0027] The characteristic of high carrier mobility of the anti-irradiation layer material ensures that the charges generated in the radiation environment can be quickly transported and recombined, reducing the accumulation of charges, thereby reducing the impact of radiation on the transistor performance.

[0028] The beneficial effects of the present invention are as follows:

[0029] 1. By constructing a composite protection system of "external anti-irradiation layer physical shielding - dielectric layer collaborative reinforcement", the present invention actively constructs a barrier on the incident path of high-energy particles, that is, introduces a new anti-irradiation protection layer, realizes high-energy particle capture through element doping, suppresses irradiation damage from the source, and significantly improves the anti-irradiation performance of the gallium nitride transistor.

[0030] 2. Combining material innovation and process optimization, the present invention realizes the monolithic integration of the shielding layer and the device structure based on the in-situ growth process of metal-organic chemical vapor deposition (MOCVD), avoiding the interface state problems introduced by traditional bonding processes. At the same time, the GaN hetero-junction prepared by MOCVD has a good interface steepness, and the prepared transistor has high stability and is more suitable for extreme environments such as space.

[0031] 3. Based on a gallium nitride-based high electron mobility transistor, the present invention sequentially sets a source electrode, a drain electrode, a p-GaN layer, and a gate electrode on the intrinsic aluminum gallium nitride layer, having the advantage of high electron mobility.

[0032] 4. The anti-irradiation gallium nitride transistor provided by the present invention constructs an energy-selective attenuation barrier on the surface of the device by integrating a gradient physical shielding layer: the anti-irradiation layer uses a lead-based perovskite material. Since the lead element has a large atomic number, it is theoretically beneficial for shielding γ-rays. Partially replacing the anions in the perovskite material with element B, due to the high neutron capture cross-section of element B, it can have a good absorption effect on thermal neutrons. The perovskite material has a special layered structure and can be used as a neutron slow-down layer with alternating light and heavy atoms in neutron shielding, greatly improving the neutron slow-down ability. At the same time, the perovskite material has the characteristic of high carrier mobility, can quickly export the charges generated in the radiation environment, and reduce the secondary damage induced by radiation. Compared with the limitation of passive compensation for ionization damage in traditional electron regulation schemes, the present invention actively intercepts incident particles through the intrinsic physical properties of the material, blocks the energy deposition path, and fundamentally suppresses the charge aggregation effect caused by single-event effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 It is a schematic diagram of the device structure after the end of step S102 in Embodiment 2 of the present invention;

[0035] Figure 2 It is a schematic diagram of the device structure after the end of step S104 in Embodiment 2 of the present invention;

[0036] Figure 3 It is a schematic diagram of the device structure after the end of step S105 in Embodiment 2 of the present invention;

[0037] Figure 4 It is a schematic diagram of the device structure after the end of step S106 in Embodiment 2 of the present invention;

[0038] Figure 5 It is a schematic diagram of the final device structure after the end of step S108 in Embodiment 2 of the present invention;

[0039] Figure 6 It is a transfer characteristic diagram of the present invention and a conventional HEMT device before and after irradiation under zero bias voltage.

[0040] In the figure: 1. Substrate; 2. Intrinsic gallium nitride layer; 3. Intrinsic aluminum gallium nitride layer; 4. p-GaN layer; 5. Source electrode; 6. Gate electrode; 7. Drain electrode; 8. Dielectric layer; 9. Anti-irradiation layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will further describe the embodiments of the present invention in detail with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0042] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. Among them, the terms "first position" and "second position" are two different positions.

[0043] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] Embodiment 1

[0045] As Figures 1 to 5 shown, this embodiment provides an anti-radiation gallium nitride transistor based on an outer layer shield, including a substrate 1, an intrinsic gallium nitride layer 2, and an intrinsic aluminum gallium nitride layer 3 arranged in sequence from bottom to top. An anode 5, a p-GaN layer 4, and a drain 7 are arranged in parallel on the intrinsic aluminum gallium nitride layer 3. The p-GaN layer 4 is located between the anode 5 and the drain 7, and a gate 6 is arranged on the p-GaN layer 4. A dielectric layer 8 is arranged around the p-GaN layer 4, the anode 5, the gate 6, and the drain 7, and an anti-radiation layer 9 is arranged on the dielectric layer 8.

[0046] Optionally, the substrate 1 is made of any one of sapphire, SiC, GaN, and Si.

[0047] Optionally, the intrinsic gallium nitride layer 2 is made of any one of GaN, AlN, AlGaN, InGaN, and InAlN, and its thickness is 1 - 10 μm.

[0048] Optionally, the intrinsic aluminum gallium nitride layer 3 is made of any one of GaN, AlN, AlGaN, InGaN, and InAlN, and its thickness is 5-100 nm.

[0049] Optionally, the thickness of the p-GaN layer 4 is 1-200 nm.

[0050] Optionally, the dielectric layer 8 is made of any one of Si3N4, Al2O3, MgO, and SiO2, and its thickness is 1-100 nm.

[0051] Optionally, the anti-irradiation layer 9 is made of any one of boron carbide, nickel-based alloy, and perovskite, and its thickness is 1-100 nm.

[0052] In this embodiment, a gallium nitride triode structure is used. Through the dielectric layer 8 and the anti-irradiation layer 9 disposed thereon, a composite protection system of "external anti-irradiation layer physical shielding - dielectric layer collaborative reinforcement" is formed, and a barrier is actively constructed on the incident path of high-energy particles, that is, a new anti-irradiation protection layer is introduced to suppress irradiation damage from the source, significantly improving the anti-irradiation performance of the gallium nitride transistor.

[0053] Embodiment 2

[0054] This embodiment provides a manufacturing method of an anti-irradiation gallium nitride transistor based on outer layer shielding according to Embodiment 1, including the following steps:

[0055] S101. Provide a substrate 1, and grow an intrinsic gallium nitride layer 2 and an intrinsic aluminum gallium nitride layer 3 on the substrate 1 by metalorganic chemical vapor deposition.

[0056] S102. Deposit a source electrode 5 and a drain electrode 7 on the intrinsic aluminum gallium nitride layer 3 by magnetron sputtering, and perform high-temperature annealing on the device. The drain electrode 6 and the source electrode 5 form an ohmic contact with the intrinsic aluminum gallium nitride layer 3.

[0057] S103. Epitaxially grow a p-GaN layer 4 on the intrinsic aluminum gallium nitride layer 3 by atomic deposition. The p-GaN layer 4 is located between the source electrode 5 and the drain electrode 7.

[0058] S104. Prepare a gate electrode 6 on the p-GaN layer 4 by magnetron sputtering and perform annealing.

[0059] S105. Epitaxially grow a dielectric layer 8 on the device obtained in step S104 by atomic deposition.

[0060] S106. Grow an anti-irradiation layer 9 on the dielectric layer 8 by multi-source co-evaporation PVD technology.

[0061] S107. Remove the dielectric above part of the gate 6, source 5, and drain 7 by dry etching or wet etching method.

[0062] S108. Prepare the metal PADs of the gate 6, source 5, and drain 7 by magnetron sputtering method.

[0063] Embodiment 3

[0064] This embodiment provides a manufacturing method of an anti-radiation gallium nitride transistor based on outer layer shielding according to Embodiment 1, including the following steps:

[0065] S201. Provide a substrate 1, and grow an intrinsic gallium nitride layer 2 and an intrinsic aluminum gallium nitride layer 3 on the substrate 1 by organic chemical vapor deposition method.

[0066] Step S201 specifically includes:

[0067] Provide a substrate 1, clean the substrate 1. First, place the silicon wafer in 1% ammonium fluoride buffer solution (BOE) to remove the surface oxide layer and inorganic impurities; then clean the substrate 1 with pure water; then soak the substrate 1 in acetone and isopropanol in sequence, and ultrasonically clean for 3 - 5 minutes; finally, rinse the substrate 1 with pure water and blow dry the substrate 1 with a nitrogen gun. Among them, the substrate 1 in this embodiment uses silicon material;

[0068] Use organic chemical vapor deposition method (MOCVD) to grow a 5μm GaN and a 20nm AlGaN on the substrate 1; first introduce trimethylgallium and ammonia into the reaction chamber, where the flow rate of trimethylgallium is 25 μmol / min, the flow rate of ammonia is 3.5 slm, the temperature is 1050 °C - 1070 °C, and the pressure is 100 Mbar to deposit the intrinsic gallium nitride layer 2; then introduce trimethylaluminum into the reaction chamber, with a flow rate of 3 - 4 μmol / min, and continue to deposit the intrinsic aluminum gallium nitride layer 3 on the intrinsic gallium nitride layer 2;

[0069] S202. Use magnetron sputtering method to deposit the source 5 and drain 7 metals on the intrinsic aluminum gallium nitride layer 3.

[0070] Step S202 specifically includes:

[0071] First, place the prepared device in a vacuum chamber and evacuate it with a vacuum chamber, then place the Ti, Al, Ni, and Au metal targets in the sputtering gun in sequence, generate arc discharge through a high-voltage power supply, so that the metal atoms on the surface of the target are evaporated and deposited on the surface of the intrinsic aluminum gallium nitride layer 3; finally, anneal at 850 °C in an atmosphere with argon as the protective gas; the drain 6 and source 5 form ohmic contacts with the intrinsic aluminum gallium nitride layer 3.

[0072] S203. Use atomic deposition method to epitaxially grow a p-GaN layer 4 on the intrinsic aluminum gallium nitride layer 3, and the p-GaN layer 4 is located between the source electrode 5 and the drain electrode 7;

[0073] Step S203 specifically includes:

[0074] First, evacuate the reaction chamber to a high vacuum state to ensure the cleanliness during the atomic deposition process. Then, heat the substrate to 300 °C through a heating system to promote the attachment and growth of the GaN material. In the sputtering system, sputter the GaN material into atomic state and deposit it on the intrinsic aluminum gallium nitride layer 3. Finally, perform annealing in a nitrogen atmosphere at 850 °C;

[0075] S204. Deposit the gate 6 metal on the p-GaN layer 4 by magnetron sputtering method and perform annealing;

[0076] Step S204 specifically includes:

[0077] First, place the prepared device in a vacuum chamber and evacuate it to a vacuum by the vacuum chamber. Then, place the Ti, Al, Ni, and Au metal targets in the sputtering gun in turn. Generate arc discharge through a high-voltage power supply, so that the metal atoms on the surface of the target are evaporated and deposited on the surface of the p-GaN layer 4. Finally, perform annealing at 850 °C in an atmosphere with argon as the protective gas;

[0078] S205. Use atomic deposition method to epitaxially grow a dielectric layer 8 on the device obtained in step S204;

[0079] Step S205 specifically includes:

[0080] First, evacuate the reaction chamber to a high vacuum state to ensure the cleanliness and precision during the atomic deposition process. Then, heat the substrate to 300 °C to promote the attachment and growth of the material. In the sputtering system, sputter the dielectric thin film material into atomic state and deposit it on the device. Finally, perform rapid annealing on the device at 850 °C;

[0081] S206. Use multi-source co-evaporation PVD technology to grow an anti-irradiation layer 9 on the dielectric layer 8;

[0082] Step S206 specifically includes:

[0083] In a vacuum chamber, a CsPbBr3 target and a B2O3 doping source are respectively loaded by two evaporation boats. By alternately exposing through a baffle to control the B concentration gradient, a boron doping concentration gradient of 5% - 15% is set along the thickness direction in the perovskite (CsPbBr3) thin film. The low-doping region at the bottom layer (5% B) maintains the lattice stability of the perovskite, and the high-doping region at the surface layer (15% B) enhances the defect capture ability through B-Pb bonds. An amorphous-nanocrystalline mixed layer, a columnar crystal transition layer, and a surface dense layer are sequentially deposited from bottom to top to form a density gradient structure from loose to dense.

[0084] Among them, a multi-source co-evaporation technique is used to simultaneously evaporate elements such as lead (Pb), cesium (Cs), bromine (Br), and boron (B). By precisely controlling the power and rate of each evaporation source, in-situ doping of perovskite materials (such as CsPbBr3) is achieved. Boron element doping: By evaporating an independent boron source, B atoms replace the Br sites in the perovskite lattice to form a CsPbBr3-xBx structure, enhancing the neutron capture ability. Moreover, by dynamically adjusting the evaporation rates of Pb and B, a gradient shielding layer with a high B concentration (10 at.%) at the surface layer and a high Pb concentration (50 at.%) at the bottom layer is formed, taking into account the requirements of neutron absorption and γ-ray shielding. Compared with traditional sputtering or single-source evaporation, the multi-source co-evaporation used in this embodiment can avoid composition segregation, ensure doping uniformity (composition deviation < ±2%), increase the film density by 30%, and significantly reduce radiation-induced lattice defects.

[0085] Therefore, through compositional gradient, process low-temperature, and interface co-optimization, the multi-source co-evaporation PVD technology in the present invention breaks through the limitations of traditional single-source deposition technology, providing a high-uniformity and high-reliability functional layer preparation scheme for radiation-resistant GaN transistors. Its seamless integration with the MOCVD process, the compatibility of the multi-source PVD low-temperature process with the MOCVD epitaxial layer, and the avoidance of damage to the heterojunction structure by high-temperature annealing further improve the performance stability of the device in an extreme radiation environment.

[0086] S207. Remove the dielectric above part of the gate 6, source 5, and drain 7 by dry etching or wet etching.

[0087] In this embodiment, the dry etching method is used to remove the dielectric above part of the gate 6, source 5, and drain 7. In this embodiment, Cl2 is incorporated into SF6 for dry etching.

[0088] S208. Prepare the metal PADs of the gate 6, source 5, and drain 7 by magnetron sputtering.

[0089] In this embodiment, Ti / Al / Ni / Au (20nm / 160nm / 55nm / 90nm) is deposited in the corresponding etched area and rapidly annealed at 850 °C for 1 minute in N2 to obtain the metal PADs of the gate 6, source 5, and drain 7.

[0090] Embodiment 4

[0091] This embodiment provides an anti-radiation implementation method for a gallium nitride transistor based on outer layer shielding according to Embodiment 1, including the following steps:

[0092] The anti-radiation layer 9 material (such as perovskite) has a high atomic binding energy and a relatively compact atomic structure. When high-energy particles impact the surface of the anti-radiation layer 9, the anti-radiation material can block the penetration of particles to a certain extent;

[0093] When high-energy particles interact with the atoms in the anti-radiation layer 9, through processes such as interatomic collisions and scattering, the energy of the particles will gradually be lost; due to the action of the atoms in the anti-radiation layer 9, the movement direction of the particles will change, thereby reducing the probability of them entering the active region of the device, reducing the impact of high-energy particles on the device, and improving the anti-radiation performance of the device;

[0094] The characteristic of the high carrier mobility of the anti-radiation layer 9 material can ensure that the charges generated in the radiation environment can be quickly transported and recombined, reducing the accumulation of charges, thereby reducing the impact of radiation on the transistor performance.

[0095] As Figure 6 shown, Figure 6 is the transfer characteristic diagram of the present invention and a conventional HEMT device before and after irradiation under zero bias. Figure 6 It shows that the transfer characteristic curve of the present invention is closer to the state of the device before irradiation in terms of curve position, slope, off-state current, and hysteresis effect, and the device degradation degree is significantly reduced.

[0096] In summary, through the composite protection system of "external anti-radiation layer physical shielding - dielectric layer collaborative reinforcement", combined with material innovation and process optimization, the present invention significantly improves the anti-radiation performance of gallium nitride transistors, and the specific effects are as follows:

[0097] 1. Actively shield high-energy particles:

[0098] γ-ray shielding: The anti-radiation layer uses a lead-based perovskite material (such as CsPbBr3). By utilizing the high atomic number (Z = 82) of lead elements, the energy of γ-rays is effectively attenuated through the photoelectric effect and Compton scattering, and the shielding efficiency is increased by more than 50% compared with the traditional Al2O3 dielectric layer.

[0099] Neutron absorption and moderation: By partially substituting the perovskite anion sites with boron (B) elements (such as CsPbBr3-xBx), the high neutron capture cross-section of B (3,840 barns) is utilized to achieve efficient thermal neutron absorption; the perovskite layered structure forms a neutron moderation layer with alternating light and heavy atoms, which attenuates the fast neutron energy to the thermal neutron range, and the comprehensive neutron shielding efficiency reaches 90%. 10 The high neutron capture cross-section of B (3,840 barns) is used to achieve efficient thermal neutron absorption; the perovskite layered structure forms a neutron moderation layer with alternating light and heavy atoms, which attenuates the fast neutron energy to the thermal neutron range, and the comprehensive neutron shielding efficiency reaches 90%.

[0100] 2. Charge management optimization:

[0101] Fast carrier extraction: The high carrier mobility (>10 cm 2 / V·s) of the perovskite material can quickly extract the excess charges induced by radiation, avoiding secondary damage caused by charge accumulation, and reducing the device leakage current by two orders of magnitude.

[0102] Synergistic protection of the dielectric layer: The dielectric layer (such as Si3N4 / Al2O3) and the anti-irradiation layer form an energy-selective barrier, which restricts the penetration of low-energy particles into the active region of the device through band offset design, and at the same time synergistically suppresses the interface charge injection with the shielding layer.

[0103] 3. Process and reliability improvement:

[0104] Monolithic integration advantage: The monolithic integration of the anti-irradiation layer and the GaN / AlGaN heterojunction is realized by using the MOCVD in-situ growth technology. The steepness of the heterojunction interface (transition layer thickness <1 nm) is improved by 5 times compared with the traditional bonding process, and the interface state density is reduced to 10 10 cm -2 or less, ensuring the long-term stability of the device at extreme temperatures (-180~200 °C).

[0105] Gradient shielding design: The anti-irradiation layer adopts a gradient doping structure (such as the B element concentration gradually decreasing from 10% on the surface layer to 2% on the bottom layer), taking into account the absorption of high-energy particles on the surface layer and the stress matching of the bottom layer structure, and extending the anti-irradiation life of the device to 10 8 Gy(Si) dose level.

[0106] Compared with the traditional electronic regulation scheme, an anti-irradiation gallium nitride transistor based on outer layer shielding and its manufacturing method provided by the present invention block the energy deposition path from the source through a physical shielding mechanism, and the charge aggregation effect caused by the single particle effect is reduced by more than 80%. The threshold voltage drift amount of the device under an equivalent irradiation dose of 100 MeV·cm 2 / mg is less than 0.1 V, meeting the stringent requirements of deep space exploration missions for high anti-irradiation devices.

[0107] In this text, specific embodiments are used to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principles of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention. Therefore, the protection scope of this invention patent shall be subject to the appended claims.

Claims

1. An anti-radiation gallium nitride transistor based on an outer shield, characterized in that It includes a substrate (1), an intrinsic gallium nitride layer (2), and an intrinsic aluminum gallium nitride layer (3) arranged successively from bottom to top. On the intrinsic aluminum gallium nitride layer (3), a source electrode (5), a p-GaN layer (4), and a drain electrode (7) are arranged in parallel. The p-GaN layer (4) is located between the source electrode (5) and the drain electrode (7), and a gate electrode (6) is arranged on the p-GaN layer (4); a dielectric layer (8) is arranged around the p-GaN layer (4), the source electrode (5), the gate electrode (6), and the drain electrode (7), and an anti-irradiation layer (9) is arranged on the dielectric layer (8).

2. The anti-radiation gallium nitride transistor based on an outer layer shield according to claim 1, wherein The anti-irradiation layer (9) is made of any one of boron carbide, nickel-based alloy, and perovskite, and its thickness is 1 - 100 nm; the dielectric layer (8) is made of any one of Si3N4, Al2O3, MgO, and SiO2, and its thickness is 1 - 100 nm; the substrate (1) is made of any one of sapphire, SiC, GaN, and Si; the intrinsic gallium nitride layer (2) is made of any one of GaN, AlN, AlGaN, InGaN, and InAlN, and its thickness is 1 - 10 μm; the intrinsic aluminum gallium nitride layer (3) is made of any one of GaN, AlN, AlGaN, InGaN, and InAlN, and its thickness is 5 - 100 nm; the thickness of the p-GaN layer (4) is 1 - 200 nm.

3. A manufacturing method of an anti-irradiation gallium nitride transistor based on an outer layer shield according to claim 1 or 2, characterized in that, It includes the following steps: S201: Provide a substrate (1), and use the organic chemical vapor deposition method to grow an intrinsic gallium nitride layer (2) and an intrinsic aluminum gallium nitride layer (3) on the substrate (1); S202: Use the magnetron sputtering method to deposit the source electrode (5) and drain electrode (7) metals on the intrinsic aluminum gallium nitride layer (3); S203: Use the atomic deposition method to epitaxially grow a p-GaN layer (4) on the intrinsic aluminum gallium nitride layer (3), and the p-GaN layer (4) is located between the source electrode (5) and the drain electrode (7); S204: Use the magnetron sputtering method to deposit the gate electrode (6) metal on the p-GaN layer (4) and perform annealing; S205: Use the atomic deposition method to epitaxially grow a dielectric layer (8) on the device obtained in step S204; S206: Use the multi-source co-evaporation PVD technology to grow an anti-irradiation layer (9) on the dielectric layer (8); S207: Use the dry etching or wet etching method to remove the dielectric above part of the gate electrode (6), the source electrode (5), and the drain electrode (7); S208: Use the magnetron sputtering method to prepare the metal PADs of the gate electrode (6), the source electrode (5), and the drain electrode (7).

4. The manufacturing method of an anti-irradiation gallium nitride transistor based on an outer layer shield according to claim 3, characterized in that, The specific content of step S201 includes: Provide a substrate (1), clean the substrate (1). First, place the silicon wafer in a 1% ammonium fluoride buffer solution to remove the surface oxide layer and inorganic impurities; then use pure water to clean the substrate (1); then soak the substrate (1) in acetone and isopropyl alcohol in sequence, and use ultrasonic cleaning for 3 - 5 minutes; finally, rinse the substrate (1) with pure water and dry the substrate (1) with a nitrogen gun. Using the organic chemical vapor deposition method, a 5-μm GaN layer and a 20-nm AlGaN layer are grown on the substrate (1); first, trimethylgallium and ammonia are introduced into the reaction chamber. Among them, the flow rate of trimethylgallium is 25 μmol / min, the flow rate of ammonia is 3.5 slm, the temperature is 1050 °C to 1070 °C, the pressure is 100 Mbar, and an intrinsic gallium nitride layer (2) is deposited; then trimethylaluminum is introduced into the reaction chamber with a flow rate of 3 - 4 μmol / min, and an intrinsic aluminum gallium nitride layer (3) is continuously deposited on the intrinsic gallium nitride layer (2).

5. The manufacturing method of an anti-radiation gallium nitride transistor based on an outer layer shield according to claim 3, characterized in that, The specific steps of step S202 include: first, the prepared device is placed in a vacuum chamber and evacuated by the vacuum chamber, then Ti, Al, Ni, and Au metal targets are successively placed in the sputtering gun, and arc discharge is generated by a high-voltage power supply, so that the metal atoms on the surface of the target are evaporated and deposited on the surface of the intrinsic aluminum gallium nitride layer (3); finally, annealing is carried out at 850 °C in an atmosphere with argon as the protective gas; the drain electrode (6) and the source electrode (5) form an ohmic contact with the intrinsic aluminum gallium nitride layer (3).

6. The manufacturing method of an anti-irradiation gallium nitride transistor based on an outer layer shield according to claim 3, wherein, The specific steps of step S203 include: first, the reaction chamber is evacuated to a high vacuum state to ensure the cleanliness during the atomic deposition process, then the substrate is heated to 300 °C by a heating system to promote the attachment and growth of the GaN material. In the sputtering system, the GaN material is sputtered into an atomic state and deposited on the intrinsic aluminum gallium nitride layer (3); finally, annealing is carried out in a nitrogen atmosphere at 850 °C.

7. The manufacturing method of an anti-irradiation gallium nitride transistor based on an outer layer shield according to claim 3, characterized in that, The specific steps of step S204 include: first, the prepared device is placed in a vacuum chamber and evacuated by the vacuum chamber, then Ti, Al, Ni, and Au metal targets are successively placed in the sputtering gun, and arc discharge is generated by a high-voltage power supply, so that the metal atoms on the surface of the target are evaporated and deposited on the surface of the p-GaN layer (4); finally, annealing is carried out at 850 °C in an atmosphere with argon as the protective gas.

8. The manufacturing method of an anti-radiation gallium nitride transistor based on an outer layer shield according to claim 3, wherein The specific steps of step S205 include: first, the reaction chamber is evacuated to a high vacuum state to ensure the cleanliness and accuracy during the atomic deposition process, then the substrate is heated to 300 °C to promote the attachment and growth of the material. In the sputtering system, the dielectric thin film material is sputtered into an atomic state and deposited on the device; finally, rapid annealing is carried out on the device at 850 °C.

9. The manufacturing method of an anti-radiation gallium nitride transistor based on an outer layer shield according to claim 3, characterized in that The specific steps of step S206 include: in the vacuum chamber, a CsPbBr3 target and a B2O3 doping source are respectively loaded by using double evaporation boats, and the B concentration gradient is controlled by alternating exposure of the baffle, and a 5% - 15% boron doping concentration gradient is set along the thickness direction in the perovskite thin film. The bottom low-doped region with 5% B maintains the perovskite lattice stability, and the surface high-doped region with 15% B enhances the defect capture ability through B-Pb bonds; an amorphous-nanocrystalline mixed layer, a columnar crystal transition layer, and a surface dense layer are successively deposited from bottom to top to form a density gradient structure from loose to dense.

10. A method for realizing anti-radiation of an anti-radiation gallium nitride transistor based on an outer layer shield according to claim 1 or 2, characterized in that, Including the following steps: The material of the anti-irradiation layer (9) has a high atomic binding energy and a tight atomic structure. When high-energy particles impact the surface of the anti-irradiation layer (9), the anti-irradiation material can block the penetration of the particles; When high-energy particles interact with the atoms in the anti-irradiation layer (9), through processes such as inter-atomic collisions and scattering, the energy of the particles is gradually lost; due to the action of the atoms in the anti-irradiation layer (9), the movement direction of the particles is changed, thereby reducing the probability of their entry into the active region of the device, reducing the impact of high-energy particles on the device, and enhancing the anti-irradiation performance of the device; The characteristic of high carrier mobility of the material of the anti-irradiation layer (9) ensures that the charges generated in the radiation environment can be quickly transported and recombined, reducing the accumulation of charges, thereby reducing the impact of radiation on the performance of the transistor.

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