Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes a semiconductor body, including a first surface and a second surface disposed opposite each other; the semiconductor body also includes a well region and a first region; the well region is connected to a first side surface of the first region, and the well region extends to a first bottom surface of the first region and is connected to the first bottom surface; wherein the first bottom surface is opposite to the first surface; an isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface. The present invention can improve the breakdown voltage of a semiconductor device without increasing the epitaxial growth time. Improve the breakdown voltage of a semiconductor device without increasing the epitaxial growth time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based on third-generation wide-bandgap semiconductors such as silicon carbide or gallium nitride has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width and high electron saturation drift velocity. This makes third-generation wide-bandgap semiconductor materials such as silicon carbide and gallium nitride a research hotspot for power semiconductor devices. In high-power applications such as high-speed railways, hybrid vehicles, and intelligent high-voltage direct current transmission, silicon carbide devices are given high expectations.

[0003] A key parameter of semiconductor devices is breakdown voltage. Planar gate semiconductor devices use the epitaxial layer as the pressure-bearing region. Therefore, current planar gate semiconductor devices require thicker epitaxial layers to increase breakdown voltage, which increases epitaxial growth time and defects. In other words, current semiconductor devices cannot simultaneously meet the requirements of both short epitaxial growth time and high breakdown voltage. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to improve the breakdown voltage of the semiconductor device without increasing the epitaxial growth time.

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0006] A semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region being in contact with a first side surface of the first region and extending to and in contact with a first bottom surface of the first region; wherein the first bottom surface is opposite to the first surface;

[0007] an isolation structure, located on the first surface and extending from the first surface into the first region, the isolation structure being spaced apart from the first side surface;

[0008] a gate, located on the first surface;

[0009] A source is located on the first surface, and a portion of the source contacting the first surface is located on a side of the isolation structure away from the first side surface.

[0010] Optionally, the first surface is further provided with an isolation groove, the isolation groove extends from the first surface into the first region, the isolation groove is spaced apart from the first side surface, and the isolation structure is located in the isolation groove.

[0011] Optionally, the semiconductor body also includes a second region, which is set to the first conductivity type and is located on the first surface, the second region includes a second bottom surface opposite to the first surface, the second region is located on the side of the isolation trench away from the first side surface, and the first region is connected to the second bottom surface, the ion concentration of the first region is less than the ion concentration of the second region; the isolation trench and the second region are spaced apart.

[0012] Optionally, the semiconductor device further comprises a first insulating layer;

[0013] The first insulating layer is located on the first surface;

[0014] The gate is located on a side of the first insulating layer away from the first surface;

[0015] The second region further includes a second side surface close to the isolation trench; along the thickness direction of the semiconductor device, the second side surface is flush with a side surface of the first insulating layer.

[0016] Optionally, the depth of the isolation trench is greater than the thickness of the second region.

[0017] Optionally, along a thickness direction of the semiconductor device, a thickness of the first region is 80% to 90% of a maximum thickness of the well region.

[0018] Optionally, along the thickness direction of the semiconductor device, the depth of the isolation trench is 30% to 70% of the maximum thickness of the well region.

[0019] Optionally, the material of the isolation structure includes at least one of silicon dioxide and silicon nitride.

[0020] Optionally, the semiconductor device further includes a drain, and the drain is located on the second surface.

[0021] Optionally, the semiconductor body further includes a third region, which is set to the second conductivity type and is located on the first surface, and the ion concentration of the third region is greater than the ion concentration of the well region; the third region is located on a side of the first region away from the well region.

[0022] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0023] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region being in contact with a first side surface of the first region and extending to and in contact with a first bottom surface of the first region; wherein the first bottom surface is opposite to the first surface;

[0024] forming an isolation structure, wherein the isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface;

[0025] forming a gate on the first surface;

[0026] A source is formed on the first surface, and a portion of the source in contact with the first surface is located on a side of the isolation structure away from the first side surface.

[0027] Optionally, providing the semiconductor body includes:

[0028] forming an isolation trench on the first surface of the semiconductor body, wherein the isolation trench extends from the first surface into the first region, and the isolation trench is spaced apart from the first side surface;

[0029] The forming of the isolation structure comprises:

[0030] The isolation structure is formed in the isolation trench.

[0031] Optionally, providing the semiconductor body includes:

[0032] forming the well region on the first surface of the semiconductor body;

[0033] forming the first region on the first surface of the semiconductor body;

[0034] The isolation trench is formed on the first surface of the semiconductor body.

[0035] Optionally, providing the semiconductor body includes:

[0036] A semiconductor body is provided which also includes a third region, wherein the third region is set to the second conductivity type and is located on the first surface, and the ion doping concentration of the third region is greater than the ion doping concentration of the well region; the third region is located on a side of the first region away from the well region.

[0037] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described above, wherein the substrate is used to support the semiconductor device.

[0038] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0039] The power conversion circuit includes a circuit board and at least one semiconductor device as described above, wherein the semiconductor device is electrically connected to the circuit board.

[0040] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described above, wherein the power conversion circuit is configured to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input the converted power into the load.

[0041] The technical solution of the embodiment of the present invention adopts a semiconductor device including a semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a well region and a first region; the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on the first surface; the well region is connected to the first side surface of the first region, and the well region extends to the first bottom surface of the first region and is connected to the first bottom surface; wherein the first bottom surface is opposite to the first surface; an isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface; a gate is located on the first surface; a source is located on the first surface, and the portion of the source contacting the first surface is located on the side of the isolation structure away from the first side surface. The breakdown voltage is increased by configuring the path of the current in the first region, without extending the path in the epitaxial layer to increase the breakdown voltage. The semiconductor device of this embodiment does not need to increase the thickness of the epitaxial layer in the semiconductor body to increase the breakdown voltage of the semiconductor device.

[0042] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 2 for Figure 1 Current path diagram of semiconductor devices;

[0046] Figure 3 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0047] Figure 4 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0048] Figure 5-Figure 9 A schematic diagram of the product structure corresponding to the main steps of the method for manufacturing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, referring to Figure 1The semiconductor device includes a semiconductor body 100 , an isolation structure 200 , a gate 302 and a source 400 . The semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104; the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on the first surface 101; the well region 103 is connected to a first side surface 1041 of the first region 104, and the well region 103 extends to a first bottom surface 1042 of the first region 104 and is connected to the first bottom surface 1042; wherein the first bottom surface 1042 is opposite to the first surface 101; the isolation structure 200 is located on the first surface 101 and extends from the first surface 101 to the first region 104, and the isolation structure 200 is spaced apart from the first side surface 1041; the gate 302 is located on the first surface 101; the source 400 is located on the first surface 101, and the portion of the source 400 contacting the first surface 101 is located on the side of the isolation structure 200 away from the first side surface 1041.

[0052] Specifically, the semiconductor device is, for example, a MOSFET device, which can be an N-type device or a P-type device. If the semiconductor device is an N-type device, the first conductivity type is N-type (i.e., N-type doping), and the second conductivity type is P-type (i.e., P-type doping). If the semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. This embodiment is described using an N-type semiconductor device as an example. The semiconductor body 100, for example, includes a substrate 10 and an epitaxial layer 20. The substrate 10 is, for example, an N+ substrate, such as an N+ silicon carbide substrate or an N+ gallium nitride substrate. The epitaxial layer 20 is an N-epitaxial layer, such as an N-silicon carbide epitaxial layer or an N-gallium nitride epitaxial layer. The surface of the epitaxial layer 20 remote from the substrate 10 is a first surface 101 of the semiconductor body 100, and the surface of the substrate 10 remote from the epitaxial layer 20 is a second surface 102 of the semiconductor body 100. The well region 103 is, for example, a P-type well region, that is, the well region 103 can be understood as a PW region. P-type ion implantation can be performed in the region of the epitaxial layer 20 where the well region 103 is to be formed to form the well region 103. The P-type ions can be aluminum ions or boron ions, etc., and the ion concentration can be 10 14 ~10 18 / cm 3. The first region 104 is of the first conductivity type, for example, the first region 104 is an N-type region. The second region 106 is of the first conductivity type, for example, the second region 106 is an N-type region. The N-type region is a region formed by N-type ion implantation, and the N-type ions are, for example, phosphorus ions or nitrogen ions. The ion concentration of the first region 104 is less than the ion concentration of the second region 106, for example, the first region 104 is an N-region, and the second region 106 is an N+region. Both the first region 104 and the second region 106 are conductive, and because the ion concentration of the first region 104 is less than the ion concentration of the second region 106, the resistance per unit length of the first region 104 is less than the resistance per unit length of the second region 106. The second region 106 can form an ohmic contact with the source 400, thereby transmitting current to the source 400.

[0053] The first side surface 1041 and the first bottom surface 1042 of the first region 104 are connected to the well region 103. During the manufacturing process of the semiconductor body 100, P-type ion implantation can be first performed at positions corresponding to the well region 103, the first region 104 and the second region 106 to form a P-type region, and then N- ion implantation and N+ ion implantation can be performed in sequence in the P-type region to form the well region 103, the first region 104 and the second region 106.

[0054] In addition, the first surface 101 is further provided with an isolation structure 200, which is made of insulating material. The isolation structure 200 is spaced apart from the first side surface 1041, that is, the isolation structure 200 does not contact the first side surface 1041, and a portion of the first region 104 exists between the two. Figure 2 As shown, Figure 2 for Figure 1Figure 1 shows the current path of the semiconductor device in FIG. After the current in the semiconductor body 100 enters the well region 103, it first enters the first region 104, then goes around to the bottom surface of the isolation structure 200, and is then transmitted from the bottom surface of the isolation structure 200 to the position where the source 400 contacts the first surface 101, and then is transmitted to the source. Compared with existing semiconductor devices, on the one hand, the first region 104 is provided, and the resistance per unit length of the first region 104 is larger. Compared with the current directly entering the source from the well region 103, the resistance encountered by the current passing through the first region 104 from the well region 103 before entering the source is greater, thereby making the breakdown voltage of the semiconductor device higher. On the other hand, by providing the isolation structure 200, after the current enters the first region 104 from the well region 103, it is transmitted along the broken line around the isolation structure 200, that is, the current transmission path is longer, and thus the resistance is greater, which makes the breakdown voltage of the semiconductor device higher. In summary, the breakdown voltage is improved by configuring the path of the current in the first region 104, without extending the path in the epitaxial layer 20 to improve the breakdown voltage. In summary, it can be seen that the semiconductor device of this embodiment can improve the breakdown voltage of the semiconductor device without increasing the thickness of the epitaxial layer 20 in the semiconductor body.

[0055] The technical solution of this embodiment adopts a semiconductor device including a semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a well region and a first region; the first region is configured as a first conductivity type and is located on the first surface, and the well region is configured as a second conductivity type and is located on the first surface; the well region is connected to the first side surface of the first region, and the well region extends to the first bottom surface of the first region and is connected to the first bottom surface; wherein the first bottom surface is opposite to the first surface; the semiconductor body also includes an isolation structure; the isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface; the gate is located on the first surface; the source is located on the first surface, and the portion of the source contacting the first surface is located on the side of the isolation structure away from the first side surface. The breakdown voltage is increased by configuring the current path in the first region, without extending the path in the epitaxial layer to increase the breakdown voltage. The semiconductor device of this embodiment does not require increasing the thickness of the epitaxial layer in the semiconductor body to increase the breakdown voltage of the semiconductor device.

[0056] Optionally, the semiconductor body 100 further includes an isolation trench 105; the isolation trench 105 is located on the first surface 101 and extends from the first surface 101 into the first region 104, with the isolation trench 105 spaced apart from the first side surface 1041; and the isolation structure 200 is located within the isolation trench 105. During semiconductor device manufacturing, the isolation trench 105 can be first formed on the first surface, and then filled into the isolation trench 105 to form the isolation structure 200. The isolation structure 200 can completely fill the isolation trench 105; in other embodiments, it can also partially fill the isolation trench.

[0057] Optionally, the semiconductor body further includes a second region 106 , which is configured as the first conductivity type and is located on the first surface 101 . The second region 106 includes a second bottom surface 1061 opposite the first surface 101 . The second region 106 is located on a side of the isolation trench 105 away from the first side surface 1041 , and the first region 104 covers the second bottom surface 1061 . The ion concentration of the first region 104 is lower than that of the second region 106 . The source 400 is located on the first surface 101 and contacts the second region 106 . Providing the second region 106 can reduce the on-resistance of the semiconductor device.

[0058] Optionally, continue to refer to Figure 1 The isolation trench 105 is spaced apart from the second region 106 .

[0059] Specifically, in this embodiment, the isolation groove 105 does not contact the second region 106, and the two are separated by the first region 104. That is, the side of the second region 106 away from the first side 1041 is also in contact with the first region 104, so that the current can have more paths to enter the second region 106, which is conducive to increasing the current.

[0060] Optionally, Figure 3 A schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, referring to Figure 3 In this embodiment, the isolation trench 105 is connected to the second region 106. In other words, the isolation trench 105 is directly in contact with the second region 106 and is not separated by the first region 104, which is beneficial for reducing the radial size of the semiconductor device.

[0061] Optionally, continue to refer to Figure 1 The semiconductor device further includes a first insulating layer 301; the first insulating layer 301 is located on the first surface 101; the gate 302 is located on a side of the first insulating layer 301 away from the first surface 101; the second region 106 further includes a second side surface 1062 close to the isolation trench 105, and along the thickness direction X of the semiconductor device, the second side surface 1062 is flush with the side surface of the first insulating layer 301.

[0062] Specifically, the first insulating layer 301 serves to isolate the gate 302 from the epitaxial layer 20. The side surface of the first insulating layer 301 is flush with the second side surface 1062 of the second region 106. The semiconductor device is an annular device, that is, the first insulating layer 301 is located within the annular structure surrounded by the second side surface 1062. The vertical projection of the second region 106 on the second surface 102 does not overlap with the vertical projection of the first insulating layer 301 on the second surface 102. The second region 106 does not affect the thickness of the first insulating layer 301, thereby ensuring the stability of the semiconductor device performance. In addition, along the radial direction Y of the semiconductor device, the distance between the second region 106 and the well region 103 is relatively close, which is more conducive to forming a current channel between the second region 106 and the well region 103, thereby reducing the threshold voltage of the semiconductor device.

[0063] Optionally, continue to refer to Figure 1 The depth of the isolation trench 105 is greater than the thickness of the second region 106. This ensures that, in the radial direction Y, current entering the first region 104 from the well region 103 does not directly enter the second region 106, but must bypass the isolation trench 105. This ensures that the current path is extended, thereby increasing the breakdown voltage of the semiconductor device.

[0064] Optionally, continue to refer to Figure 1 Along the thickness direction X of the semiconductor device, the thickness of the first region 104 is 80% to 90% of the maximum thickness of the well region 103 .

[0065] Specifically, the maximum thickness of the well region 103 is the depth of ion implantation performed on the first surface 101 when the well region 103 is formed. If the thickness of the first region 104 is too thick, the thickness of the well region 103 located in the first region 104 near the second surface 102 will be relatively thin, affecting the establishment of the conductive channel. If the first region 104 is too thin, the isolation trench 105 will be too thin, or the portion of the first region 104 located between the isolation trench 105 and the second bottom surface 1061 will be too thin, which will also cause the current in the first region 104 to be too small, affecting the performance of the semiconductor device. In this embodiment, the thickness of the first region 104 is 80% to 90% of the maximum thickness of the well region 103. This ensures that the portion of the well region 103 located in the first region 104 near the second surface 102 has an appropriate thickness, and that the second region 106 and the portion of the first region 104 located between the isolation trench 105 and the second bottom surface 1061 have an appropriate thickness, thereby ensuring that the semiconductor device has better performance.

[0066] Alternatively, continue to refer to Figure 1 Along the thickness direction X of the semiconductor device, the depth of the isolation trench 105 is 30% to 70% of the maximum thickness of the well region 103 .

[0067] Specifically, because the depth of the isolation trench 105 is greater than the thickness of the second region 106, if the depth of the isolation trench 105 is too small, the thickness of the second region 106 will be too small, affecting the formation of the conductive channel. On the other hand, if the depth of the isolation trench 105 is too large, the distance between the isolation trench 105 and the first bottom surface 1042 will be too close. In other words, the first region 104 between the isolation trench 105 and the first bottom surface 1042 will be too thin, and its impedance will be too high, affecting the establishment of the conductive channel.

[0068] Optionally, the material of the isolation structure 200 includes at least one of silicon dioxide and silicon nitride. Both silicon dioxide and silicon nitride have excellent insulating properties. During the semiconductor device manufacturing process, silicon dioxide and silicon nitride are more likely to fully fill the isolation trench 105 and are easier to etch back so that the isolation structure 200 is flush with the first surface 101. Of course, in other embodiments, the isolation structure 200 may also be made of other insulating materials.

[0069] Optionally, continue to refer to Figure 1 The semiconductor body 100 also includes a third region 107, which is set to the second conductivity type and is located on the first surface 101. The ion concentration of the third region 107 is greater than the ion concentration of the well region 103; the third region 107 is located on the side of the first region 104 away from the well region 103.

[0070] Specifically, the third region 107 is, for example, a P+ region. The third region 107 is used to improve the conductivity of the semiconductor device and form a good contact region, thereby improving the performance of the semiconductor device.

[0071] Optionally, continue to refer to Figure 1 The semiconductor device further includes a drain electrode 800, which is located on the second surface 102. The drain electrode 800 may be made of titanium, titanium nitride, or aluminum.

[0072] Optionally, continue to refer to Figure 1 The semiconductor device also includes a packaging structure, which includes a passivation layer 600 and a protective layer 700. The passivation layer 600 is located on the side of the source 400 away from the first surface 101. The protective layer 700 is located on the side of the passivation layer 600 away from the first surface 101. The protective layer 700 covers the passivation layer 600 and the sidewalls of the passivation layer 600 away from the edge of the semiconductor device. The area not encapsulated by the packaging structure is the lead area of ​​the gate 302, and the lead area can electrically connect the gate 302 to the outside. The material of the passivation layer 600 can be silicon dioxide and / or silicon nitride. The material of the protective layer 700 can be, for example, polyimide.

[0073] Optionally, continue to refer to Figure 1 An interlayer dielectric layer 500 is further provided between the gate 302 and the source 400 .

[0074] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device provided by any embodiment of the present invention. Figure 4 As shown, Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention, the manufacturing method comprising:

[0075] Step S101, providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region being in contact with a first side surface of the first region, and the well region extending to and in contact with a first bottom surface of the first region; wherein the first bottom surface is opposite to the first surface;

[0076] Specifically, if Figure 1 As shown, the semiconductor body 100 may include a substrate 10 and an epitaxial layer 20. If the semiconductor device is an N-type device, the first conductivity type is N-type and the second conductivity type is P-type; if the semiconductor device is a P-type device, the first conductivity type is P-type and the second conductivity type is N-type. The well region 103 is, for example, a P-type well region, and the second region 106 is an N-type region. The first surface 101 is also provided with an isolation trench 105. After the current in the semiconductor body 100 enters the well region 103, it first enters the first region 104. Since it cannot pass through the isolation trench 105, it will go around to the bottom surface of the isolation trench 105, and then be transmitted from the bottom surface of the isolation trench 105 to the bottom surface of the second region 106, and then enter the second region 106.

[0077] Step S102, forming an isolation structure, wherein the isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface;

[0078] Specifically, the surface of the isolation structure 200 may be set flush with the first surface 101 . The isolation structure has an insulating property and prevents current from flowing.

[0079] Step S103, forming a gate on the first surface;

[0080] Specifically, the gate 302 is located on a side of the first surface 101 away from the second surface 102 .

[0081] In step S104 , a source electrode is formed on the first surface, wherein a portion of the source electrode in contact with the first surface is located on a side of the isolation structure away from the first side surface.

[0082] Specifically, the source electrode 400 and the first surface form a current channel between the first region 104 and the source electrode 400 .

[0083] The technical solution of this embodiment employs a semiconductor device manufactured using the method for manufacturing a semiconductor device. This method improves the breakdown voltage by configuring the current path within the first region, without extending the path within the epitaxial layer. The semiconductor device of this embodiment improves the breakdown voltage without increasing the thickness of the epitaxial layer within the semiconductor body.

[0084] Optionally, providing the semiconductor body includes: forming an isolation trench on a first surface of the semiconductor body, the isolation trench extending from the first surface to the first region, the isolation trench being spaced apart from the first side surface; and forming the isolation structure includes: forming the isolation structure in the isolation trench.

[0085] Specifically, an isolation trench may be formed by etching, and then the isolation trench may be filled to form an isolation structure, and then back-etched to make the surface of the isolation structure 200 flush with the first surface 101 .

[0086] Optionally, Figure 5-Figure 9 Schematic diagram of the product structure corresponding to the main steps of the method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 5-Figure 9 , providing a semiconductor body including:

[0087] A well region is formed on the first surface of the semiconductor body; a first region is formed on the first surface of the semiconductor body; and a second region is formed on the first surface of the semiconductor body.

[0088] Specifically, if Figure 5 As shown, a substrate 10 and an epitaxial layer 20 may be provided first. Then, ion implantation corresponding to the well region, ion implantation corresponding to the first region, and ion implantation corresponding to the second region are sequentially performed on the first surface 101 to form a well region 103, a first region 104, and a second region 106. Figure 5 As shown, providing a semiconductor body includes: providing a semiconductor body further including a third region, the third region being configured as a second conductivity type and located on the first surface, the ion doping concentration of the third region being greater than the ion doping concentration of the well region; the third region being located on a side of the first region away from the well region. For example, ion implantation corresponding to the third region, i.e., P+ ion implantation, can be performed before ion implantation of the well region to form the third region.

[0089] Then, if Figure 6 As shown, an isolation trench 105 is formed on the first surface of the semiconductor body. For example, the isolation trench 105 can be formed by etching.

[0090] Then, if Figure 7 As shown, the isolation trench 105 is filled with the isolation structure 200 , and then etched back so that the surface of the isolation structure 200 is flush with the first surface 101 .

[0091] Then, if Figure 8 As shown, a first insulating layer 301 and a gate 302 are prepared. The gate 302 is, for example, polysilicon.

[0092] Then, if Figure 1 As shown, an interlayer dielectric layer 500 is formed, and then the first insulating layer 301 is etched to expose the second region 106 and the third region 107. Subsequently, a source electrode 400, a passivation layer 600, a protection layer 700 and a drain electrode 800 are formed.

[0093] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device as described in any of the embodiments of the present invention are not further elaborated here.

[0094] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0095] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device described in the embodiments of the present invention will not be repeated here.

[0096] An embodiment of the present invention further provides a vehicle including a load and a power conversion circuit according to any embodiment of the present invention. The power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention in the vehicle are not further elaborated here.

[0097] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0098] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region being in contact with a first side surface of the first region and extending to and in contact with a first bottom surface of the first region; wherein the first bottom surface is opposite to the first surface; an isolation structure, located on the first surface and extending from the first surface into the first region, the isolation structure being spaced apart from the first side surface; the isolation structure not contacting the first side surface; a gate, located on the first surface; a source electrode, located on the first surface, wherein a portion of the source electrode in contact with the first surface is located on a side of the isolation structure away from the first side surface; The semiconductor body also includes an isolation trench, and the isolation structure is located in the isolation trench; the semiconductor body also includes a second region, the second region is set to a first conductive type and is located on the first surface, the second region includes a second bottom surface opposite to the first surface, the second region is located on the side of the isolation trench away from the first side surface, and the first region is connected to the second bottom surface, the ion concentration of the first region is less than the ion concentration of the second region; the isolation trench and the second region are spaced apart; the isolation trench and the second region are not in contact.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes a first insulating layer; The first insulating layer is located on the first surface; The gate is located on a side of the first insulating layer away from the first surface; The second region further includes a second side surface close to the isolation trench; along the thickness direction of the semiconductor device, the second side surface is flush with a side surface of the first insulating layer.

3. The semiconductor device according to claim 1, wherein The depth of the isolation trench is greater than the thickness of the second region.

4. The semiconductor device according to claim 1, wherein Along the thickness direction of the semiconductor device, the thickness of the first region is 80% to 90% of the maximum thickness of the well region; along the thickness direction of the semiconductor device, the depth of the isolation trench is 30% to 70% of the maximum thickness of the well region.

5. The semiconductor device according to claim 1, wherein The isolation structure is made of at least one of silicon dioxide and silicon nitride.

6. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region being in contact with a first side surface of the first region and extending to and in contact with a first bottom surface of the first region; wherein the first bottom surface is opposite to the first surface; forming an isolation structure, wherein the isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface; forming a gate on the first surface; forming a source electrode on the first surface, wherein a portion of the source electrode in contact with the first surface is located on a side of the isolation structure away from the first side surface; In which, the isolation structure does not contact the first side surface; the semiconductor body also includes an isolation trench, and the isolation structure is located in the isolation trench; the semiconductor body also includes a second region, the second region is set to the first conductive type and is located on the first surface, the second region includes a second bottom surface opposite to the first surface, the second region is located on the side of the isolation trench away from the first side surface, and the first region is connected to the second bottom surface, the ion concentration of the first region is less than the ion concentration of the second region; the isolation trench and the second region are spaced apart; the isolation trench does not contact the second region.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The semiconductor body provided includes: forming an isolation trench on the first surface of the semiconductor body, wherein the isolation trench extends from the first surface into the first region, and the isolation trench is spaced apart from the first side surface; The forming of the isolation structure comprises: The isolation structure is formed in the isolation trench.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The semiconductor body provided includes: forming the well region on the first surface of the semiconductor body; forming the first region on the first surface of the semiconductor body; The isolation trench is formed on the first surface of the semiconductor body.

9. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to any one of claims 1 to 5, wherein the substrate is used to carry the semiconductor device.

10. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that: The invention comprises a load and a power conversion circuit as claimed in claim 10, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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