Low-capacitance electrostatic protection device based on novel structure and manufacturing method thereof

Abstract

The invention provides a low-capacitance electrostatic protection device based on a novel structure and a manufacturing method thereof, the low-capacitance electrostatic protection device comprises a P-type heavily doped substrate and a P-type epitaxial layer, an isolation deep groove, an N-type inversion layer and a P-type heavily doped buried layer which are matched with each other are arranged in the P-type epitaxial layer, the P-type heavily doped buried layer surrounds the isolation deep groove and is divided into two parts by the isolation deep groove, and the N-type inversion layer and the P-type heavily doped buried layer are arranged in the P-type epitaxial layer. The length of the inner side part of the P-type heavily doped substrate is W3, W3 is larger than the thickness of the N-type inversion layer, the lower surface of the P-type heavily doped substrate can be connected with a first I / O port, the upper surface of the P-type epitaxial layer is provided with an N + heavily doped active region which can be connected with a second I / O port, the distance between the N + heavily doped active region and the inner side part of the P-type heavily doped buried layer is W5, the P-type heavily doped buried layer and the N + heavily doped active region form a PN junction, and the P-type heavily doped buried layer and the N + heavily doped active region form a PN junction. The avalanche breakdown voltage of the PN junction can change along with the adjustment of the W5. The electrostatic protection device has the beneficial effects that the electrostatic protection device with ultralow parasitic capacitance and adjustable breakdown voltage can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic protection devices, and in particular to a low-capacitance electrostatic protection device based on a novel structure and a manufacturing method thereof. Background Art

[0002] Electro-Static Discharge (ESD) and Electrical OverStress (EOS) are natural phenomena existing in the application environment of electronic devices. These phenomena can not only cause the failure of electronic devices and greatly reduce the reliability of products, but in severe cases, may even directly cause irreversible damage to electronic devices. One of the effective ways to solve ESD and EOS is to add Transient Voltage Suppressors (TVS) to various interfaces of the system. TVS can provide efficient electrostatic and surge protection for the backend circuit or chip and is a very common electrostatic protection device.

[0003] In recent years, with the increasingly complex system architecture of electronic products, the internal signal transmission frequency of electronic systems has been continuously climbing, and the transmission speed has also become faster and faster. In high-speed signal transmission lines, the presence of capacitance will affect the signal, such as causing signal attenuation and distortion. At this time, it is required that the electrostatic protection device must have low-capacitance characteristics, so as to ensure that the high-speed signal can avoid the damage of ESD and EOS during the transmission process and maintain the signal quality and transmission speed without being interfered by the electrostatic protection device. However, in the prior art, it is often difficult to achieve the low-capacitance characteristics of the electrostatic protection device.

[0004] As shown in FIG. 1(a), for on-chip and off-chip electrostatic protection, avalanche diodes are usually used in the prior art. The negative electrode of the avalanche diode is usually connected to the "I / O or power port", and its positive electrode is usually connected to the "ground port". When a positive ESD pulse comes, the avalanche diode is reverse-biased and avalanche-conducts, and its avalanche breakdown voltage usually needs to be higher than the maximum operating voltage of the port. When a negative ESD pulse comes, the avalanche diode is forward-biased and conducts, equivalent to a forward-biased PN junction. FIG. 1(b) shows the structure of a vertical avalanche diode, which is fabricated on a P-type heavily doped substrate, a P-type epitaxial layer is grown, and then isolation deep trenches and P-type heavily doped active regions are fabricated. Generally speaking, the doping concentration of the P-type epitaxial layer is relatively high to obtain a lower and appropriate avalanche breakdown voltage. At this time, the overall parasitic capacitance of the avalanche diode is relatively large and cannot be used for electrostatic protection of high-speed I / O ports.

[0005] As shown in Figs. 2(a) and 2(b), to reduce the parasitic capacitance of the avalanche diode, a P-type epitaxial layer with high resistivity can be used, thereby reducing the junction capacitance of the P-type heavily doped substrate / P-type epitaxial layer (corresponding to Fig. 2(a), representing the case where "the doping types of the substrate and the epitaxial layer are different") or the junction capacitance of the N-type active region / P-type epitaxial layer (corresponding to Fig. 2(b), representing the case where "the doping types of the substrate and the epitaxial layer are the same"). However, due to the presence of oxide charges C (usually positive charges), an "N-type inversion layer" will be formed on the side of the high-resistance P-type epitaxial layer. These inversion layers are connected to the P-type heavily doped substrate or the N-type heavily doped active region, ultimately equivalently increasing the junction area and introducing an additional parasitic capacitance of the P-type heavily doped substrate or the active region / P-type epitaxial layer, deteriorating the overall parasitic capacitance. At the same time, the avalanche breakdown voltage of the P-type heavily doped substrate or the active region / P-type epitaxial junction will also increase with the increase in the resistivity of the epitaxial layer. An excessively high breakdown voltage cannot meet the effective electrostatic protection requirements for some low-voltage circuit ports, such as the 3.3V / 5V USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface) ports. Therefore, this method also cannot meet the usage requirements of people. Summary of the Invention

[0006] To solve the problems in the prior art, the present invention provides a low-capacitance electrostatic protection device based on a novel structure and a manufacturing method thereof. By arranging a P-type heavily doped substrate, a P-type epitaxial layer, an N-type inversion layer, an isolation deep trench, and a P-type heavily doped buried layer that cooperate with each other in the low-capacitance electrostatic protection device, the P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction, and the avalanche breakdown voltage of the PN junction can vary with the adjustment of W5, effectively shielding the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer due to oxide charges, and solving the problem in the prior art that it is difficult to achieve the low-capacitance characteristic of the electrostatic protection device, resulting in difficulty in meeting the usage requirements of people.

[0007] A low-capacitance electrostatic protection device based on a novel structure provided by the present invention includes a P-type heavily doped substrate and a P-type epitaxial layer arranged from bottom to top. An isolation deep trench, an N-type inversion layer, and a P-type heavily doped buried layer are arranged in the P-type epitaxial layer in a cooperative manner. The top of the isolation deep trench is flush with the upper surface of the P-type epitaxial layer. The bottom of the isolation deep trench penetrates through the P-type epitaxial layer and extends into the P-type heavily doped substrate. The N-type inversion layer is arranged closely along the inner side of the isolation deep trench. The P-type heavily doped buried layer is located at the inner top of the P-type epitaxial layer and its top is flush with the upper surface of the P-type epitaxial layer. The P-type heavily doped buried layer surrounds the isolation deep trench and is divided into two parts by the isolation deep trench. The length of the inner part of the P-type heavily doped buried layer divided by the isolation deep trench is W3, and W3 > the thickness of the N-type inversion layer. The lower surface of the P-type heavily doped substrate can be connected to an I / O port one. An N+-heavily doped active region capable of being connected to an I / O port two is arranged on the upper surface of the P-type epitaxial layer. The distance between the N+-heavily doped active region and the inner part of the P-type heavily doped buried layer is W5, and the value of W5 > 0 mm. The inner part of the P-type heavily doped buried layer can cut off the connection between the N-type inversion layer and the N+-heavily doped active region. The P-type heavily doped buried layer and the N+-heavily doped active region form a PN junction, and the avalanche breakdown voltage of the PN junction can vary with the adjustment of W5.

[0008] In a further improvement of the present invention, the length of the outer part of the P-type heavily doped buried layer divided by the isolation deep trench is W4, and the value of W4 > 0 mm.

[0009] In a further improvement of the present invention, the length of the outer part of the P-type heavily doped buried layer divided by the isolation deep trench is W4, and the value of W4 < 0 mm. At this time, the outer part of the P-type heavily doped buried layer does not exist, and there is a spacing between the inner part of the P-type heavily doped buried layer and the isolation deep trench.

[0010] In a further improvement of the present invention, an insulating oxide layer is also arranged on the upper surface of the P-type epitaxial layer, and the insulating oxide layer is arranged around the N+-heavily doped active region.

[0011] In a further improvement of the present invention, the top of the isolation deep trench is connected to the insulating oxide layer, and the top of the P-type heavily doped buried layer is connected to the insulating oxide layer.

[0012] In a further improvement of the present invention, the I / O port one is a ground port.

[0013] In a further improvement of the present invention, the filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K.

[0014] The present invention also provides a manufacturing method, which is applied to the above-mentioned low-capacitance electrostatic protection device based on a novel structure, and includes:

[0015] Step 1: Prepare a P-type heavily doped substrate, the doping concentration of the P-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ;

[0016] Step 2: Grow a P-type epitaxial layer on the P-type heavily doped substrate, the doping concentration of the P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ;

[0017] Step 3: Fabricate isolation deep trenches;

[0018] Step 4: On the P-type epitaxial layer, form a P-type heavily doped buried layer through ion implantation or diffusion process, and the optional impurity types are boron or boron fluoride;

[0019] Step 5: On the P-type epitaxial layer, fabricate an N+-heavily doped active region through ion implantation or diffusion process, and then perform window opening of contact holes, deposition and etching of metal, and PAD window opening.

[0020] The present invention is further improved. In the step 4, a subsequent drive-in process can be added to adjust the junction depth of the P-type heavily doped buried layer.

[0021] The present invention is further improved. In the step 5, a subsequent drive-in process can also be added to adjust the junction depth of the N+-heavily doped active region.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: It provides a low-capacitance electrostatic protection device based on a novel structure and its manufacturing method. By arranging a mutually cooperating P-type heavily doped substrate, P-type epitaxial layer, N-type inversion layer, isolation deep trenches and P-type heavily doped buried layer in the low-capacitance electrostatic protection device, a PN junction is formed between the P-type heavily doped buried layer and the N+-heavily doped active region. The avalanche breakdown voltage of the PN junction can vary with the adjustment of W5, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer due to oxide charges, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage. Finally, an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for electrostatic and surge protection of high-speed I / O ports, and solves the problem that it is difficult to meet the usage requirements of people due to the difficulty in realizing the low-capacitance characteristics of electrostatic protection devices in the prior art. Description of the Drawings

[0023] To more clearly illustrate the solutions in the present invention or the prior art, the following provides a brief introduction to the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0024] FIG. 1(a) is a schematic diagram of electrostatic protection of a typical existing avalanche diode;

[0025] FIG. 1(b) is a schematic diagram of the structure of a typical existing avalanche diode;

[0026] FIG. 2(a) is a schematic diagram of the structure of an existing low-capacitance vertical avalanche diode with different doping types of the substrate and the epitaxy;

[0027] FIG. 2(b) is a schematic diagram of the structure of an existing low-capacitance vertical avalanche diode with the same doping types of the substrate and the epitaxy;

[0028] Figure 3 FIG. is a schematic diagram of the structure of Embodiment 1 of a low-capacitance electrostatic protection device based on a novel structure of the present invention;

[0029] Figure 4 FIG. is a flowchart of the manufacturing method of Embodiment 1 of a low-capacitance electrostatic protection device based on a novel structure of the present invention. Detailed implementation manners

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "comprising" and "having" and any variations thereof in the specification and claims of the present invention and the above drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the specification and claims of the present invention or the above drawings are used to distinguish different objects and are not used to describe a specific order.

[0031] Referring to "embodiment" herein means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0032] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0033] like Figures 3 - 4 As shown, an embodiment 1 of a low capacitance electrostatic protection device based on a novel structure provided by the present invention comprises a P-type heavily doped substrate 500 and a P-type epitaxial layer 510 arranged from bottom to top, wherein the P-type epitaxial layer 510 is provided with a matching isolation deep trench 511, an N-type inversion layer 515 and a P-type heavily doped buried layer 513, wherein the top of the isolation deep trench 511 is flush with the upper surface of the P-type epitaxial layer 510, the bottom of the isolation deep trench 511 passes through the P-type epitaxial layer 510 and extends into the P-type heavily doped substrate 500, the N-type inversion layer 515 is arranged close to the inner side of the isolation deep trench 511, the P-type heavily doped buried layer 513 is located at the top of the P-type epitaxial layer 510 and the top is flush with the upper surface of the P-type epitaxial layer 510, the P-type heavily doped buried layer 513 surrounds the isolation deep trench 511 and is surrounded by the isolation deep trench The groove 511 is divided into two parts, and the inner part of the P-type heavily doped buried layer 513 divided by the isolation deep groove 511 has a length of W3, W3> the thickness of the N-type inversion layer 515, the lower surface of the P-type heavily doped substrate 500 can be connected to the I / O port one, and the upper surface of the P-type epitaxial layer 510 is provided with an N+ heavily doped active area 512 that can be connected to the I / O port two, and the distance between the N+ heavily doped active area 512 and the inner part of the P-type heavily doped buried layer 513 is W5, and the value of W5 is> 0mm. The inner part of the P-type heavily doped buried layer 513 can cut off the connection between the N-type inversion layer 515 and the N+ heavily doped active area 512, and the P-type heavily doped buried layer 513 and the N+ heavily doped active area 512 form a PN junction, and the avalanche breakdown voltage of the PN junction can change with the adjustment of W5. In this embodiment, the P-type heavily doped buried layer is manufactured by default surrounding the isolation deep trench on the layout, wherein the size of W3 needs to exceed the thickness of the N-type inversion layer to completely block the connection between the N-type inversion layer and the N+ heavily doped active area; the length of the outer portion of the P-type heavily doped buried layer 513 divided by the isolation deep trench 511 is W4, and the value of the W4 size can be positive or negative. When it is a negative value, it means that the P-type heavily doped buried layer and the isolation deep trench do not overlap at this time, that is, the outer portion of the P-type heavily doped buried layer does not exist at this time, and there is a gap between the inner portion of the P-type heavily doped buried layer and the isolation deep trench; adjusting the value of W5 can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer caused by the oxide charge, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage, and finally can realize an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage, which is particularly suitable for electrostatic and surge protection of high-speed I / O ports.

[0034] like Figures 3 - 4As shown in the figure, an insulating oxide layer 514 is further provided on the upper surface of the P-type epitaxial layer 510. The insulating oxide layer 514 is disposed around the N+ heavily doped active region 512. The top of the isolation deep trench 511 is connected to the insulating oxide layer 514, and the top of the P-type heavily doped buried layer 513 is connected to the insulating oxide layer 514. The first I / O port is a ground port.

[0035] As Figure 4 shown, the manufacturing method of Embodiment 1 of the present invention includes:

[0036] Step 1: Prepare a P-type heavily doped substrate 500. The doping concentration of the P-type heavily doped substrate 500 is C1. The doping concentration of the P-type heavily doped substrate is usually high. In this embodiment, the value range of C1 is 10 19 cm -3 ≤ C1 ≤ 10 21 cm -3 ;

[0037] Step 2: Grow a P-type epitaxial layer 510 on the P-type heavily doped substrate 500. The doping concentration of the P-type epitaxial layer 510 is C2. To reduce the capacitance, its doping concentration needs to be very low. In this embodiment, the value range of C2 is 10 13 cm -3 ≤ C1 ≤ 10 16 cm -3 ;

[0038] Step 3: Manufacture the isolation deep trench 511. The filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K;

[0039] Step 4: On the P-type epitaxial layer 510, form a P-type heavily doped buried layer 513 by ion implantation or diffusion process. The optional impurity types are boron or boron fluoride. A subsequent drive-in process can be added to control the junction depth of the P-type heavily doped buried layer 513;

[0040] Step 5: On the P-type epitaxial layer 510, manufacture an N+ heavily doped active region 512 by ion implantation or diffusion process. A subsequent drive-in process can also be added to control the junction depth of the N+ heavily doped active region 512. Then, a typical back-end process (BEOL) is performed, including the opening of contact holes, the deposition and etching of metals, and the opening of PADs.

[0041] The manufacturing process of a low-capacitance electrostatic protection device based on a novel structure according to the present invention is applicable to various common integrated circuit manufacturing processes, such as nanoscale complementary metal oxide semiconductor (CMOS) process, three-dimensional fin field-effect transistor (FinFET) or gate-all-around FET (GAA) process, or silicon-on-insulator (SOI) process, etc.

[0042] As can be seen from the above, the present invention provides a low-capacitance electrostatic protection device based on a novel structure and its manufacturing method. By arranging a P-type heavily doped substrate, a P-type epitaxial layer, an N-type inversion layer, an isolation deep trench and a P-type heavily doped buried layer that cooperate with each other in the low-capacitance electrostatic protection device, a PN junction is formed between the P-type heavily doped buried layer and the N+ heavily doped active region. The avalanche breakdown voltage of the PN junction can vary with the adjustment of W5, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer due to oxide charges, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage. Finally, an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for electrostatic and surge protection of high-speed I / O ports, and solves the problem in the prior art that it is difficult to achieve the low-capacitance characteristic of the electrostatic protection device, resulting in difficulty in meeting people's usage requirements.

[0043] The above-mentioned specific implementation manners are the preferred implementation manners of the present invention, and do not limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to this specific implementation manner. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A low-capacitance electrostatic protection device based on a novel structure, characterized in that: The invention comprises a P-type heavily doped substrate and a P-type epitaxial layer arranged from bottom to top, wherein the P-type epitaxial layer is provided with a matching isolation deep trench, an N-type inversion layer and a P-type heavily doped buried layer, the top of the isolation deep trench is flush with the upper surface of the P-type epitaxial layer, the bottom of the isolation deep trench passes through the P-type epitaxial layer and extends into the P-type heavily doped substrate, the N-type inversion layer is arranged close to the inner side of the isolation deep trench, the P-type heavily doped buried layer is located at the top of the P-type epitaxial layer and the top is flush with the upper surface of the P-type epitaxial layer, the P-type heavily doped buried layer surrounds the isolation deep trench and is divided into two parts by the isolation deep trench, and the P-type heavily doped buried layer is surrounded by the isolation deep trench. The length of the inner part separated from the deep trench is W3, W3>the thickness of the N-type inversion layer, the lower surface of the P-type heavily doped substrate can be connected to I / O port one, the upper surface of the P-type epitaxial layer is provided with an N+ heavily doped active area that can be connected to I / O port two, the distance between the N+ heavily doped active area and the inner part of the P-type heavily doped buried layer is W5, the value of W5 is>0mm, the inner part of the P-type heavily doped buried layer can cut off the connection between the N-type inversion layer and the N+ heavily doped active area, the P-type heavily doped buried layer and the N+ heavily doped active area form a PN junction, and the avalanche breakdown voltage of the PN junction can change with the adjustment of W5.

2. The low-capacitance electrostatic protection device based on the novel structure according to claim 1, characterized in that: The length of the outer portion of the P-type heavily doped buried layer divided by the isolation deep trench is W4, and the value of W4 is greater than 0 mm.

3. The low-capacitance electrostatic protection device based on the novel structure according to claim 1, characterized in that: The length of the outer part of the P-type heavily doped buried layer divided by the isolation deep trench is W4, and the value of W4 is <0mm. At this time, the outer part of the P-type heavily doped buried layer does not exist, and there is a distance between the inner part of the P-type heavily doped buried layer and the isolation deep trench.

4. The low-capacitance electrostatic protection device based on the novel structure according to any one of claims 2 or 3, characterized in that: An insulating oxide layer is also provided on the upper surface of the P-type epitaxial layer, and the insulating oxide layer is arranged around the N+ heavily doped active region.

5. The low-capacitance electrostatic protection device based on the novel structure according to claim 4, characterized in that: The top of the isolation deep trench is connected to the insulating oxide layer, and the top of the P-type heavily doped buried layer is connected to the insulating oxide layer.

6. The low-capacitance electrostatic protection device based on the novel structure according to claim 5, characterized in that: The I / O port 1 is a ground port.

7. The low-capacitance electrostatic protection device based on the novel structure according to claim 6, wherein: The filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K.

8. A manufacturing method, applied to the low-capacitance electrostatic protection device based on the novel structure according to any one of claims 5-7, characterized in that, include: Step 1, prepare a P-type heavily doped substrate, the doping concentration of the P-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤ C1 ≤ 10 21 cm -3 ; Step 2: Grow a P-type epitaxial layer on the P-type heavily doped substrate. The doping concentration of the P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 3, manufacturing isolation deep trenches; Step 4, forming a P-type heavily doped buried layer on the P-type epitaxial layer by ion implantation or diffusion process, wherein the optional impurity type is boron or boron fluoride; Step 5: On the P-type epitaxial layer, an N+ heavily doped active area is manufactured by ion implantation or diffusion process, and then contact holes are opened, metal is deposited and etched, and PAD windows are opened.

9. The manufacturing method according to claim 8, characterized in that: In step 4, a subsequent junction pushing process may be added to adjust the junction depth of the P-type heavily doped buried layer.

10. The manufacturing method according to claim 9, characterized in that: In step 5, a subsequent junction-pushing process may also be added to adjust the junction depth of the N+ heavily doped active region.

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