Low capacitance electrostatic discharge protection device based on novel structure and method of manufacturing the same

Abstract

The application provides a low capacitance electrostatic protection device based on a novel structure and a manufacturing method thereof, which comprises a P-type heavily doped substrate and a P-type epitaxial layer, the P-type epitaxial layer is provided with a matching isolation deep groove, an N-type inversion layer and a P-type heavily doped buried layer, the P-type heavily doped buried layer is arranged around the isolation deep groove and is divided into two parts by the isolation deep groove, the inner part has a length of W3, W3>N-type inversion layer thickness, the lower surface of the P-type heavily doped substrate can be connected with an I / O port 1, the upper surface of the P-type epitaxial layer is provided with an N+ heavily doped active region which can be connected with an I / O port 2, the distance between the N+ heavily doped active region and the inner part of the P-type heavily doped buried layer is W5, the P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction, and the avalanche breakdown voltage of the PN junction can be changed by adjusting W5. The application has the beneficial effect that the electrostatic protection device with super low parasitic capacitance and adjustable breakdown voltage can be realized.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection device technology, and specifically to a low-capacitance ESD protection device based on a novel structure and its manufacturing method. Background Technology

[0002] Electrostatic discharge (ESD) and electrical overstress (EOS) are natural phenomena in the environments in which electronic equipment is used. These phenomena can not only cause electronic equipment to fail and significantly reduce product reliability, but in severe cases, they can even cause irreversible damage to the electronic equipment. One effective way to solve ESD and EOS is to add transient voltage suppressors (TVS) to various interfaces of the system. TVS can provide highly efficient electrostatic and surge protection for back-end circuits or chips and is a very common electrostatic protection device.

[0003] In recent years, with the increasingly complex system architecture of electronic products, the signal transmission frequency within electronic systems has continued to rise, and the transmission speed has become increasingly faster. In high-speed signal transmission lines, the presence of capacitance can affect the signal, causing attenuation and distortion. Therefore, electrostatic discharge (ESD) protection devices must possess low capacitance characteristics to ensure that high-speed signals are protected from ESD and EOS damage during transmission, while maintaining signal quality and transmission speed unaffected by ESD interference. However, in existing technologies, achieving low capacitance characteristics in ESD protection devices is often difficult.

[0004] As shown in Figure 1(a), avalanche diodes are commonly used in existing technologies for on-chip and off-chip ESD protection. The negative terminal of an avalanche diode is typically connected to an "I / O or power port," while its positive terminal is typically connected to a "ground port." When a positive ESD pulse arrives, the avalanche diode is reverse-biased and conducts avalanche, and its avalanche breakdown voltage typically needs to be higher than the maximum operating voltage of the port. When a negative ESD pulse arrives, the avalanche diode is forward-biased and conducts, equivalent to a forward-biased PN junction. Figure 1(b) shows the structure of a vertical avalanche diode, fabricated on a heavily doped P-type substrate, where a P-type epitaxial layer is grown, followed by the fabrication of isolation trenches and heavily doped P-type active regions. Typically, the P-type epitaxial layer has a high doping concentration to obtain a low and suitable avalanche breakdown voltage. However, this results in a large overall parasitic capacitance for the avalanche diode, making it unsuitable for ESD protection of high-speed I / O ports.

[0005] As shown in Figures 2(a) and 2(b), to reduce the parasitic capacitance of the avalanche diode, a high-resistivity P-type epitaxial layer can be used, thereby reducing the junction capacitance of the heavily doped P-type substrate / P-type epitaxial layer (corresponding to Figure 2(a), representing the case where "the doping types of the substrate and the epitaxial layer are different") or the junction capacitance of the N-type active region / P-type epitaxial layer (corresponding to Figure 2(b), representing the case where "the doping types of the substrate and the epitaxial layer are the same"). However, due to the presence of oxide charge C (usually positive charge), an "N-type inversion layer" is formed on the high-resistivity P-type epitaxial side. These inversion layers are connected to the heavily doped P-type substrate or the heavily doped N-type active region, ultimately effectively increasing the junction area and introducing additional parasitic capacitance of the heavily doped P-type substrate or the active region / P-type epitaxial layer, thus worsening the overall parasitic capacitance. At the same time, the avalanche breakdown voltage of the P-type heavily doped substrate or active region / P-type epitaxial junction will also increase with the increase of epitaxial layer resistivity. The excessively high breakdown voltage cannot meet the effective electrostatic protection of some low-voltage circuit ports, such as 3.3V / 5V USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface) ports. Therefore, this method cannot meet people's usage needs. Summary of the Invention

[0006] To address the problems in existing technologies, this invention provides a low-capacitance electrostatic discharge (ESD) protection device based on a novel structure and its manufacturing method. The device comprises a P-type heavily doped substrate, a P-type epitaxial layer, an N-type inversion layer, an isolation deep trench, and a P-type heavily doped buried layer. The P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction. The avalanche breakdown voltage of the PN junction can vary with the adjustment of W5, effectively shielding the N-type inversion layer from degrading the capacitance of the ESD protection device due to oxide charge. This solves the problem in existing technologies where achieving low capacitance characteristics in ESD protection devices is difficult, thus failing to meet user needs.

[0007] This invention provides a low-capacitance electrostatic discharge (ESD) protection device based on a novel structure, comprising a P-type heavily doped substrate and a P-type epitaxial layer arranged from bottom to top. The P-type epitaxial layer contains a cooperating isolation deep trench, an N-type inversion layer, and a P-type heavily doped buried layer. The top of the isolation deep trench is flush with the upper surface of the P-type epitaxial layer, and the bottom of the isolation deep trench passes through the P-type epitaxial layer and extends into the P-type heavily doped substrate. The N-type inversion layer is disposed adjacent to the inner side of the isolation deep trench. The P-type heavily doped buried layer is located at the top of the P-type epitaxial layer, and its top is flush with the upper surface of the P-type epitaxial layer. The P-type heavily doped buried layer surrounds the isolation deep trench and is divided into two parts by the isolation deep trench. The inner portion of the P-type heavily doped buried layer, divided by the isolation trench, has a length of W3, where W3 is greater than the thickness of the N-type inversion layer. The lower surface of the P-type heavily doped substrate can be connected to I / O port one. The upper surface of the P-type epitaxial layer has an N+ heavily doped active region that can be connected to I / O port two. The distance between the N+ heavily doped active region and the inner portion of the P-type heavily doped buried layer is W5, where W5 is greater than 0 mm. The inner portion of the P-type heavily doped buried layer can isolate the connection between the N-type inversion layer and the N+ heavily doped active region. The P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction, and the avalanche breakdown voltage of the PN junction can be varied with the adjustment of W5.

[0008] In a further improvement to the present invention, the length of the outer portion of the P-type heavily doped buried layer divided by the isolation deep trench is W4, and the value of W4 is > 0 mm.

[0009] In a further improvement to the present invention, the length of the outer portion of the P-type heavily doped buried layer divided by the isolation deep trench is W4, and the value of W4 is <0 mm. At this time, the outer portion of the P-type heavily doped buried layer does not exist, and there is a gap between the inner portion of the P-type heavily doped buried layer and the isolation deep trench.

[0010] In a further improvement of the present invention, an insulating oxide layer is provided on the upper surface of the P-type epitaxial layer, and the insulating oxide layer is disposed around the N+ heavily doped active region.

[0011] In a further improvement to the present invention, the top of the isolation deep trench is connected to the insulating oxide layer, and the top of the P-type heavily doped buried layer is connected to the insulating oxide layer.

[0012] In a further improvement to this invention, one of the I / O ports is a ground port.

[0013] In a further improvement to the present invention, the filling material in the isolation deep trench is silicon dioxide, silicon nitride, or High-K.

[0014] The present invention also provides a manufacturing method for the above-mentioned low capacitance electrostatic protection device based on the novel structure, comprising:

[0015] Step 1: Prepare a heavily doped P-type substrate with a doping concentration of C1, where C1 ranges from 10. 19 cm -3 ≤C1≤10 21 cm -3 ;

[0016] Step 2: Grow a P-type epitaxial layer on a heavily doped P-type substrate. The doping concentration of the P-type epitaxial layer is C2, and the value of C2 ranges from 10. 13 cm -3 ≤C1≤10 16 cm -3 ;

[0017] Step 3: Fabricate the isolation trench;

[0018] Step 4: On the P-type epitaxial layer, a heavily doped P-type buried layer is formed by ion implantation or diffusion process. The impurity can be boron or boron fluoride.

[0019] Step 5: On the P-type epitaxial layer, an N+ heavily doped active region is fabricated by ion implantation or diffusion process, followed by contact hole opening, metal deposition and etching, and PAD opening.

[0020] In a further improvement to the present invention, a subsequent push-in process can be added in step 4 to control the junction depth of the heavily doped P-type buried layer.

[0021] In a further improvement to the present invention, a subsequent junction push-in process can be added to step 5 to control the junction depth of the N+ heavily doped active region.

[0022] Compared with the prior art, the beneficial effects of the present invention are: it provides a low-capacitance electrostatic discharge (ESD) protection device based on a novel structure and its manufacturing method. By setting mutually cooperating P-type heavily doped substrate, P-type epitaxial layer, N-type inversion layer, isolation deep trench and P-type heavily doped buried layer in the low-capacitance ESD protection device, the P-type heavily doped buried layer and N+ heavily doped active region form a PN junction. The avalanche breakdown voltage of the PN junction can be changed with the adjustment of W5, which can effectively shield the deterioration of the capacitance of the ESD protection device caused by the N-type inversion layer due to oxide charge, and can solve the contradiction between parasitic capacitance and avalanche breakdown voltage. Finally, an ESD protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for ESD and surge protection of high-speed I / O ports. It solves the problem that the low capacitance characteristics of ESD protection devices in the prior art are difficult to achieve, which makes it difficult to meet people's needs. Attached Figure Description

[0023] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1(a) is a schematic diagram of the electrostatic protection of a typical existing avalanche diode;

[0025] Figure 1(b) is a schematic diagram of a typical existing avalanche diode structure;

[0026] Figure 2(a) is a schematic diagram of the existing low-capacitance longitudinal avalanche diode with different substrate and epitaxial doping types;

[0027] Figure 2(b) is a schematic diagram of the existing low-capacitance longitudinal avalanche diode with the same doping type as the substrate and epitaxial layer.

[0028] Figure 3 This is a schematic diagram of a first embodiment of the low capacitance electrostatic protection device based on the novel structure of the present invention;

[0029] Figure 4 This is a flowchart illustrating the manufacturing method of a first embodiment of the low-capacitance electrostatic protection device based on a novel structure according to the present invention. Detailed Implementation

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein and in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects and not to describe a particular order.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0033] like Figures 3-4 The image shows an embodiment of a low-capacitance electrostatic discharge (ESD) protection device based on a novel structure provided by the present invention. It includes a P-type heavily doped substrate 500 and a P-type epitaxial layer 510 arranged from bottom to top. The P-type epitaxial layer 510 contains a cooperating isolation deep trench 511, an N-type inversion layer 515, and a P-type heavily doped buried layer 513. The top of the isolation deep trench 511 is flush with the upper surface of the P-type epitaxial layer 510, and the bottom of the isolation deep trench 511 passes through the P-type epitaxial layer 510 and extends into the P-type heavily doped substrate 500. The N-type inversion layer 515 is disposed close to the inner side of the isolation deep trench 511. The P-type heavily doped buried layer 513 is located at the top of the P-type epitaxial layer 510, and its top is flush with the upper surface of the P-type epitaxial layer 510. The P-type heavily doped buried layer 513 surrounds the isolation deep trench 511 and is deeply isolated. The trench 511 is divided into two parts. The inner part of the deep trench 511 is isolated by the P-type heavily doped buried layer 513. The length of the inner part is W3, where W3 is greater than the thickness of the N-type inversion layer 515. The lower surface of the P-type heavily doped substrate 500 can be connected to I / O port one. The upper surface of the P-type epitaxial layer 510 is provided with an N+ heavily doped active region 512 that can be connected to I / O port two. The distance between the N+ heavily doped active region 512 and the inner part of the P-type heavily doped buried layer 513 is W5, where W5 is greater than 0 mm. The inner part of the P-type heavily doped buried layer 513 can isolate the connection between the N-type inversion layer 515 and the N+ heavily doped active region 512. The P-type heavily doped buried layer 513 and the N+ heavily doped active region 512 form a PN junction. The avalanche breakdown voltage of the PN junction can be changed with the adjustment of W5. In this embodiment, the P-type heavily doped buried layer is fabricated by default to surround the isolation trench on the layout. The size of W3 needs to exceed the thickness of the N-type inversion layer to completely block the connection between the N-type inversion layer and the N+ heavily doped active region. The length of the outer part of the P-type heavily doped buried layer 513 divided by the isolation trench 511 is W4. The value of W4 can be positive or negative. When it is negative, it means that the P-type heavily doped buried layer and the isolation trench do not overlap. That is, the outer part of the P-type heavily doped buried layer does not exist, and there is a gap between the inner part of the P-type heavily doped buried layer and the isolation trench. Adjusting the value of W5 can effectively shield the N-type inversion layer caused by oxide charge from degrading the capacitance of the electrostatic protection device, and can solve the contradiction between parasitic capacitance and avalanche breakdown voltage. Finally, an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for electrostatic and surge protection of high-speed I / O ports.

[0034] like Figures 3-4As shown, the upper surface of the P-type epitaxial layer 510 is also provided with an insulating oxide layer 514. The insulating oxide layer 514 is arranged around the N+ heavily doped active region 512. The top of the isolation deep trench 511 is connected to the insulating oxide layer 514. The top of the P-type heavily doped buried layer 513 is connected to the insulating oxide layer 514. I / O port one is a ground port.

[0035] like Figure 4 The diagram shows a manufacturing method according to Embodiment 1 of the present invention, comprising:

[0036] Step 1: Prepare a heavily doped P-type substrate 500. The doping concentration of the heavily doped P-type substrate 500 is C1. The doping concentration of heavily doped P-type substrates is usually quite high. In this embodiment, the value of C1 ranges from 10. 19 cm -3 ≤C1≤10 21 cm -3 ;

[0037] Step 2: Grow a P-type epitaxial layer 510 on a heavily doped P-type substrate 500. The doping concentration of the P-type epitaxial layer 510 is C2. To reduce capacitance, its doping concentration needs to be very low. In this embodiment, the value of C2 is in the range of 10. 13 cm -3 ≤C1≤10 16 cm -3 ;

[0038] Step 3: Fabricate the isolation deep trench 511. The filling material inside the isolation deep trench is silicon dioxide, silicon nitride, or High-K.

[0039] Step 4: On the P-type epitaxial layer 510, a heavily doped P-type buried layer 513 is formed by ion implantation or diffusion process. The impurity can be boron or boron fluoride. A subsequent push-over process can be added to control the junction depth of the heavily doped P-type buried layer 513.

[0040] Step 5: On the P-type epitaxial layer 510, an N+ heavily doped active region 512 is fabricated by ion implantation or diffusion process. A subsequent push-junction process can also be added to control the junction depth of the N+ heavily doped active region 512. Then, a typical back-end process (BEOL) is performed, including opening of contact holes, metal deposition and etching, and opening of PADs.

[0041] The manufacturing process of a low-capacitance electrostatic discharge protection device based on a novel structure, as described in this invention, is applicable to various common integrated circuit manufacturing processes, such as nanoscale complementary metal-oxide-semiconductor (CMOS) technology, three-dimensional fin field-effect transistor (FinFET) or gate-all-around FET (GAA) technology, or silicon-on-insulator (SOI) technology, etc.

[0042] As can be seen from the above, the present invention provides a low-capacitance electrostatic discharge (ESD) protection device based on a novel structure and its manufacturing method. By setting a P-type heavily doped substrate, a P-type epitaxial layer, an N-type inversion layer, an isolation deep trench, and a P-type heavily doped buried layer in the low-capacitance ESD protection device, the P-type heavily doped buried layer and the N+ heavily doped active region form a PN junction. The avalanche breakdown voltage of the PN junction can be changed with the adjustment of W5, which can effectively shield the deterioration of the capacitance of the ESD protection device caused by the N-type inversion layer due to oxide charge, and can solve the contradiction between parasitic capacitance and avalanche breakdown voltage. Finally, an ESD protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for ESD and surge protection of high-speed I / O ports. It solves the problem that the low capacitance characteristics of existing ESD protection devices are difficult to achieve, which makes it difficult to meet people's needs.

[0043] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A low-capacitance electrostatic protection device based on a novel structure, characterized in that: The system comprises a heavily doped P-type substrate and a P-type epitaxial layer arranged from bottom to top. The P-type epitaxial layer contains a cooperating isolation trench, an N-type inversion layer, and a heavily doped P-type buried layer. The top of the isolation trench is flush with the upper surface of the P-type epitaxial layer, and the bottom of the isolation trench penetrates the P-type epitaxial layer and extends into the heavily doped P-type substrate. The N-type inversion layer is disposed adjacent to the inner side of the isolation trench. The heavily doped P-type buried layer is located at the top of the P-type epitaxial layer, with its top flush with the upper surface of the P-type epitaxial layer. The heavily doped P-type buried layer surrounds the isolation trench and is divided into two parts by the isolation trench. The length of the inner portion separated from the deep trench is W3, where W3 is greater than the thickness of the N-type inversion layer. The lower surface of the heavily doped P-type substrate can be connected to I / O port one. The upper surface of the P-type epitaxial layer is provided with an N+ heavily doped active region that can be connected to I / O port two. The distance between the N+ heavily doped active region and the inner portion of the heavily doped P-type buried layer is W5, where W5 is greater than 0 mm. The inner portion of the heavily doped P-type buried layer can isolate the connection between the N-type inversion layer and the N+ heavily doped active region. The heavily doped P-type buried layer and the N+ heavily doped active region form a PN junction. The avalanche breakdown voltage of the PN junction can be varied with the adjustment of W5.

2. The low-capacitance electrostatic protection device based on a novel structure according to claim 1, characterized in that: The outer portion of the P-type heavily doped buried layer, which is divided by the isolation trench, has a length of W4, where W4 is greater than 0 mm.

3. The low-capacitance electrostatic protection device based on a novel structure according to claim 1, characterized in that: The outer portion of the heavily doped P-type buried layer divided by the isolation trench has a length of W4, where W4 is less than 0 mm. In this case, the outer portion of the heavily doped P-type buried layer does not exist, and there is a gap between the inner portion of the heavily doped P-type buried layer and the isolation trench.

4. The low-capacitance electrostatic protection device based on the novel structure according to any one of claims 2 or 3, characterized in that: The upper surface of the P-type epitaxial layer is further provided with an insulating oxide layer, which surrounds the N+ heavily doped active region.

5. The low-capacitance electrostatic protection device based on the novel structure according to claim 4, characterized in that: The top of the isolation trench is in contact with the insulating oxide layer, and the top of the P-type heavily doped buried layer is in contact with the insulating oxide layer.

6. The low-capacitance electrostatic protection device based on the novel structure according to claim 5, characterized in that: One of the I / O ports is a grounding port.

7. The low-capacitance electrostatic protection device based on the novel structure according to claim 6, characterized in that: The filling material in the isolation trench is silicon dioxide, silicon nitride, or High-K.

8. A manufacturing method applied to the low-capacitance electrostatic protection device based on the novel structure according to any one of claims 5-7, characterized in that, include: Step 1: Prepare a heavily doped P-type substrate with a doping concentration of C1, where C1 ranges from 10. 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: Grow a P-type epitaxial layer on a heavily doped P-type substrate. The doping concentration of the P-type epitaxial layer is C2, and the value of C2 ranges from 10. 13 cm -3 ≤C1≤10 16 cm -3 ; Step 3: Fabricate the isolation trench; Step 4: On the P-type epitaxial layer, a heavily doped P-type buried layer is formed by ion implantation or diffusion process. The impurity can be boron or boron fluoride. Step 5: On the P-type epitaxial layer, an N+ heavily doped active region is fabricated by ion implantation or diffusion process, followed by contact hole opening, metal deposition and etching, and PAD opening.

9. The manufacturing method according to claim 8, characterized in that: In step 4, a subsequent push-in process can be added to control the junction depth of the heavily doped P-type buried layer.

10. The manufacturing method according to claim 9, characterized in that: In step 5, a subsequent junction push-in process can also be added to control the junction depth of the N+ heavily doped active region.

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