Preparation method of image sensor
By forming a metal silicide barrier structure during the image sensor preparation process, the white noise pixel problem caused by metal impurities in the CIS device is solved, and the effect of reducing dark current and improving yield is achieved.
Patent Information
- Application Number
- CN202510379671.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-08
AI Technical Summary
There are many metal impurities in CIS devices, resulting in a large number of white noise pixels, resulting in dark currents, affecting the device yield.
During the preparation of the image sensor, the first silicide barrier layer is first formed and the doped ions are activated by thermal annealing. Then, the second silicide barrier layer is deposited by furnace tube LPCVD process to form a metal silicide barrier structure to avoid plasma contamination and metal impurity contamination.
Effectively reduce the number of white noise pixels, avoid dark current generation, and improve device yield.
Smart Images
Figure CN120282560A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly relates to a method for manufacturing an image sensor. Background Art
[0002] With the booming development of the consumer electronics market, CIS (COMS Image Sensor) devices have been widely used in fields such as mobile phone cameras / security and environmental monitoring. In order to obtain better shooting effects, the requirements for CIS devices are getting higher and higher.
[0003] The number of white noise pixels is one of the key parameters for evaluating the performance of CIS devices. During the chip manufacturing process, it is inevitably affected by various factors such as process fluctuations, raw material changes, and metal contamination, resulting in the generation of charge by pixel points themselves even without light. As the charge accumulates and aggregates, it will form dark current. For a pixel, when the dark current value exceeds the photocurrent generated by capturing photons, the pixel point is defaulted as a white noise pixel by the control circuit. The output of white noise pixels is generally much higher than the average output of all pixels in the dark field. Pixels with an output generally 64DN higher than the average output of all pixels are called white noise pixels.
[0004] Metal contamination in the chip is an important factor for generating dark current. With the continuous miniaturization of the pixel area size, how to better reduce metal impurities in CIS devices and reduce the number of white noise pixels poses a new challenge to the manufacturing process of CIS devices. Summary of the Invention
[0005] The present application provides a method for manufacturing an image sensor, which can solve the problem that there are more metal impurities and more white noise pixels in CIS devices, resulting in the generation of dark current in the devices and affecting the yield of the devices.
[0006] An embodiment of the present application provides a method for manufacturing an image sensor, including:
[0007] Providing a substrate, the substrate includes a plurality of device regions, and a plurality of shallow trench isolation structures are formed in the substrate. The shallow trench isolation structures are used to isolate different device regions, and a gate structure and sidewall structures located on both sides of the gate structure are formed on the substrate of each device region;
[0008] Performing ion implantation on the substrate on both sides of the sidewall structures to form source regions and drain regions in the substrate of each device region;
[0009] Forming a first silicide blocking layer, the first silicide blocking layer covering the gate structure, the sidewall structures and the substrate;
[0010] Thermally anneal the semiconductor structure after forming the first silicide barrier layer to activate the doped ions in the source region and the drain region;
[0011] Form a second silicide barrier layer by furnace LPCVD process, and the second silicide barrier layer covers the first silicide barrier layer.
[0012] Optionally, in the method for manufacturing the image sensor, during the process of forming the second silicide barrier layer by furnace LPCVD process, the chamber pressure is 0.1 Torr to 2 Torr; the chamber temperature is: 580 °C to 650 °C; the gases participating in the reaction at least include: DCS gas and NH3; the process duration is: 90 min to 170 min.
[0013] Optionally, in the method for manufacturing the image sensor, during the process of forming the second silicide barrier layer by furnace LPCVD process, the flow rate of DCS gas is 100 sccm to 300 sccm; the flow rate of NH3 is 300 sccm to 1000 sccm.
[0014] Optionally, in the method for manufacturing the image sensor, the thickness of the second silicide barrier layer is 200 Å to 650 Å.
[0015] Optionally, in the method for manufacturing the image sensor, the first silicide barrier layer is formed by CVD process.
[0016] Optionally, in the method for manufacturing the image sensor, the thickness of the first silicide barrier layer is 100 Å to 300 Å.
[0017] Optionally, in the method for manufacturing the image sensor, nitrogen gas is introduced into the process chamber, and a spike thermal annealing process is performed on the semiconductor structure after forming the first silicide barrier layer.
[0018] Optionally, in the method for manufacturing the image sensor, during the process of performing the spike thermal annealing process on the semiconductor structure after forming the first silicide barrier layer, the flow rate of nitrogen gas is 10 slm to 40 slm; the process temperature is 1000 °C to 1200 °C; the duration is 1 s to 2 s.
[0019] Optionally, in the method for manufacturing the image sensor, after forming the second silicide barrier layer by furnace LPCVD process, the method for manufacturing the image sensor further includes:
[0020] Etch the second silicide barrier layer and the first silicide barrier layer at the top of the gate structure, and etch the second silicide barrier layer and the first silicide barrier layer above the source region and the drain region.
[0021] The technical solution of this application has at least the following advantages:
[0022] In this application, after the source region and the drain region are formed by ion implantation, a first silicide barrier layer is first deposited, and then the doped ions in the source region and the drain region are activated by thermal annealing. Finally, a dense second silicide barrier layer is deposited by a furnace tube LPCVD (low-pressure chemical vapor deposition) process, so that the first silicide barrier layer and the second silicide barrier layer constitute the final metal silicide barrier structure. In this application, the final metal silicide barrier structure is composed of the first silicide barrier layer and the second silicide barrier layer. The metal silicide barrier structure of this application can avoid introducing plasma during the formation of the second silicide barrier layer by the traditional PECVD (plasma-enhanced chemical vapor deposition) process, thus avoiding plasma contamination of the gate structure and the substrate, and can effectively prevent metal impurity contamination brought during the subsequent contact hole process and the back-end metal wiring process, thereby reducing the number of white noise pixels and avoiding the generation of dark current in the device, thereby improving the yield of the device. Description of the Drawings
[0023] In order to more clearly illustrate the specific embodiments of this application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0024] Figure 1 is a flowchart of a method for manufacturing an image sensor according to an embodiment of the present invention;
[0025] Figures 2 - 5 is a schematic diagram of a semiconductor structure in each process step of manufacturing an image sensor according to an embodiment of the present invention;
[0026] Among them, the description of the reference numerals is as follows:
[0027] 10 - Substrate, 11 - Shallow trench isolation structure, 12 - First source region, 13 - First drain region, 14 - Second source region, 15 - Second drain region, 21 - First gate oxide layer, 22 - Second gate oxide layer, 31 - First gate, 32 - Second gate, 41 - First sidewall, 42 - Fourth sidewall, 51 - Second sidewall, 52 - Fifth sidewall, 61 - Third sidewall, 62 - Sixth sidewall;
[0028] 70 - Metal silicide barrier structure, 71 - First silicide barrier layer, 72 - Second silicide barrier layer. Detailed Embodiments
[0029] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.
[0030] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.
[0031] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.
[0032] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0033] The embodiment of the present application provides a method for manufacturing an image sensor. Refer to Figure 1 , Figure 1 which is a flowchart of the method for manufacturing an image sensor according to the embodiment of the present invention. The method for manufacturing the image sensor includes:
[0034] First, perform step S1: Refer to Figure 2 , Figure 2 which is a schematic diagram of a semiconductor structure after forming a sidewall structure according to the embodiment of the present application. Provide a substrate 10, the substrate 10 includes a plurality of device regions, and a plurality of shallow trench isolation structures 11 are formed in the substrate. The shallow trench isolation structures 11 are used to isolate different device regions. A gate structure and sidewall structures located on both sides of the gate structure are formed on the substrate 10 of each device region.
[0035] In this embodiment, taking the substrate 10 including an NMOS device region and a PMOS device region as an example, the shallow trench isolation structure 11 is used to isolate the NMOS device region and the PMOS device region. A first gate oxide layer 21, a first gate 31, and spacers 41, 51, and 61 on both sides of the first gate 31 are formed on the substrate 10 in the NMOS device region; a second gate oxide layer 22, a second gate 32, and spacers 42, 52, and 62 on both sides of the second gate 32 are formed on the substrate 10 in the PMOS device region. Further, a P-type well region is formed in the substrate of the NMOS device region, and an N-type well region is formed in the substrate of the PMOS device region.
[0036] Then, step S2 is executed: Refer to Figure 3 , Figure 3 which is a schematic diagram of the semiconductor structure after forming the first source region, the second source region, the first drain region, and the second drain region in the embodiment of the present application. Ion implantation is performed on the substrate 10 on both sides of the first gate 31 in the NMOS device region to form a first source region 12 and a first drain region 13 in the substrate of the NMOS device region; and ion implantation is performed on the substrate 10 on both sides of the second gate 32 in the PMOS device region to form a second source region 14 and a second drain region 15 in the substrate of the PMOS device region.
[0037] Next, step S3 is executed: Refer to Figure 4 , Figure 4 which is a schematic diagram of the semiconductor structure after forming the first silicide blocking layer in the embodiment of the present application. A first silicide blocking layer 71 is formed, and the first silicide blocking layer 71 covers the first gate 31, the first source region 12, and the first drain region 13 in the NMOS device region, and covers the second gate 32, the second source region 14, and the second drain region 15 in the PMOS device region.
[0038] Preferably, the first silicide blocking layer 71 is formed by a CVD process.
[0039] Preferably, the thickness of the first silicide blocking layer 71 is 100 Å to 300 Å.
[0040] In this embodiment, the material of the first silicide blocking layer 71 is silicon dioxide.
[0041] Further, step S4 is executed: Thermal annealing is performed on the semiconductor structure after forming the first silicide blocking layer 71 to activate the doped ions in the first source region 12, the first drain region 13, the second source region 14, and the second drain region 15;
[0042] Preferably, nitrogen is introduced into the process chamber, and a spike thermal annealing process is performed on the semiconductor structure after forming the first silicide blocking layer 71.
[0043] Specifically, during the process of performing spike thermal annealing on the semiconductor structure after forming the first silicide barrier layer 71, the flow rate of nitrogen is 10 slm to 40 slm; the process temperature is 1000 °C to 1200 °C; the duration is 1 s to 2 s.
[0044] Finally, perform step S5: Refer to Figure 5 , Figure 5 FIG. Figure 5 is a schematic diagram of the semiconductor structure after forming the second silicide barrier layer in the embodiment of the present application. The second silicide barrier layer 72 is formed by a furnace tube LPCVD process. The second silicide barrier layer 72 covers the first silicide barrier layer 71. In this embodiment, the first silicide barrier layer 71 and the second silicide barrier layer 72 constitute the final metal silicide barrier structure 70.
[0045] Among them, during the process of forming the second silicide barrier layer 72 by the furnace tube LPCVD process, the chamber pressure is 0.1 Torr to 2 Torr; the chamber temperature is 580 °C to 650 °C; the gases participating in the reaction at least include DCS gas and NH3; the process duration is 90 min to 170 min. In this embodiment, the second silicide barrier layer 72 is a silicon nitride layer.
[0046] Preferably, during the process of forming the second silicide barrier layer 72 by the furnace tube LPCVD process, the flow rate of DCS gas is 100 sccm to 300 sccm; the flow rate of NH3 is 300 sccm to 1000 sccm.
[0047] Preferably, the thickness of the second silicide barrier layer 72 is 200 Å to 650 Å.
[0048] In the present application, after forming the source region and the drain region by ion implantation, the first silicide barrier layer is first deposited, and then the doped ions in the source region and the drain region are activated by thermal annealing. Finally, a dense second silicide barrier layer is deposited by a furnace tube LPCVD (low pressure chemical vapor deposition) process. Thus, the first silicide barrier layer and the second silicide barrier layer constitute the final metal silicide barrier structure 70. The metal silicide barrier structure 70 can avoid introducing plasma during the process of forming the second silicide barrier layer by the traditional PECVD (plasma enhanced chemical vapor deposition) process, thereby avoiding plasma contamination of the gate structure and the substrate, and can effectively prevent metal impurity contamination during the subsequent contact hole process and the back-end metal wiring process, thereby reducing the number of white noise pixels and avoiding the generation of dark current in the device, thereby improving the yield of the device.
[0049] Further, after forming the second silicide blocking layer 72 by using the furnace tube LPCVD process, the method for manufacturing the image sensor may further include: etching the second silicide blocking layer 72 and the first silicide blocking layer 71 at the top of the gate 31 in the NMOS device region and the gate 32 in the PMOS device region, and etching the second silicide blocking layer 72 and the first silicide blocking layer 71 (not shown) above the source region 12 and the drain region 13 in the NMOS device region and the source region 14 and the drain region 15 in the PMOS device region, wherein the exposed surfaces of the tops of the gate 31 and the gate 32, the surfaces of the source region 12 and the drain region 13, and the surfaces of the source region 14 and the drain region 15 will form a metal silicide layer subsequently.
[0050] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. The obvious changes or variations derived therefrom are still within the protection scope of the present application.
Claims
1. A method for preparing an image sensor, characterized in that, Including: Providing a substrate, the substrate includes a plurality of device regions, a plurality of shallow trench isolation structures are formed in the substrate, the shallow trench isolation structures are used to isolate different device regions, a gate structure and sidewall structures located on both sides of the gate structure are formed on the substrate of each device region; Ion-implanting the substrate on both sides of the sidewall structures to form source regions and drain regions in the substrate of each device region; Forming a first silicide blocking layer, the first silicide blocking layer covers the gate structure, the sidewall structures and the substrate; Performing thermal annealing on the semiconductor structure after forming the first silicide blocking layer to activate the doped ions in the source regions and the drain regions; Forming a second silicide blocking layer by using a furnace LPCVD process, the second silicide blocking layer covers the first silicide blocking layer.
2. The manufacturing method of the image sensor according to claim 1, characterized in that, During the process of forming the second silicide blocking layer by using a furnace LPCVD process, the chamber pressure is 0.1 Torr to 2 Torr; the chamber temperature is: 580 °C to 650 °C; the gases participating in the reaction at least include: DCS gas and NH3; the process duration is: 90 min to 170 min.
3. The manufacturing method of the image sensor according to claim 2, characterized in that, During the process of forming the second silicide blocking layer by using a furnace LPCVD process, the flow rate of the DCS gas is 100 sccm to 300 sccm; the flow rate of the NH3 is 300 sccm to 1000 sccm.
4. The manufacturing method of the image sensor according to claim 1, characterized in that The thickness of the second silicide blocking layer is 200 Å to 650 Å.
5. The manufacturing method of the image sensor according to claim 1, characterized in that, Forming the first silicide blocking layer by using a CVD process.
6. The manufacturing method of the image sensor according to claim 1, characterized in that, The thickness of the first silicide blocking layer is 100 Å to 300 Å.
7. The manufacturing method of the image sensor according to claim 1, characterized in that, Introducing nitrogen gas into the process chamber and performing spike thermal annealing on the semiconductor structure after forming the first silicide blocking layer.
8. The manufacturing method of the image sensor according to claim 7, characterized in that, During the process of performing spike thermal annealing on the semiconductor structure after forming the first silicide blocking layer, the flow rate of the nitrogen gas is 10 slm to 40 slm; the process temperature is 1000 °C to 1200 °C; the duration is 1 s to 2 s.
9. The manufacturing method of the image sensor according to claim 1, characterized in that, After forming the second silicide blocking layer by using a furnace LPCVD process, the method for manufacturing the image sensor further includes: Etching the second silicide blocking layer and the first silicide blocking layer at the top of the gate structure, and etching the second silicide blocking layer and the first silicide blocking layer above the source regions and the drain regions.