Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a substrate, a light-emitting device arranged on one side of the substrate, the light-emitting device comprising a first electrode, a light-emitting functional layer and a second electrode which are sequentially stacked, the first electrode comprising a main body part and a connecting part connected with the main body part and protruding relative to the main body part, the light-emitting device comprising a plurality of first-type devices and a plurality of second-type devices, the first-type devices and the second-type devices are alternately arranged along a first direction and form a first device column, and the first-type devices and the second-type devices are alternately arranged along a second direction and form a first device row, in the same first device column, the connecting parts of the first-type devices are all connected to one side of the main body part in the second direction, and the connecting parts of the second-type devices are all connected to the other side of the main body part in the second direction, in the same first device row, the connecting parts of each first electrode are all located on the same side of the main body part in the second direction.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a display panel and a display device. BACKGROUND

[0002] Liquid crystal display (LCD) panels, organic light emitting diode display (OLED) panels, and display panels using light emitting diode (LED) devices have been widely applied to mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] However, the working effect of the current display product needs to be improved. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device, aiming to improve the working effect of the display panel.

[0005] An embodiment of the first aspect of the present application provides a display panel, comprising: a substrate; a light emitting device arranged on one side of the substrate, the light emitting device comprising a first electrode, a light emitting functional layer and a second electrode which are stacked in sequence in a direction away from the substrate, the first electrode comprising a main body portion and a connecting portion connected to the main body portion and protruding relative to the main body portion, wherein the light emitting device comprises a plurality of first type devices and a plurality of second type devices, the first type devices and the second type devices are alternately arranged along a first direction and form a first device column, and the first type devices and the second type devices are alternately arranged along a second direction and form a first device row, the light emitting color of the first type devices is different from the light emitting color of the second type devices, the first direction intersects the second direction, in the same first device column, the connecting portions of the first type devices are all connected to one side of the main body portion in the second direction, and the connecting portions of the second type devices are all connected to the other side of the main body portion in the second direction, in the same first device row, the connecting portions of each first electrode are all located on the same side of the main body portion in the second direction.

[0006] An embodiment of the second aspect of the present application provides a display device, comprising the display panel of the above embodiment.

[0007] In the display panel provided by the embodiment of the present application, the display panel comprises a substrate and a light-emitting device. The light-emitting device is arranged on one side of the substrate. In the direction away from the substrate, the light-emitting device comprises a first electrode, a light-emitting functional layer and a second electrode which are stacked in sequence. The first electrode and the second electrode on both sides of the light-emitting functional layer can be used to drive the light-emitting of the light-emitting functional layer, so as to realize the light-emitting display of the display panel. The first electrode comprises a main body part and a connecting part connected with the main body part and protruding relative to the main body part. The connecting part protruding from the main body part can be used to be electrically connected with the device structure in the substrate to receive a driving current, and the main body part can be used to transmit the driving current received by the connecting part to the light-emitting functional layer to participate in the driving of the light-emitting of the light-emitting functional layer.

[0008] The light-emitting device comprises a plurality of first-type devices and a plurality of second-type devices. The light-emitting color of the first-type device is different from the light-emitting color of the second-type device, so as to realize the color display of the display panel. The first-type devices and the second-type devices are alternately arranged along a first direction and form a first device column, and the first-type devices and the second-type devices are alternately arranged along a second direction and form a first device row.

[0009] By being arranged in the same first device column, the connecting part of the first-type device is connected to one side of the main body part in the second direction, and the connecting part of the second-type device is connected to the other side of the main body part in the second direction. Thus, the first-type devices and the second-type devices can be electrically connected with the device structures in different columns of the substrate respectively, so as to facilitate the independent driving of the first-type devices and the second-type devices, and thus facilitate the improvement of the display effect of the display panel.

[0010] By being arranged in the same first device row, the connecting part of each first electrode is located on the same side of the main body part in the second direction. Thus, there can be only one connecting part of the first electrode between the main body parts of the adjacent first electrodes in the second direction, so that the spacing between each main body part in the first device row can be approximately similar or the same, which is beneficial to the arrangement of each light-emitting device in the display panel, and thus is beneficial to the improvement of the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0012] Figure 1 is a partial cross-sectional view of a display panel provided by the embodiment of the present application;

[0013] Figure 2is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0014] Figure 3 is a layout schematic diagram of a light emitting device provided by an embodiment of the present application;

[0015] Figure 4 is a layout schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0016] Figure 5 is a partial structural schematic diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 6 is a connection relationship schematic diagram of a pixel circuit, a light emitting device and a data signal line provided by an embodiment of the present application;

[0018] Figure 7 is a partial structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0019] Figures 8 to 12 is a partial structural schematic diagram of each film layer in a substrate provided by an embodiment of the present application;

[0020] Figure 13 is a structural schematic diagram of a pixel circuit provided by another embodiment of the present application;

[0021] Figure 14 is a partial structural schematic diagram of a shielding structure provided by an embodiment of the present application;

[0022] Figure 15 is a partial structural schematic diagram of a display panel provided by another embodiment of the present application;

[0023] Figure 16 is a partial enlarged structural schematic diagram of a display panel provided by an embodiment of the present application.

[0024] Legend of reference signs:

[0025] 10, display panel;

[0026] 100, substrate; 110, base; 120, first insulating layer; 130, second insulating layer; 140, third insulating layer; 150, fourth insulating layer; 160, fifth insulating layer; 170, sixth insulating layer; 171, first sub-layer; 172, second sub-layer; 180, pixel circuit; 181, transistor; 181a, semiconductor; 181b, gate; 181c, source; 181d, drain; 182, storage capacitor; 182a, first plate; 182b, second plate; 190, connection structure; 191, first connection structure; 192, second connection structure; 193, third connection structure;

[0027] 200, pixel definition layer; 200a, pixel opening;

[0028] 300, light emitting device; 301, first type device; 302, second type device; 303, third type device; 310, first electrode; 311, main body part; 312, connection part; 320, light emitting functional layer; 321, light emitting structure; 322, common layer; 330, second electrode;

[0029] T1, driving transistor; T2, data writing transistor; T3, threshold compensation transistor; T4, first reset transistor; T5, second control transistor; T6, first control transistor; T7, second reset transistor; T8, bias adjustment transistor;

[0030] ELVDD, first power voltage signal line; Hole, let go opening; ELVSS, second power voltage signal line; Vdata, data signal line; FIAA, in-plane wiring; VREFP1, bias signal line; VREFN1, first reset signal line; VREFN2, second reset signal line; EM, light emitting control signal line; S1, first scan signal line; S2, second scan signal line; S3, third scan signal line; S4, fourth scan signal line;

[0031] ES, conductive structure; ES1, conductive part; ES2, shielding part; BS, shielding structure;

[0032] L1, first device column; L2, second device column;

[0033] R1, first device row; R2, second device row;

[0034] E1, first circuit column; E2, second circuit column; E3, third circuit column;

[0035] DL, virtual symmetry axis;

[0036] EG, circuit repeating unit; LG, device repeating unit;

[0037] X, first direction;

[0038] Y, second direction;

[0039] Z, thickness direction. DETAILED DESCRIPTION

[0040] The features and exemplary embodiments of the various aspects of the present application will be described in detail below with reference to the drawings. For the purpose of clarity, the description will be made with specific reference to the examples of the embodiments of the present application. It is to be understood that the specific examples described herein are merely illustrative of the present application and are not intended to limit the present application. The present application can be implemented without some of the specific details of the embodiments described below. The description of the embodiments is merely provided to give a better understanding of the present application by showing examples of the present application.

[0041] It should be noted that the terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply there is any such actual relationship or order between these entities or operations. Also, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0042] It should be understood that when describing the structure of a component, when a layer, a region is referred to as being "on" or "above" another layer, another region, it can mean being directly on or above the other layer, another region, or other layers or regions can be included therebetween. Also, if the component is turned over, the layer, the region will be "under" or "below" the other layer, another region.

[0043] Embodiments of the present application provide a display panel and a display device, which will be described below with reference to the accompanying drawings.

[0044] Figure 1 is a partial cross-sectional view of a display panel 10 provided by embodiments of the present application, Figure 2 is a structural schematic diagram of a pixel circuit 180 provided by embodiments of the present application, Figure 3is a schematic diagram of an arrangement of a light emitting device 300 provided by an embodiment of the present application. In the diagram, the X direction can schematically represent a first direction X, the Y direction can schematically represent a second direction Y, and the Z direction can schematically represent a thickness direction Z of the display panel 10. The first direction X, the second direction Y, and the thickness direction Z of the display panel 10 can each intersect with one another. For example, the first direction X, the second direction Y, and the thickness direction Z of the display panel 10 can each be perpendicular to one another. In order to facilitate the display of the specific arrangement of the light emitting device 300, the light emitting functional layer 320 and the second electrode 330 are hidden in some of the drawings of the present application.

[0045] As shown in Figures 1 to 3 An embodiment of the first aspect of the present application provides a display panel 10, comprising: a substrate 100; and a light emitting device 300 disposed on one side of the substrate 100, the light emitting device 300 comprising a first electrode 310, a light emitting functional layer 320, and a second electrode 330 stacked in sequence in a direction away from the substrate 100, the first electrode 310 comprising a main body portion 311 and a connecting portion 312 connected to the main body portion 311 and protruding relative to the main body portion 311, wherein the light emitting device 300 comprises a plurality of first-type devices 301 and a plurality of second-type devices 302, the first-type devices 301 and the second-type devices 302 are alternately arranged along a first direction X and form a first device column L1, and the first-type devices 301 and the second-type devices 302 are alternately arranged along a second direction Y and form a first device row R1, the light emitting color of the first-type devices 301 is different from the light emitting color of the second-type devices 302, the first direction X and the second direction Y intersect, in the same first device column L1, the connecting portions 312 of the first-type devices 301 are all connected to one side of the main body portion 311 in the second direction Y, and the connecting portions 312 of the second-type devices 302 are all connected to the other side of the main body portion 311 in the second direction Y, in the same first device row R1, the connecting portions 312 of each first electrode 310 are all located on the same side of the main body portion 311 in the second direction Y.

[0046] In a display panel 10 provided by an embodiment of the present application, the display panel 10 comprises a substrate 100 and a light emitting device 300.

[0047] Optionally, the substrate 100 can be provided in various ways. For example, the substrate 100 can comprise a substrate 110 and a plurality of pixel circuits 180 disposed on one side of the substrate 110. For example, the pixel circuit 180 can comprise a transistor 181, a storage capacitor 182, and a driving signal line for connecting various devices.

[0048] Optionally, the transistor 181 can include a semiconductor 181a, a gate 181b, a source 181c and a drain 181d. For example, the semiconductor 181a can have a channel region and source and drain regions arranged on two sides of the channel region, the gate 181b can be arranged on at least one side of the channel region in the thickness direction Z of the display panel 10, the source 181c can be connected to the source region through a via, and the drain 181d can be connected to the drain region through a via.

[0049] Optionally, the storage capacitor 182 can include a first plate 182a and a second plate 182b arranged on a side of the first plate 182a away from the substrate 110.

[0050] Optionally, the substrate 100 can include a first insulating layer 120, a second insulating layer 130, a third insulating layer 140, a fourth insulating layer 150, a fifth insulating layer 160 and a sixth insulating layer 170 stacked in sequence on the substrate 110. Each device in the pixel circuit 180 can be arranged between any two of the third insulating layer 140, the fourth insulating layer 150, the fifth insulating layer 160 and the sixth insulating layer 170, and the third insulating layer 140, the fourth insulating layer 150, the fifth insulating layer 160 and the sixth insulating layer 170 can be used to realize the arrangement and insulation of each device in the pixel circuit 180.

[0051] Optionally, the sixth insulating layer 170 can serve as a planarization layer of the display panel 10, that is, the surface of the sixth insulating layer 170 on the side away from the substrate 110 can be relatively flat, which can facilitate the subsequent preparation of other film layers on the substrate 100. For example, the material of the sixth insulating layer 170 can include an organic material, so that the material of the sixth insulating layer 170 has good flowability during the preparation of the sixth insulating layer 170, so that the surface of the sixth insulating layer 170 on the side away from the substrate 110 can be relatively flat.

[0052] The light-emitting device 300 is arranged on one side of the substrate 100. For example, the light-emitting device 300 can be arranged on the side of the sixth insulating layer 170 away from the substrate 110.

[0053] Optionally, the number of light-emitting devices 300 can be multiple, and the multiple light-emitting devices 300 can be arranged in an array along the first direction X and the second direction Y.

[0054] In the direction away from the substrate 100, the light-emitting device 300 includes a first electrode 310, a light-emitting functional layer 320 and a second electrode 330 stacked in sequence, and the first electrode 310 and the second electrode 330 arranged on two sides of the light-emitting functional layer 320 can be used to drive the light-emitting of the light-emitting functional layer 320, thereby realizing the light-emitting display of the display panel 10.

[0055] Optionally, the light-emitting functional layer 320 can include a light-emitting structure 321 and a common layer 322 disposed on at least one side of the light-emitting structure 321 in the thickness direction Z of the display panel 10. For example, the common layer 322 can be disposed on both sides of the light-emitting structure 321 in the thickness direction Z of the display panel 10. The common layer 322 disposed on the side of the light-emitting structure 321 facing the substrate 110 can include a hole injection layer (HIL) and a hole transport layer (HTL). The common layer 322 disposed on the side of the light-emitting structure 321 away from the substrate 110 can include an electron injection layer (EIL) and an electron transport layer (ETL).

[0056] Optionally, the first electrode 310 and the second electrode 330 can serve as pixel electrodes of the display panel 10. One of the first electrode 310 and the second electrode 330 can serve as an anode, and the other can serve as a cathode to drive the light-emitting functional layer 320 to emit light. In the embodiments of the present application, the first electrode 310 is taken as an anode of the display panel 10, and the second electrode 330 is taken as a cathode of the display panel 10 for example.

[0057] Optionally, the second electrodes 330 of the light-emitting devices 300 can be electrically connected to each other, so as to facilitate the control of the display panel 10. For example, the second electrodes 330 of the light-emitting devices 300 can be integrally formed. Optionally, the common layers 322 of the light-emitting devices 300 can be integrally formed, so as to facilitate the preparation of the display panel 10.

[0058] Optionally, the display panel 10 can further include a pixel definition layer 200 disposed on the side of the first electrode 310 away from the substrate 110. The pixel definition layer 200 can be provided with a pixel opening 200a. The light-emitting functional layer 320 and the second electrode 330 can extend from inside the pixel opening 200a to outside the pixel opening 200a. At least part of the surface of the first electrode 310 away from the substrate 110 can be exposed from the pixel opening 200a and connected to the light-emitting functional layer 320. The pixel definition layer 200 can be used to participate in the division of the sub-pixels of the display panel 10.

[0059] The first electrode 310 includes a main body part 311 and a connecting part 312 connected to the main body part 311 and protruding relative to the main body part 311. The connecting part 312 protruding from the main body part 311 can be used to be electrically connected to a device structure in the substrate 100 to receive a driving current. The main body part 311 can be used to transmit the driving current received by the connecting part 312 to the light-emitting functional layer 320 to participate in the light emission of the light-emitting functional layer 320.

[0060] Optionally, at least part of the surface of the main body 311 away from the substrate 110 can be exposed from the pixel opening 200a and connected with the light-emitting functional layer 320, and the connecting portion 312 can be located on the side of the pixel definition layer 200 facing the substrate 100.

[0061] Optionally, the connecting portion 312 can protrude relative to the main body 311, which can mean that the connecting portion 312 can protrude relative to the main body 311 along the first direction X or the second direction Y.

[0062] Optionally, the electrical connection between one and another in the embodiments of the present application can mean that one and another are directly connected in contact to achieve electrical connection, or can mean that electrical connection is achieved between one and another through other device structures, which is not specifically limited in the present application.

[0063] Optionally, the connecting portion 312 can be electrically connected with the pixel circuit 180 to receive a driving current. For example, the pixel circuit 180 includes a first control transistor T6 electrically connected with the connecting portion 312, and when the first control transistor T6 is turned on, the pixel circuit 180 can provide a driving current to the main body 311 through the connecting portion 312 to drive the light-emitting of the light-emitting functional layer 320.

[0064] Optionally, a single pixel circuit 180 can correspond to a single light-emitting device 300, i.e., a single pixel circuit 180 can be electrically connected with the first electrode 310 of a single light-emitting device 300, so that the single pixel circuit 180 can drive and control the light-emitting of the single light-emitting device 300.

[0065] Optionally, there are various working principles and circuit structure setting modes of the pixel circuit 180.

[0066] For example, the pixel circuit 180 can further include a driving transistor T1 electrically connected with the first control transistor T6, and a second control transistor T5 electrically connected with the driving transistor T1 away from the first control transistor T6, and the pixel circuit 180 can further include a data writing transistor T2 electrically connected with the second control transistor T5 close to the driving transistor T1 and the driving transistor T1 away from the first control transistor T6.

[0067] The display panel 10 can further include a data signal line Vdata, and the data writing transistor T2 away from the driving transistor T1 is electrically connected with the data signal line Vdata, and the data signal line Vdata can be used to provide a data signal to the pixel circuit 180.

[0068] The display panel 10 can further include a first power voltage signal line ELVDD, and a second end of the second control transistor T5 can be electrically connected to the first power voltage signal line ELVDD. The first power voltage signal line ELVDD can be used to provide a positive power voltage signal to the pixel circuit 180.

[0069] As a further example, the pixel circuit 180 can further include a threshold compensation transistor T3, a first reset transistor T4, a second reset transistor T7, and a bias adjustment transistor 181. The display panel 10 can further include a second power voltage signal line ELVSS, a bias signal line VREFP1, a first reset signal line VREFN1, a second reset signal line VREFN2, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, and an emission control signal line EM.

[0070] The first end of the second control transistor T5 can be electrically connected to the second plate 182b of the storage capacitor 182, and the first end of the second control transistor T5 and the second plate 182b of the storage capacitor 182 can be electrically connected to the first power voltage signal line ELVDD (e.g., which can be a positive power voltage signal line). The first power voltage signal line ELVDD can provide a positive power voltage signal to the second control transistor T5 and the storage capacitor 182. The first end of the data write transistor T2 can be electrically connected to a data signal line Vdata, and the data signal line Vdata can provide a data signal to the data write transistor T2. The first end of the bias adjustment transistor T8 can be electrically connected to a bias signal line VREFP1, and the bias signal line VREFP1 can provide a bias signal to the bias adjustment transistor T8. The second end of the data write transistor T2, the second end of the second control transistor T5, the second end of the bias adjustment transistor T8, and the first end of the drive transistor T1 can be electrically connected to each other.

[0071] The first end of the threshold compensation transistor T3, the second end of the driving transistor T1 and the first end of the first control transistor T6 can be electrically connected with each other. The first end of the first reset transistor T4 can be electrically connected with the first reset signal line VREFN1, and the first reset signal line VREFN1 can provide a first reset signal to the first reset transistor T4. The second end of the first reset transistor T4, the second end of the threshold compensation transistor T3, the control end of the driving transistor T1 and the first plate 182a of the storage capacitor 182 can be electrically connected with each other. The first end of the second reset transistor T7 can be electrically connected with the second reset signal line VREFN2, and the second reset signal line VREFN2 can provide a second reset signal to the second reset transistor T7. The second end of the second reset transistor T7, the second end of the first control transistor T6 and the first electrode 310 of the light emitting device 300 can be electrically connected with each other. The second electrode 330 of the light emitting device 300 can be electrically connected with the second power voltage signal line ELVSS (for example, can be a negative power voltage signal line).

[0072] The control end of the first control transistor T6 can be electrically connected with the control end of the second control transistor T5, and the control end of the first control transistor T6 and the control end of the second control transistor T5 can be electrically connected with the light emitting control signal line EM. The control end of the first reset transistor T4 can be electrically connected with the first scan signal line S1, the control end of the data write transistor T2 can be electrically connected with the second scan signal line S2, and the control end of the threshold compensation transistor T3 can be electrically connected with the third scan signal line S3. The control end of the second reset transistor T7 and the control end of the bias adjustment transistor T8 can be electrically connected with each other, and the control end of the second reset transistor T7 and the control end of the bias adjustment transistor T8 can be electrically connected with the fourth scan signal line S4.

[0073] Optionally, in the working process of the pixel circuit 180, the pixel circuit 180 can have a gate 181b reset stage, a data write stage, a light emitting stage and a bias stage. In the gate 181b reset stage, the first scan signal line S1 provides an effective level to the control end of the first reset transistor T4, so that the first reset transistor T4 is turned on. The first reset signal provided by the first reset signal line VREFN1 can be input to the control end of the driving transistor T1 through the first reset transistor T4, so as to reset the control end of the driving transistor T1.

[0074] In the data writing stage, the second scan signal line S2 provides an effective level to the control end of the data writing transistor T2, so as to turn on the data writing transistor T2. Meanwhile, the third scan signal line S3 provides an effective level to the control end of the threshold compensation transistor T3, so as to turn on the threshold compensation transistor T3. The data signal provided by the data signal line Vdata can be sequentially input to the first plate 182a of the storage capacitor 182 via the data writing transistor T2, the driving transistor T1 and the threshold compensation transistor T3, and stored by the storage capacitor 182.

[0075] Before and / or after the data writing stage, a bias stage can be provided. In the bias stage, the fourth scan signal line S4 can provide an effective level to the control end of the second reset transistor T7 and the control end of the bias adjustment transistor 181, so as to turn on the second reset transistor T7 and the bias adjustment transistor 181. The second reset signal line VREFN2 can provide a second reset signal to the first electrode 310 of the light emitting device 300 through the second reset transistor T7, so as to reset the first electrode 310 of the light emitting device 300. The bias signal line VREFP1 can write a bias signal to the first end of the driving transistor T1 through the bias adjustment transistor T8, so as to adjust the reverse bias of the driving transistor T1 by the bias signal, and compensate the characteristic curve drift caused by the forward bias.

[0076] In the light emitting stage, the light emitting control signal line EM provides an effective level to the control end of the first control transistor T6 and the control end of the second control transistor T5, so as to turn on the first control transistor T6 and the second control transistor T5. The driving transistor T1 provides a corresponding driving current to the first electrode 310 of the light emitting device 300 according to the data signal stored by the storage capacitor 182, so that the light emitting device 300 can emit light at a target brightness.

[0077] Optionally, one of the first end and the second end of the transistor 181 in any of the foregoing embodiments can refer to the source 181c of the transistor 181, and the other can refer to the drain 181d of the transistor 181. The control end of the transistor 181 can refer to the gate 181b of the transistor 181.

[0078] Optionally, the semiconductor material of the transistor 181 in any of the foregoing embodiments can be N-type or P-type. For example, in the pixel circuit 180, except for the threshold compensation transistor T3 and the first reset transistor T4 which are N-type semiconductor material transistors 181, the remaining transistors 181 can be P-type semiconductor material transistors 181. For instance, in the pixel circuit 180, except for the threshold compensation transistor T3 and the first reset transistor T4 whose semiconductor 181a materials both include indium gallium zinc oxide (IGZO), the semiconductor 181a materials of the remaining transistors 181 can all include amorphous silicon (a-Si).

[0079] The light-emitting device 300 includes a plurality of first-type devices 301 and a plurality of second-type devices 302. The light-emitting color of the first-type devices 301 is different from that of the second-type devices 302, so as to realize the color display of the display panel 10.

[0080] For example, the first type of device 301 may emit red light, and the second type of device 302 may emit blue light.

[0081] The first type of device 301 and the second type of device 302 are arranged alternately along the first direction X to form a first device column L1, and the first type of device 301 and the second type of device 302 are arranged alternately along the second direction Y to form a first device row R1.

[0082] By setting the first type of device 301 in the same first device column L1, the connection portion 312 of the first type of device 301 is connected to one side of the main body 311 in the second direction Y, and the connection portion 312 of the second type of device 302 is connected to the other side of the main body 311 in the second direction Y, so that the first type of device 301 and the second type of device 302 can be electrically connected to the device structure (e.g., pixel circuit 180) located in different columns in the substrate 100, thereby facilitating the relatively independent driving of the first type of device 301 and the second type of device 302, which is beneficial to improving the display effect of the display panel 10.

[0083] For example, such as Figure 3 As shown, in the same first device column L1, the connecting portion 312 of the first type of device 301 can be connected to the left side of the main body 311, and the connecting portion 312 of the second type of device 302 can be connected to the right side of the main body 311; or, in the same first device column L1, the connecting portion 312 of the first type of device 301 can be connected to the right side of the main body 311, and the connecting portion 312 of the second type of device 302 can be connected to the left side of the main body 311.

[0084] Optionally, in two adjacent columns of first device columns L1, the connecting portions 312 of the first type of device 301 in one column of first device column L1 can be connected to the left side of the main body 311, and the connecting portions 312 of the second type of device 302 can be connected to the right side of the main body 311. In the other column of first device columns L1, the connecting portions 312 of the first type of device 301 can be connected to the right side of the main body 311, and the connecting portions 312 of the second type of device 302 can be connected to the left side of the main body 311.

[0085] By setting the connection portion 312 of each first electrode 310 in the same first device row R1, all the connection portions 312 of the main body portion 311 are located on the same side of the second direction Y, so that there can be only one connection portion 312 between the main body portions 311 of adjacent first electrodes 310 in the second direction Y. This makes the spacing between each main body portion 311 in the first device row R1 more similar or the same, which is beneficial to improving the arrangement effect of each light-emitting device 300 in the display panel 10, and thus beneficial to improving the display effect of the display panel 10.

[0086] For example, such as Figure 3 As shown, in the same first device row R1, the connection portion 312 of the first type device 301 and the second type device 302 can be connected to the left side of the main body portion 311; or, the connection portion 312 of the first type device 301 and the second type device 302 can be connected to the right side of the main body portion 311.

[0087] Optionally, in two adjacent rows of first devices R1, the connection portions 312 of the first electrodes 310 located in different rows of first devices R1 are located on different sides of the main body 311 in the second direction Y. For example, in two adjacent rows of first devices R1, the connection portions 312 of the first type of device 301 and the second type of device 302 in one row of first devices R1 can be connected to the left side of the main body 311, while the connection portions 312 of the first type of device 301 and the second type of device 302 in the other row of first devices R1 can be connected to the right side of the main body 311.

[0088] Figure 4 This is a schematic diagram of the arrangement of a pixel circuit 180 provided in an embodiment of this application. Figure 5 This is a partial structural schematic diagram of a display panel 10 provided in an embodiment of this application. Figure 6 This is a schematic diagram illustrating the connection relationship between a pixel circuit 180, a light-emitting device 300, and a data signal line Vdata, provided in an embodiment of this application. It is exemplary and intended for easy distinction. Figure 4 The first circuit column E1, the second circuit column E2, and the third circuit column E3 in the diagram. Figure 4 The pixel circuits 180 in the first circuit column E1, the second circuit column E2 and the third circuit column E3 are filled with different patterns.

[0089] like Figures 4 to 6 As shown, in some optional embodiments, at least two pixel circuits 180 are arranged in the first direction X to form a circuit column, and the data signal line Vdata can extend along the first direction X. Each pixel circuit 180 in the same circuit column is electrically connected to the same data signal line Vdata, so that a single data signal line Vdata can provide data signals to each pixel circuit 180 located in the same circuit column, which is beneficial to improving the working efficiency of the data signal line Vdata and facilitates the control of the display panel 10.

[0090] Optionally, each pixel circuit 180 in the same circuit column is electrically connected to the same data signal line Vdata. This can mean that the first terminal of the data writing transistor T2 of each pixel circuit 180 in the same circuit column can be electrically connected to the same data signal line Vdata.

[0091] Optionally, there can be multiple data signal lines Vdata. For example, the number of data signal lines Vdata can be the same as the number of circuit columns, and a single data signal line Vdata can be set to correspond to a single circuit column.

[0092] Optionally, multiple data signal lines Vdata can be spaced out in the second direction Y.

[0093] Optionally, the data signal line Vdata can be disposed within the substrate 100, and there are various ways to position the data signal line Vdata within the substrate 100. For example, the sixth insulating layer 170 may include a first sub-layer 171 and a second sub-layer 172 disposed on the side of the first sub-layer 171 facing away from the substrate 110, and the data signal line Vdata may be disposed between the first sub-layer 171 and the second sub-layer 172.

[0094] Optionally, the first power supply voltage signal line ELVDD can be disposed in the same layer and made of the same material as the data signal line Vdata, so that the first power supply voltage signal line ELVDD and the data signal line Vdata can be fabricated together in the same fabrication step, which is beneficial to improving the fabrication efficiency of the display panel 10. For example, both the first power supply voltage signal line ELVDD and the data signal line Vdata can be disposed between the first sublayer 171 and the second sublayer 172.

[0095] Optionally, the first power voltage signal line ELVDD can extend along the first direction X, and each pixel circuit 180 in the same circuit column can be electrically connected with the same first power voltage signal line ELVDD. For example, the first end of the second control transistor T5 of each pixel circuit 180 in the same circuit column can be electrically connected with the same first power voltage signal line ELVDD, so that a single first power voltage signal line ELVDD can provide a positive power voltage signal to each pixel circuit 180 in the same circuit column, which is beneficial to improve the working efficiency of the first power voltage signal line ELVDD and facilitate the control of the display panel 10.

[0096] Optionally, the number of the first power voltage signal lines ELVDD can be multiple, and a single first power voltage signal line ELVDD can be arranged corresponding to at least one circuit column. For example, a single first power voltage signal line ELVDD can be arranged corresponding to two circuit columns adjacent in the second direction Y, that is, each pixel circuit 180 in the two circuit columns adjacent in the second direction Y can be electrically connected with the same first power voltage signal line ELVDD.

[0097] Optionally, the multiple first power voltage signal lines ELVDD can be arranged at intervals in the second direction Y.

[0098] Optionally, the substrate 100 can further be provided with a signal line (not shown in the figure) for electrically connecting at least two first power voltage signal lines ELVDD adjacent in the second direction Y, so that each first power voltage signal line ELVDD can be electrically connected with each other, which is beneficial to facilitate the control of each first power voltage signal line ELVDD and reduce the voltage drop and resistance of the first power voltage signal line ELVDD.

[0099] Optionally, at least one data signal line Vdata can be arranged between the first power voltage signal lines ELVDD adjacent in the second direction Y. For example, two data signal lines Vdata can be arranged between the first power voltage signal lines ELVDD adjacent in the second direction Y, which is beneficial to realize that a single first power voltage signal line ELVDD can be arranged corresponding to two circuit columns adjacent in the second direction Y, and a single data signal line Vdata can be arranged corresponding to a single circuit column.

[0100] Optionally, the display panel 10 can further include a fanout in AA (Fanout in AA) to reduce the frame of the display panel 10.

[0101] Optionally, at least part of the in-plane wires FIAA can extend along the first direction X, and the in-plane wires FIAA extending along the first direction X can be arranged in the same layer and made of the same material as the data signal lines Vdata, so that the in-plane wires FIAA extending along the first direction X can be prepared together with the data signal lines Vdata in the same preparation step, which is conducive to improving the preparation efficiency of the display panel 10. For example, the first power voltage signal line ELVDD, the data signal lines Vdata, and the in-plane wires FIAA extending along the first direction X can all be arranged between the first sub-layer 171 and the second sub-layer 172.

[0102] Optionally, part of the in-plane wires FIAA can also extend along the second direction Y (not shown in the figure), so as to further improve the arrangement density of the in-plane wires FIAA. Optionally, the in-plane wires FIAA extending along the second direction Y can be arranged in different layers from the in-plane wires FIAA extending along the first direction X.

[0103] Optionally, the in-plane wires FIAA extending along the first direction X can be arranged between adjacent data signal lines Vdata in the second direction Y. For example, two in-plane wires FIAA extending along the first direction X can be arranged between adjacent data signal lines Vdata in the second direction Y, so as to improve the arrangement density of the in-plane wires FIAA.

[0104] In some optional embodiments, the circuit columns include first circuit columns E1 and second circuit columns E2, the first circuit columns E1 and the second circuit columns E2 are arranged alternately along the second direction Y, the connection portions 312 of each first type of device 301 in the first device column L1 are respectively electrically connected to each pixel circuit 180 in the same first circuit column E1, and / or the connection portions 312 of each second type of device 302 in the first device column L1 are respectively electrically connected to each pixel circuit 180 in the same second circuit column E2.

[0105] Optionally, the connection portions 312 of each first type of device 301 in the first device column L1 are respectively electrically connected to the second ends of the first control transistors T6 of each pixel circuit 180 in the same first circuit column E1.

[0106] Optionally, the connection portions 312 of each second type of device 302 in the first device column L1 are respectively electrically connected to the second ends of the first control transistors T6 of each pixel circuit 180 in the same second circuit column E2.

[0107] Optionally, a single data signal line Vdata can be electrically connected to each pixel circuit 180 in a single first circuit column E1. For example, a single data signal line Vdata can be electrically connected to the first ends of the data write transistors T2 of each pixel circuit 180 in a single first circuit column E1.

[0108] Optionally, the single data signal line Vdata can be electrically connected with each pixel circuit 180 in the single second circuit column E2. For example, the single data signal line Vdata can be electrically connected with the first end of the data write transistor T2 of each pixel circuit 180 in the single second circuit column E2.

[0109] Optionally, the data signal lines Vdata electrically connected with the first circuit columns E1 can be arranged alternately with the data signal lines Vdata electrically connected with the second circuit columns E2 along the second direction Y, so as to facilitate the electrical connection between the data signal lines Vdata and the corresponding circuit columns.

[0110] Optionally, the voltage of the provided data signal of the data signal line Vdata electrically connected with the first circuit columns E1 can be different from the voltage of the provided data signal of the data signal line Vdata electrically connected with the second circuit columns E2 during the operation of the pixel circuit 180.

[0111] In these optional embodiments, by arranging the connection portions 312 of each first-type device 301 in the first device column L1 to be electrically connected with each pixel circuit 180 in the same first circuit column E1 respectively, and arranging the connection portions 312 of each second-type device 302 in the first device column L1 to be electrically connected with each pixel circuit 180 in the same second circuit column E2 respectively, the first circuit column E1 and the second circuit column E2 can be used for relatively independent driving and control of the light emission of the first-type device 301 and the second-type device 302 respectively, i.e., the light emission of the first-type device 301 and the second-type device 302 with different light emission colors can be driven and controlled relatively independently, thereby facilitating the reduction of the power consumption of the display panel 10 and the improvement of the display effect of the display panel 10.

[0112] In some optional embodiments, in two adjacent first device columns L1, the connection portions 312 of each first-type device 301 are electrically connected with each pixel circuit 180 in the same first circuit column E1, or the connection portions 312 of each second-type device 302 are electrically connected with each pixel circuit 180 in the same second circuit column E2.

[0113] Optionally, in two adjacent first device columns L1, the connection portions 312 of each first-type device 301 are electrically connected with each pixel circuit 180 in the same first circuit column E1, and the connection portions 312 of each second-type device 302 in different first device columns L1 are electrically connected with each pixel circuit 180 in different second circuit columns E2; or the connection portions 312 of each second-type device 302 are electrically connected with each pixel circuit 180 in the same second circuit column E2, and the connection portions 312 of each first-type device 301 in different first device columns L1 are electrically connected with each pixel circuit 180 in different first circuit columns E1.

[0114] For example, in the two adjacent first device columns L1, the connection portions 312 of the first type of devices 301 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in the same first circuit column E1, and the connection portions 312 of the second type of devices 302 in different first device columns L1 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in different second circuit columns E2; or, the connection portions 312 of the second type of devices 302 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in the same second circuit column E2, and the connection portions 312 of the first type of devices 301 in different first device columns L1 are respectively electrically connected to the second ends of the first control transistors T6 of the pixel circuits 180 in different first circuit columns E1.

[0115] Optionally, the orthogonal projection of the first circuit column E1 on the substrate 110 can be located between the orthogonal projections of the main body portions 311 of the two adjacent first device columns L1 on the substrate 110, so as to electrically connect the connection portions 312 of the first type of devices 301 in the two adjacent first device columns L1 to the pixel circuits 180 in the same first circuit column E1.

[0116] Optionally, the orthogonal projection of the second circuit column E2 on the substrate 110 can be located between the orthogonal projections of the main body portions 311 of the two adjacent first device columns L1 on the substrate 110, so as to electrically connect the connection portions 312 of the second type of devices 302 in the two adjacent first device columns L1 to the pixel circuits 180 in the same second circuit column E2.

[0117] In these optional embodiments, by electrically connecting the connection portions 312 of the first type of devices 301 in the two adjacent first device columns L1 to the pixel circuits 180 in the same first circuit column E1, each pixel circuit 180 in a single first circuit column E1 can drive and control the light-emitting work of the first type of devices 301 in the two adjacent first device columns L1, so that the number of the first circuit columns E1 arranged in the second direction Y can be reduced by increasing the number of the pixel circuits 180 arranged in the first direction X in the first circuit column E1, thereby facilitating to improve the pixel arrangement density of the display panel 10 and further improving the display effect of the display panel 10.

[0118] Similarly, by setting the connection portions 312 of the second-type devices 302 in the two adjacent first-device columns L1 to be electrically connected with the pixel circuits 180 in the same second-circuit column E2 respectively, each pixel circuit 180 in the single second-circuit column E2 can drive and control the light-emitting operation of the second-type devices 302 in the two adjacent first-device columns L1 respectively, so that the number of the second columns arranged in the second direction Y can be reduced by increasing the number of the pixel circuits 180 arranged in the first direction X in the second-circuit column E2, thereby facilitating to improve the pixel arrangement density of the display panel 10 and further improving the display effect of the display panel 10.

[0119] In some optional embodiments, the connection portion 312 of the first-type device 301 can be located between the body portion 311 of the first-type device 301 and the body portion 311 of the second-type device 302 adjacent in the second direction Y, and / or the connection portion 312 of the second-type device 302 can be located between the body portion 311 of the first-type device 301 and the body portion 311 of the second-type device 302 adjacent in the second direction Y.

[0120] In the optional embodiments, by setting the connection portion 312 of the first-type device 301 and the connection portion 312 of the second-type device 302 between the body portion 311 of the first-type device 301 and the body portion 311 of the second-type device 302 adjacent in the second direction Y, the connection portion 312 of the first-type device 301 and the connection portion 312 of the second-type device 302 can not easily have an excessively large size (for example, the connection portion 312 of the first-type device 301 can not extend to the side of the body portion 311 of the second-type device 302 in the first direction X, and the connection portion 312 of the second-type device 302 can not extend to the side of the body portion 311 of the first-type device 301 in the first direction X), thereby facilitating to reduce the possibility of disconnection of the first electrode 310 of the first-type device 301 and the first electrode 310 of the second-type device 302, and to reduce the coupling interference between the light-emitting devices 300, thereby facilitating to improve the working effect of the display panel 10.

[0121] In some optional embodiments, the first control transistor T6 is at least partially located on one side of the body portion 311 of the first-type device 301 and / or the second-type device 302 in the second direction Y.

[0122] Optionally, the first control transistor T6 being at least partially located on one side of the body portion 311 of the first-type device 301 and / or the second-type device 302 in the second direction Y can mean that the orthographic projection of the first control transistor T6 on the substrate 110 is at least partially located on one side of the orthographic projection of the body portion 311 of the first-type device 301 and / or the second-type device 302 on the substrate 110 in the second direction Y.

[0123] Exemplarily, the orthogonal projection of the source 181c and / or the drain 181d of the first control transistor T6 on the substrate 110 can be at least partially located at one side of the orthogonal projection of the main body 311 of the first type device 301 and / or the second type device 302 on the substrate 110 in the second direction Y.

[0124] Optionally, the first control transistor T6 of at least one of the first circuit columns E1 can be at least partially located at one side of the main body 311 of the first type device 301 and / or the second type device 302 in the second direction Y. Exemplarily, the first control transistor T6 of the first circuit column E1 can be at least partially located at one side of the main body 311 of the first type device 301 and / or the second type device 302 in the second direction Y. The first control transistor T6 of the second circuit column E2 can be at least partially located at one side of the main body 311 of the first type device 301 and / or the second type device 302 in the second direction Y.

[0125] Optionally, the orthogonal projection of the source 181c and / or the drain 181d of the first control transistor T6 of at least one of the circuit columns on the substrate 110 can be at least partially located between the orthogonal projection of the main body 311 of the first type device 301 on the substrate 110 and the orthogonal projection of the main body 311 of the second type device 302 on the substrate 110 in the second direction Y. Exemplarily, the orthogonal projection of the source 181c and / or the drain 181d of the first control transistor T6 of the first circuit column E1 on the substrate 110 can be at least partially located between the orthogonal projection of the main body 311 of the first type device 301 on the substrate 110 and the orthogonal projection of the main body 311 of the second type device 302 on the substrate 110 in the second direction Y, and / or, the orthogonal projection of the source 181c and / or the drain 181d of the first control transistor T6 of the second circuit column E2 on the substrate 110 can be at least partially located between the orthogonal projection of the main body 311 of the first type device 301 on the substrate 110 and the orthogonal projection of the main body 311 of the second type device 302 on the substrate 110 in the second direction Y.

[0126] In these optional embodiments, by disposing the first control transistor T6 connected with the connecting portion 312 on one side of the main body portion 311 of the first type device 301 and the second type device 302 in the second direction Y, the electrical connection between the connecting portion 312 of the first type device 301 and the connecting portion 312 of the second type device 302 which protrude from the main body portion 311 in the second direction Y and the first control transistor T6 can be facilitated, and the connecting point between the connecting portion 312 of the first type device 301 and the pixel circuit 180 can be located between the main body portion 311 of the first type device 301 and the main body portion 311 of the second type device 302 adjacent in the second direction Y, or the connecting point between the connecting portion 312 of the second type device 302 and the pixel circuit 180 can be located between the main body portion 311 of the first type device 301 and the main body portion 311 of the second type device 302 adjacent in the second direction Y, so that the connecting portion 312 of the first type device 301 and the connecting portion 312 of the second type device 302 can not easily have an excessively large size, thereby facilitating the reduction of the possibility of disconnection of the first electrode 310 of the first type device 301 and the first electrode 310 of the second type device 302, and facilitating the reduction of the coupling interference between the light emitting devices 300, and further facilitating the improvement of the working effect of the display panel 10.

[0127] In some optional embodiments, the light emitting device 300 further comprises a plurality of third type devices 303 which are different from the first type device 301 and the second type device 302 in the light emitting color, so as to realize the color display of the display panel 10.

[0128] For example, the light emitting color of the third type device 303 can be green.

[0129] Optionally, the orthographic projection area of the main body portion 311 of the first type device 301 on the substrate 110 can be greater than the orthographic projection area of the main body portion 311 of the third type device 303 on the substrate 110, and / or the orthographic projection area of the main body portion 311 of the second type device 302 on the substrate 110 can be greater than the orthographic projection area of the main body portion 311 of the third type device 303 on the substrate 110, so that when the light emitting color of the first type device 301 is red, the light emitting color of the second type device 302 is blue, and the light emitting color of the third type device 303 is green, the light emitting effect of the first type device 301 and the second type device 302 with lower light emitting efficiency can be better improved.

[0130] Optionally, the orthographic projection area of the main body portion 311 of the second type device 302 on the substrate 110 can be greater than the orthographic projection area of the main body portion 311 of the first type device 301 on the substrate 110, so that when the light emitting color of the first type device 301 is red and the light emitting color of the second type device 302 is blue, the light emitting effect of the second type device 302 with lower light emitting efficiency can be better improved.

[0131] In some optional embodiments, the plurality of third-type devices 303 are arranged along the first direction X and form a second device column L2, the first device column L1 and the second device column L2 are arranged alternately along the second direction Y, the circuit column further comprises a third circuit column E3, the first circuit column E1, the second circuit column E2 and the third circuit column E3 are arranged alternately along the second direction Y, and at least one third circuit column E3 is arranged between adjacent first circuit column E1 and second circuit column E2, and the connecting portions 312 of each third-type device 303 in the second device column L2 are electrically connected to each pixel circuit 180 in the same third circuit column E3.

[0132] Optionally, the first circuit column E1, the second circuit column E2 and the third circuit column E3 arranged alternately along the second direction Y can mean that each first circuit column E1 arranged along the second direction Y can not be directly adjacent, i.e. each first circuit column E1 arranged along the second direction Y can be provided with a second circuit column E2 or a third circuit column E3, and each second circuit column E2 arranged along the second direction Y can not be directly adjacent, i.e. each second circuit column E2 arranged along the second direction Y can be provided with a first circuit column E1 or a third circuit column E3, and each third circuit column E3 arranged along the second direction Y can not be directly adjacent, i.e. each third circuit column E3 arranged along the second direction Y can be provided with a first circuit column E1 or a second circuit column E2.

[0133] Optionally, in the display panel 10, a single first circuit column E1, a single second circuit column E2 and two third circuit columns E3 can constitute a circuit repeating unit EG in the circuit column arrangement, and the number of circuit repeating units EG can be multiple, and the multiple circuit repeating units EG can be arranged along the second direction Y. For example, as shown in FIG. 4, in the direction from left to right, a third circuit column E3, a first circuit column E1, a third circuit column E3 and a second circuit column E2 can be arranged in the circuit repeating unit EG in sequence. Figure 4

[0134] Optionally, in the display panel 10, two first device columns L1 and two second device columns L2 can constitute a device repeating unit LG in the arrangement of light-emitting devices 300, and the number of device repeating units LG can be multiple, and the multiple device repeating units LG can be arranged along the second direction Y. For example, as shown in FIG. 5, in the direction from left to right, a first device column L1, a second device column L2, a first device column L1 and a second device column L2 can be arranged in the device repeating unit LG in sequence. Figure 5

[0135] ​​Optionally, the data signal line Vdata electrically connected with the third circuit column E3 can be adjacent to the data signal line Vdata electrically connected with the second circuit column E2, or the data signal line Vdata electrically connected with the third circuit column E3 can be adjacent to the data signal line Vdata electrically connected with the first circuit column E1.

[0136] Optionally, the data signal line Vdata electrically connected with the third circuit column E3 can be adjacent to the data signal line Vdata electrically connected with the second circuit column E2, or the data signal line Vdata electrically connected with the third circuit column E3 can be adjacent to the data signal line Vdata electrically connected with the first circuit column E1.

[0137] In these optional embodiments, by electrically connecting the connection part 312 of each third-type device 303 in the second device column L2 with each pixel circuit 180 in the same third circuit column E3 respectively, the third circuit column E3 can be used for relatively independent driving and control of the light emission of the third-type device 303, thereby facilitating the reduction of the power consumption of the display panel 10 and the improvement of the display effect of the display panel 10. By arranging the first device column L1 and the second device column L2 to be arranged alternately along the second direction Y, the first circuit column E1, the second circuit column E2 and the third circuit column E3 are arranged alternately along the second direction Y, and at least one third circuit column E3 is arranged between the adjacent first circuit column E1 and the second circuit column E2, the electrical connection between each second device column L2 and the pixel circuit 180 in the third circuit column E3 can be facilitated.

[0138] In some optional embodiments, in two adjacent first device columns L1, the first electrode 310 of one of the first device columns L1 has a projection on the substrate 110 that partially overlaps with the projection of the first circuit column E1 on the substrate 110 and partially overlaps with the projection of the third circuit column E3 on the substrate 110, and the first electrode 310 of the other of the first device columns L1 has a projection on the substrate 110 that partially overlaps with the projection of the second circuit column E2 on the substrate 110 and partially overlaps with the projection of the third circuit column E3 on the substrate 110, so that one of the first device columns L1 in the device repeating unit LG can be better positioned between the first circuit column E1 and one of the third circuit columns E3 in the circuit repeating unit EG, and the other of the first device columns L1 in the device repeating unit LG can be better positioned between the second circuit column E2 and the other of the third circuit columns E3 in the circuit repeating unit EG, which is conducive to achieving electrical connection between the first type of devices 301 in the two first device columns L1 and each pixel circuit 180 in the same first circuit column E1, and is conducive to achieving electrical connection between the second type of devices 302 in the two first device columns L1 and each pixel circuit 180 in the same first circuit column E1.

[0139] In some optional embodiments, in two adjacent second device columns L2, the first electrode 310 of one of the second device columns L2 has a projection on the substrate 110 that partially overlaps with the projection of the first circuit column E1 on the substrate 110 and partially overlaps with the projection of the third circuit column E3 on the substrate 110, and the first electrode 310 of the other of the second device columns L2 has a projection on the substrate 110 that partially overlaps with the projection of the second circuit column E2 on the substrate 110 and partially overlaps with the projection of the third circuit column E3 on the substrate 110, which is conducive to achieving electrical connection between the third type of devices 303 in each second device column L2 and each pixel circuit 180 in each third circuit column E3, respectively.

[0140] In some optional embodiments, the plurality of third type of devices 303 are arranged along the second direction Y and form a second device row R2, and the first device row R1 and the second device row R2 are alternately arranged along the first direction X, and the connecting portion 312 of the third type of device 303 is connected to one side of the main body portion 311 in the first direction X.

[0141] Optionally, in the same second device column L2, the connecting portion 312 of each first electrode 310 is located on the same side of the main body portion 311 in the first direction X, and / or, in the same second device row R2, the connecting portion 312 of each first electrode 310 is located on the same side of the main body portion 311 in the first direction X, which can facilitate the arrangement of the third type of devices 303.

[0142] For example, Figure 5As shown, in the same second device column L2, the connecting part 312 of each first electrode 310 is located on the upper side of the main body part 311, and / or in the same second device row R2, the connecting part 312 of each first electrode 310 is located on the upper side of the main body part 311.

[0143] Optionally, the first control transistor T6 of the third circuit column E3 can be at least partially located on one side of the main body part 311 of the first device 301 and / or the second device 302 in the second direction Y.

[0144] Optionally, the source 181c and / or the drain 181d of the first control transistor T6 of the third circuit column E3 can be at least partially located between the projection on the substrate 110 of the main body part 311 of the first device 301 and the projection on the substrate 110 of the main body part 311 of the second device 302 in the second direction Y.

[0145] Optionally, the connecting part 312 of the third device 303 can be located between the main body part 311 of the first device 301 and the main body part 311 of the second device 302 in the second direction Y.

[0146] In these optional embodiments, by connecting the connecting part 312 of the third device 303 to one side of the main body part 311 in the first direction X, the connecting part 312 of the third device 303 can be connected to the first control transistor T6 in the third circuit column E3 arranged on one side of the main body part 311 of the first device 301 and the second device 302 in the second direction Y. Also, the connecting point between the connecting part 312 of the third device 303 and the pixel circuit 180 can be located between the main body part 311 of the first device 301 and the main body part 311 of the second device 302 in the second direction Y, so that the connecting part 312 of the third device 303 can not have an excessively large size, thereby reducing the possibility of disconnection of the first electrode 310 of the third device 303, and reducing the coupling interference between the light emitting devices 300, thereby improving the working effect of the display panel 10.

[0147] In some optional embodiments, the connecting part 312 of the third device 303 can be located on one side of the connecting part 312 of the first device 301 in the first direction X, or the connecting part 312 of the third device 303 can be located on one side of the connecting part 312 of the second device 302 in the first direction X.

[0148] Optionally, as shown in FIG. 1, the connecting part 312 of the third device 303 can be located on one side of the connecting part 312 of the first device 301 in the first direction X, or the connecting part 312 of the third device 303 can be located on one side of the connecting part 312 of the second device 302 in the first direction X. Figure 5As shown, the connecting portion 312 of the third type of device 303 can be located below the connecting portion 312 of the first type of device 301, or the connecting portion 312 of the third type of device 303 can be located below the connecting portion 312 of the second type of device 302.

[0149] Optionally, when the orthogonal projection of the first electrode 310 of the second device column L2 on the substrate 110 partially overlaps with the orthogonal projection of the first circuit column E1 on the substrate 110 and partially overlaps with the orthogonal projection of the third circuit column E3 on the substrate 110, the connecting portion 312 of the third type of device 303 can be located on one side of the connecting portion 312 of the first type of device 301 in the first direction X. When the orthogonal projection of the first electrode 310 of the second device column L2 on the substrate 110 partially overlaps with the orthogonal projection of the second circuit column E2 on the substrate 110 and partially overlaps with the orthogonal projection of the third circuit column E3 on the substrate 110, the connecting portion 312 of the third type of device 303 can be located on one side of the connecting portion 312 of the second type of device 302 in the first direction X.

[0150] In these optional embodiments, by setting the connecting portion 312 of the third type of device 303 on one side of the connecting portion 312 of the first type of device 301 in the first direction X, or setting the connecting portion 312 of the third type of device 303 on one side of the connecting portion 312 of the second type of device 302 in the first direction X, the interference between the connecting portion 312 of the third type of device 303 and the connecting portion 312 of the first type of device 301 can be reduced, and the interference between the connecting portion 312 of the third type of device 303 and the connecting portion 312 of the second type of device 302 can be reduced, which is conducive to the arrangement of each light emitting device 300, and thus is conducive to improving the pixel arrangement density of the display panel 10.

[0151] In some optional embodiments, the substrate 100 further includes a connection structure 190 arranged between the light emitting device 300 and the pixel circuit 180, the connection structure 190 includes a first connection structure 191, a second connection structure 192, and a third connection structure 193, the connecting portion 312 of the first type of device 301 is electrically connected to the pixel circuit 180 through the first connection structure 191, the connecting portion 312 of the second type of device 302 is electrically connected to the pixel circuit 180 through the second connection structure 192, and the connecting portion 312 of the third type of device 303 is electrically connected to the pixel circuit 180 through the third connection structure 193.

[0152] Optionally, the connecting portion 312 of the first type of device 301 is electrically connected to the second end of the first control transistor T6 in the first circuit column E1 through the first connecting structure 191, the connecting portion 312 of the second type of device 302 is electrically connected to the second end of the first control transistor T6 in the second circuit column E2 through the second connecting structure 192, and the connecting portion 312 of the third type of device 303 is electrically connected to the second end of the first control transistor T6 in the third circuit column E3 through the third connecting structure 193.

[0153] Optionally, the connecting structure 190 can be arranged in the substrate 100, and the connecting structure 190 can be arranged in various manners in the substrate 100. For example, the connecting structure 190 can be arranged between the first sub-layer 171 and the second sub-layer 172.

[0154] Optionally, the connecting structure 190 can be arranged in the same layer and made of the same material as the data signal line Vdata, so that the connecting structure 190 and the data signal line Vdata can be prepared in the same preparation step, which is beneficial to improving the preparation efficiency of the display panel 10. For example, the first power voltage signal line ELVDD, the data signal line Vdata, the connecting structure 190, and the in-plane wire FIAA extending along the first direction X can be arranged between the first sub-layer 171 and the second sub-layer 172.

[0155] In some optional embodiments, one end of the first connecting structure 191 away from the connecting portion 312 of the first type of device 301 and one end of the third connecting structure 193 away from the connecting portion 312 of the third type of device 303 are arranged adjacent to and spaced apart from each other in the second direction Y, and / or one end of the second connecting structure 192 away from the connecting portion 312 of the second type of device 302 and one end of the third connecting structure 193 away from the connecting portion 312 of the third type of device 303 are arranged adjacent to and spaced apart from each other in the second direction Y.

[0156] For example, when the orthographic projection of the first electrode 310 of the second device column L2 on the substrate 110 partially overlaps with the orthographic projection of the first circuit column E1 on the substrate 110 and partially overlaps with the orthographic projection of the third circuit column E3 on the substrate 110, one end of the third connecting structure 193 connected to the first electrode 310 corresponding to the second device column L2 away from the connecting portion 312 of the third type of device 303 can be arranged adjacent to and spaced apart from one end of the first connecting structure 191 away from the connecting portion 312 of the first type of device 301 in the second direction Y.

[0157] When the orthogonal projection of the first electrode 310 of the second device column L2 on the substrate 110 partially overlaps with the orthogonal projection of the second circuit column E2 on the substrate 110 and partially overlaps with the orthogonal projection of the third circuit column E3 on the substrate 110, the end of the third connecting structure 193 connected with the first electrode 310 corresponding to the second device column L2 away from the connecting part 312 of the third type device 303 can be arranged adjacent to and spaced apart from the end of the second connecting structure 192 away from the connecting part 312 of the second type device 302 in the second direction Y.

[0158] Optionally, the first connecting structure 191 can have a certain size in the first direction X and the second direction Y, so that the first electrode 310 of the first type device 301 is electrically connected to the pixel circuit 180 through the first connecting structure 191. The second connecting structure 192 can have a certain size in the first direction X and the second direction Y, so that the first electrode 310 of the second type device 302 is electrically connected to the pixel circuit 180 through the first connecting structure 191.

[0159] Optionally, the first control transistor T6 in the first circuit column E1 can be adjacent to the first control transistor T6 in the third circuit column E3 in the second direction Y, and / or the first control transistor T6 in the second circuit column E2 can be adjacent to the first control transistor T6 in the third circuit column E3 in the second direction Y.

[0160] In these optional embodiments, by arranging the end of the first connecting structure 191 away from the connecting part 312 of the first type device 301 adjacent to and spaced apart from the end of the third connecting structure 193 away from the connecting part 312 of the third type device 303 in the second direction Y, the connection position between the first connecting structure 191 and the pixel circuit 180 can be arranged adjacent to and spaced apart from the connection position between the third connecting structure 193 and the pixel circuit 180 in the second direction Y, which is conducive to adapting to the arrangement of the first circuit column E1 and the third circuit column E3 in the second direction Y, facilitating the electrical connection between the first connecting structure 191 and the second end of the first control transistor T6 in the first circuit column E1, and facilitating the electrical connection between the third connecting structure 193 and the second end of the first control transistor T6 in the third circuit column E3.

[0161] Similarly, by setting the second connecting structure 192 away from one end of the connecting part 312 of the second type device 302 and the third connecting structure 193 away from one end of the connecting part 312 of the third type device 303, and adjacent and spaced apart in the second direction Y, the connection position between the second connecting structure 192 and the pixel circuit 180 can be adjacent and spaced apart in the second direction Y from the connection position between the third connecting structure 193 and the pixel circuit 180, which is conducive to adapting to the arrangement of the second circuit column E2 and the third circuit column E3 along the second direction Y, facilitating the electrical connection between the second connecting structure 192 and the second end of the first control transistor T6 in the second circuit column E2, and facilitating the electrical connection between the third connecting structure 193 and the second end of the first control transistor T6 in the third circuit column E3.

[0162] Figure 7 is a partial structure schematic diagram of a pixel circuit 180 provided by an embodiment of the present application, Figures 8 to 12 is a partial structure schematic diagram of each film layer in a substrate 100 provided by an embodiment of the present application. Figure 7 The dashed box at the junction of the film layers in the above figure can indicate the connection position between the film layers.

[0163] As shown in the above figure, Figures 5 to 12 in some optional embodiments, the virtual symmetry axis DL extending along the first direction X extends through the first electrode 310 of the first device column L1, the adjacent first circuit column E1 and the third circuit column E3 are symmetrically arranged about the virtual symmetry axis DL extending along the first direction X, and / or the adjacent second circuit column E2 and the third circuit column E3 are symmetrically arranged about the virtual symmetry axis DL extending along the first direction X, and / or the adjacent data signal line Vdata is symmetrically arranged about the virtual symmetry axis DL extending along the first direction X.

[0164] Optionally, the virtual symmetry axis DL extending along the first direction X can extend through the first electrode 310 of the first type device 301 and / or the first electrode 310 of the second type device 302.

[0165] Optionally, the virtual symmetry axis DL extending along the first direction X can extend through the main body part 311 of the first electrode 310 of the first device column L1. Illustratively, the virtual symmetry axis DL extending along the first direction X can extend through the main body part 311 of the first electrode 310 of the first type device 301, and / or the virtual symmetry axis DL extending along the first direction X can extend through the main body part 311 of the first electrode 310 of the second type device 302.

[0166] Optionally, the adjacent first circuit column E1 and the third circuit column E3 are symmetrically arranged about a virtual symmetry axis DL extending along the first direction X, which can mean that the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged about the virtual symmetry axis DL extending along the first direction X.

[0167] Optionally, the adjacent second circuit column E2 and the third circuit column E3 are symmetrically arranged about a virtual symmetry axis DL extending along the first direction X, which can mean that the second circuit column E2 and the third circuit column E3 adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged about the virtual symmetry axis DL extending along the first direction X.

[0168] Optionally, the adjacent data signal lines Vdata are symmetrically arranged about a virtual symmetry axis DL extending along the first direction X, which can mean that the data signal lines Vdata adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged about the virtual symmetry axis DL extending along the first direction X.

[0169] Optionally, the adjacent in-plane wires FIAA can also be symmetrically arranged about a virtual symmetry axis DL extending along the first direction X. For example, the in-plane wires FIAA adjacent in the second direction Y and located on both sides of the virtual symmetry axis DL in the second direction Y can be symmetrically arranged about the virtual symmetry axis DL extending along the first direction X.

[0170] Optionally, any two circuit columns in the embodiments of the present application are symmetrically arranged about a virtual symmetry axis DL extending along the first direction X, which can mean that each transistor 181 in one of the circuit columns can be symmetrically arranged with the corresponding transistor 181 in the other of the circuit columns about the virtual symmetry axis DL extending along the first direction X, and the storage capacitor 182 in one of the circuit columns can be symmetrically arranged with the storage capacitor 182 in the other of the circuit columns about the virtual symmetry axis DL extending along the first direction X.

[0171] In these optional embodiments, by setting the adjacent first circuit column E1 and the third circuit column E3 to be symmetrically arranged about the virtual symmetry axis DL extending along the first direction X, the first control transistor T6 of the first circuit column E1 and the first control transistor T6 of the third circuit column E3 can be more symmetrically distributed on both sides of the first electrode 310 of the first device column L1, which is conducive to the connection part 312 of the first type of device 301 in the first device column L1 extending along the second direction Y and being electrically connected to the first control transistor T6 of the first circuit column E1, and is conducive to the connection part 312 of the third type of device 303 in the second device column L2 adjacent to the first device column L1 extending along the first direction X and being electrically connected to the first control transistor T6 of the third circuit column E3.

[0172] Similarly, by setting the adjacent second circuit column E2 and the third circuit column E3 to be symmetrically arranged about the virtual symmetry axis DL extending along the first direction X, the first control transistor T6 of the second circuit column E2 and the first control transistor T6 of the third circuit column E3 can be more symmetrically distributed on both sides of the first electrode 310 of the first device column L1, which is conducive to the connection part 312 of the second type of device 302 in the first device column L1 extending along the second direction Y and being electrically connected to the first control transistor T6 of the second circuit column E2, and is conducive to the connection part 312 of the third type of device 303 in the second device column L2 adjacent to the first device column L1 extending along the first direction X and being electrically connected to the first control transistor T6 of the third circuit column E3.

[0173] Therefore, by the aforementioned symmetrical relationship, the main body part 311 of the third type of device 303 is arranged below the gap between the main body part 311 of the first type of device 301 and the main body part 311 of the second type of device 302 in the second direction Y, which is conducive to improving the pixel arrangement density of the display panel 10, and further conducive to improving the display effect of the display panel 10.

[0174] In some optional embodiments, the second control transistor T5 is located on one side of the first control transistor T6 close to the virtual symmetry axis DL, the orthogonal projection of the first power voltage signal line ELVDD on the substrate 110 is arranged apart from the orthogonal projection of the first control transistor T6 on the substrate 110, and part of the orthogonal projection of the first power voltage signal line ELVDD on the substrate 110 is located between the orthogonal projection of the first control transistor T6 on the substrate 110 and the orthogonal projection of the virtual symmetry axis DL on the substrate 110.

[0175] In the optional embodiment, by setting the first power voltage signal line ELVDD to be spaced from the projection of the first control transistor T6 on the substrate 110, the arrangement of the first power voltage signal line ELVDD is less likely to interfere with the electrical connection between the first electrode 310 and the first control transistor T6. By setting the second control transistor T5 to be located on the side of the first control transistor T6 close to the virtual symmetry axis DL and setting the projection of the partial first power voltage signal line ELVDD on the substrate 110 to be located between the projection of the first control transistor T6 on the substrate 110 and the projection of the virtual symmetry axis DL on the substrate 110, the second control transistor T5 can be electrically connected with the first power voltage signal line ELVDD at the region between the first control transistor T6 and the virtual symmetry axis DL, which is conducive to reducing the interference of other devices in the substrate 100 with the electrical connection between the second control transistor T5 and the first power voltage signal line ELVDD.

[0176] In some optional embodiments, the projection of the first power voltage signal line ELVDD on the substrate 110 at least partially overlaps with the projection of the first electrode 310 of the third-type device 303 on the substrate 110, and the first power voltage signal line ELVDD is provided with a yielding opening Hole on the side of the first control transistor T6 away from the substrate 110, and the connection part 312 of the first electrode 310 is electrically connected with the first control transistor T6 via the yielding opening Hole.

[0177] Optionally, the yielding opening Hole can be at least partially located between the main body parts 311 of two third-type devices 303 adjacent in the first direction X.

[0178] Optionally, the connection structure 190 can be located in the yielding opening Hole, and the first power voltage signal line ELVDD can be arranged around the connection structure 190.

[0179] Optionally, the yielding opening Hole can be at least partially located between the main body parts 311 of the first device columns L1 adjacent in the first direction X. Optionally, the connection part 312 of each of the first-type device 301, the second-type device 302 and the third-type device 303 can extend to the side of the yielding opening Hole away from the substrate 110.

[0180] Optionally, the line width of the first power voltage signal line ELVDD on the two sides of the yielding opening Hole in the second direction Y can be smaller than the line width of the first power voltage signal line ELVDD on the two sides of the yielding opening Hole in the first direction X.

[0181] Optionally, in the two circuit columns adjacent to the under the hole, one of the second control transistors T5 of the circuit column can be electrically connected with the first power voltage signal line ELVDD located on one side of the hole in the second direction Y, and the second control transistor T5 of the other circuit column can be electrically connected with the first power voltage signal line ELVDD located on the other side of the hole in the second direction Y. For example, in the first circuit column E1 and the third circuit column E3 adjacent to the hole, the second control transistor T5 of the first circuit column E1 can be electrically connected with the first power voltage signal line ELVDD located on one side of the hole in the second direction Y, and the second control transistor T5 of the third circuit column E3 can be electrically connected with the first power voltage signal line ELVDD located on the other side of the hole in the second direction Y. For another example, in the second circuit column E2 and the third circuit column E3 adjacent to the hole, the second control transistor T5 of the second circuit column E2 can be electrically connected with the first power voltage signal line ELVDD located on one side of the hole in the second direction Y, and the second control transistor T5 of the third circuit column E3 can be electrically connected with the first power voltage signal line ELVDD located on the other side of the hole in the second direction Y.

[0182] In these optional embodiments, the first power voltage signal line ELVDD can extend through the under of the first electrode 310 of the third type device 303, and by opening the hole on the first power voltage signal line ELVDD, it is beneficial to reduce the arrangement interference between the first power voltage signal line ELVDD and other device structures in the display panel 10, so that the first electrode 310 of each light emitting device 300 can be electrically connected with the pixel circuit 180 via the hole, for example, so that the first electrode 310 of each light emitting device 300 can be electrically connected with the connection structure 190 via the hole, to be electrically connected with the first control transistor T6 in the pixel circuit 180 through the connection structure 190.

[0183] In some optional embodiments, a single hole is located on the side of the first control transistor T6 of at least two pixel circuits 180 adjacent in the second direction Y away from the substrate 110.

[0184] For example, the single hole can be located on the side of the first control transistor T6 of the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y away from the substrate 110, or the single hole can be located on the side of the first control transistor T6 of the second circuit column and the third circuit column E3 adjacent in the second direction Y away from the substrate 110.

[0185] Optionally, the single accommodating opening Hole can accommodate at least two connection structures 190. For example, the single accommodating opening Hole can accommodate a single first connection structure 191 and a single third connection structure 193, or the single accommodating opening Hole can accommodate a single second connection structure 192 and a single third connection structure 193.

[0186] In these optional embodiments, by arranging the single accommodating opening Hole on the side of the first control transistor T6 of the at least two pixel circuits 180 adjacent in the second direction Y away from the substrate 110, the at least two pairs of pixel circuits 180 and the light emitting device 300 can be electrically connected at the single accommodating opening Hole, which can facilitate the arrangement of the first power voltage signal line ELVDD and also facilitate reducing the spacing between the pixel circuits 180 adjacent in the second direction Y, for example, facilitating reducing the spacing between the first control transistors T6 of the pixel circuits 180 adjacent in the second direction Y, thereby facilitating improving the arrangement effect of the light emitting device 300 in the display panel 10.

[0187] In some optional embodiments, the data write transistor T2 is located on the side of the first control transistor T6 close to the virtual symmetry axis DL, the orthogonal projection of the data signal line Vdata on the substrate 110 is arranged apart from the orthogonal projection of the first control transistor T6 on the substrate 110, and part of the orthogonal projection of the data signal line Vdata on the substrate 110 is located between the orthogonal projection of the first control transistor T6 on the substrate 110 and the orthogonal projection of the virtual symmetry axis DL on the substrate 110.

[0188] Optionally, the data signal line Vdata can be located on the side of the first power voltage signal line ELVDD facing the virtual symmetry axis DL.

[0189] In this optional embodiment, by arranging the orthogonal projection of the data signal line Vdata on the substrate 110 apart from the orthogonal projection of the first control transistor T6 on the substrate 110, the arrangement of the data signal line Vdata is less likely to interfere with the electrical connection between the first electrode 310 and the first control transistor T6. By arranging the data write transistor T2 on the side of the first control transistor T6 close to the virtual symmetry axis DL, and arranging part of the orthogonal projection of the data signal line Vdata on the substrate 110 between the orthogonal projection of the first control transistor T6 on the substrate 110 and the orthogonal projection of the virtual symmetry axis DL on the substrate 110, the data write transistor T2 can be electrically connected with the data signal line Vdata in the region between the first control transistor T6 and the virtual symmetry axis DL, which is conducive to reducing the interference of other devices in the substrate 100 with the electrical connection between the data write transistor T2 and the data signal line Vdata.

[0190] Optionally, in a single pixel circuit 180, the threshold compensation transistor T3 and the second reset transistor T7 may be disposed on opposite sides of the first control transistor T6 in the first direction X, and the first reset transistor T4 may be disposed on the side of the threshold compensation transistor T3 away from the first control transistor T6 in the first direction X. The driving transistor T1 may be disposed on the side of the first control transistor T6 and / or the threshold compensation transistor T3 near the virtual axis of symmetry DL in the second direction Y. The second control transistor T5 and the data writing transistor T2 may also be disposed on opposite sides of the driving transistor T1 in the first direction X. The bias adjustment transistor T8 may be disposed on the side of the second control transistor T5 away from the driving transistor T1 in the first direction X. The first plate 182a and the second plate 182b of the storage capacitor 182 may be located on the side of the semiconductor 181a of the driving transistor T1 away from the substrate 110.

[0191] By reasonably setting the relative positional relationship between each transistor 181 and storage capacitor 182 in the pixel circuit 180, it is not only convenient to realize the electrical connection between each device structure in the pixel circuit 180, but also to facilitate the connection between the light-emitting device 300 and the pixel circuit 180, the electrical connection between the first power supply voltage signal line ELVDD and the pixel circuit 180, and the electrical connection between the data signal line Vdata and the pixel circuit 180.

[0192] In some embodiments of this application, the storage capacitor 182 and each transistor 181 in the pixel circuit 180 are arranged in various ways on the substrate 100.

[0193] Optional, such as Figure 8 As shown, the semiconductors 181a of the driving transistor T1, data writing transistor T2, second control transistor T5, first control transistor T6, second reset transistor T7, and bias adjustment transistor T8 can all be located on the same layer. For example, the semiconductors 181a of the driving transistor T1, data writing transistor T2, second control transistor T5, first control transistor T6, second reset transistor T7, and bias adjustment transistor T8 can all be located between the substrate 110 and the first insulating layer 120.

[0194] like Figure 9As shown, the first plate 182a of the storage capacitor 182, the gate 181b of the data writing transistor T2, the gate 181b of the first control transistor T6, the gate 181b of the second control transistor T5, the gate 181b of the second reset transistor T7, the gate 181b of the bias adjustment transistor T8, the second scan signal line S2, the fourth scan signal line S4, and the light emission control signal line EM can all be located on the same layer. For example, the gate 181b of the data writing transistor T2, the gate 181b of the first control transistor T6, the gate 181b of the second control transistor T5, the gate 181b of the second reset transistor T7, the gate 181b of the bias adjustment transistor T8, the second scan signal line S2, the fourth scan signal line S4, and the light emission control signal line EM can all be located between the first insulating layer 120 and the second insulating layer 130.

[0195] like Figure 10 As shown, the second electrode 182b of the storage capacitor 182, the first scan signal line S1, and the third scan signal line S3 can all be located on the same layer. For example, the second electrode 182b of the storage capacitor 182, the first scan signal line S1, and the third scan signal line S3 can all be located between the second insulating layer 130 and the third insulating layer 140.

[0196] like Figure 11 As shown, the semiconductor 181a of the threshold compensation transistor T3 and the semiconductor 181a of the first reset transistor T4 may be located on the same layer. For example, the semiconductor 181a of the threshold compensation transistor T3 and the semiconductor 181a of the first reset transistor T4 may be located between the third insulating layer 140 and the fourth insulating layer 150 on the same layer.

[0197] like Figure 12 As shown, the source 181c and drain 181d of each transistor 181 in the pixel circuit 180 (e.g., driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first reset transistor T4, second control transistor T5, first control transistor T6, second reset transistor T7, and bias adjustment transistor T8) can all be located on the same layer. For example, the source 181c and drain 181d of each transistor 181 in the pixel circuit 180 can all be located between the fourth insulating layer 150 and the fifth insulating layer 160.

[0198] Optionally, a via may be provided on the second plate 182b of the storage capacitor 182 so that the second terminal of the first reset transistor T4 and the second terminal of the threshold compensation transistor T3 can be electrically connected to the first plate 182a of the storage capacitor 182 via the via on the second plate 182b.

[0199] Figure 13 This is a schematic diagram of the structure of a pixel circuit 180 provided in another embodiment of this application.Figure 14 is a partial structure schematic diagram of a shielding structure BS provided by an embodiment of the present application, Figure 15 is a partial structure schematic diagram of a display panel 10 provided by another embodiment of the present application, Figure 16 is a partial enlarged structure schematic diagram of a display panel 10 provided by an embodiment of the present application. Figure 13 The dashed box at the interface of the middle film layer can indicate the connection position between the film layers.

[0200] Optionally, Figure 15 the area in the dashed box in Figure 16 may indicate the arrangement position of the second end of the partial driving transistor T1 or the arrangement position of the first end of the partial first control transistor T6. Exemplarily, Figure 15 the area in the dashed box in Figure 16 may indicate the arrangement position of the second end of the driving transistor T1 in the third circuit column E3, or Figure 15 the area in the dashed box in Figure 16 may indicate the arrangement position of the first end of the first control transistor T6 in the third circuit column E3.

[0201] As shown in Figures 13 to 16 , in some optional embodiments, the substrate 100 further includes a shielding structure BS arranged between the first electrode 310 and the pixel circuit 180.

[0202] Optionally, the shielding structure BS can be arranged between the pixel circuit 180 and the first electrode 310 of at least one of the first circuit column E1, the second circuit column E2 and the third circuit column E3.

[0203] In some embodiments of the present application, since in the same first device column L1, the connecting portions 312 of the first type of devices 301 are all connected to one side of the main body portion 311 in the second direction Y, and the connecting portions 312 of the second type of devices 302 are all connected to the other side of the main body portion 311 in the second direction Y. Therefore, in two adjacent pixel circuits 180 in the first direction X (for example, two adjacent pixel circuits 180 in the first circuit column E1, the second circuit column E2 or the third circuit column E3 in the first direction X), the overlapping area between one of the pixel circuits 180 and the first electrode 310 can be different from the overlapping area between the other of the pixel circuits 180 and the first electrode 310 (for example, in two adjacent first device rows R1, the overlapping area between the first electrode 310 in one of the first device rows R1 and the second end of the corresponding driving transistor T1 in the substrate 110 is greater than the overlapping area between the first electrode 310 in the other of the first device rows R1 and the second end of the corresponding driving transistor T1 in the substrate 110), so that the interference of the first electrode 310 on the two adjacent pixel circuits 180 in the first direction X is different, thereby easily causing the light emitting effect between the two light emitting devices 300 with the same light emitting color electrically connected to the adjacent pixel circuits 180 in the first direction X to have a difference, and further easily causing the display panel 10 to have display unevenness.

[0204] Therefore, by arranging the shielding structure BS between the first electrode 310 and the pixel circuit 180, the interference of the first electrode 310 on the pixel circuit 180 can be better limited, so that the two adjacent pixel circuits 180 in the first direction X can both not be easily affected by the signal interference of the first electrode 310, and have better working stability, thereby enabling the light emitting effect between the two light emitting devices 300 with the same light emitting color electrically connected to the adjacent pixel circuits 180 in the first direction X to be the same or similar, which is beneficial to improving the display uniformity of the display panel 10.

[0205] As an example, when the light emitting color of the third type of device 303 is green, compared with the first type of device 301 and the second type of device 302, since the third type of device 303 is more easily affected by the fluctuation of the working stability of the pixel circuit 180, when the position arrangement of the shielding structure BS is limited, the shielding structure BS can be preferentially arranged between the pixel circuit 180 electrically connected to the third type of device 303 and the first electrode 310 of the third type of device 303, that is, the shielding structure BS can be preferentially arranged between the pixel circuit 180 in the third circuit column E3 and the first electrode 310 of the third type of device 303, thereby better improving the working stability of the second device column L2, and further being beneficial to improving the display uniformity of the third type of device 303 of the display panel 10 in the first direction X.

[0206] In some embodiments of the present application, the shielding structure BS can not need to completely cover the pixel circuit 180, i.e., the orthogonal projection of the partial pixel circuit 180 on the substrate 110 can be located outside the orthogonal projection of the shielding structure BS on the substrate 110, so as to facilitate the electrical connection between the various device structures in the display panel 10 and the pixel circuit 180.

[0207] For example, the shielding structure BS can be arranged only above the position in the pixel circuit 180 which is more affected by the signal interference in the first electrode 310.

[0208] In some optional embodiments, the orthogonal projection of the shielding structure BS on the substrate 110 at least partially overlaps the orthogonal projection of the first control transistor T6 on the substrate 110, and / or the orthogonal projection of the shielding structure BS on the substrate 110 at least partially overlaps the orthogonal projection of the driving transistor T1 on the substrate 110.

[0209] Optionally, when the second end of the driving transistor T1 is electrically connected to the first end of the first control transistor T6, and the second end of the first control transistor T6 is electrically connected to the first electrode 310, the orthogonal projection of the shielding structure BS on the substrate 110 can at least partially overlap the orthogonal projection of the first end of the first control transistor T6 on the substrate 110, and / or the orthogonal projection of the shielding structure BS on the substrate 110 can at least partially overlap the orthogonal projection of the second end of the driving transistor T1 on the substrate 110.

[0210] For example, the orthogonal projection of the shielding structure BS on the substrate 110 can at least partially overlap the orthogonal projection of the source 181c of the first control transistor T6 on the substrate 110, and / or the orthogonal projection of the shielding structure BS on the substrate 110 can at least partially overlap the orthogonal projection of the drain 181d of the driving transistor T1 on the substrate 110.

[0211] Optionally, the orthogonal projection of the shielding structure BS on the substrate 110 can at least partially overlap the orthogonal projection of the first control transistor T6 of at least one of the first circuit column E1, the second circuit column E2 and the third circuit column E3 on the substrate 110, and / or the orthogonal projection of the shielding structure BS on the substrate 110 can at least partially overlap the orthogonal projection of the driving transistor T1 of at least one of the first circuit column E1, the second circuit column E2 and the third circuit column E3 on the substrate 110.

[0212] Optionally, in the two adjacent first device rows R1, the overlapping area of the normal projection of the first electrode 310 in one of the first device rows R1 on the substrate 110 and the normal projection of the second end of the corresponding driving transistor T1 on the substrate 110 is greater than the overlapping area of the normal projection of the first electrode 310 in the other of the first device rows R1 on the substrate 110 and the normal projection of the second end of the corresponding driving transistor T1 on the substrate 110, and the normal projection of the shielding structure BS on the substrate 110 can at least partially overlap the normal projection of the second end of the driving transistor T1 on the substrate 110.

[0213] In these optional embodiments, since the first control transistor T6 in the pixel circuit 180 is more susceptible to signal interference in the first electrode 310, by arranging the shielding structure BS between the first control transistor T6 and the first electrode 310 and arranging the shielding structure BS between the driving transistor T1 and the first electrode 310, the limiting effect of the shielding structure BS on signal interference can be better improved, which is beneficial to improving the display uniformity of the display panel 10.

[0214] In some optional embodiments, the display panel 10 includes a direct-current signal end, and the shielding structure BS is electrically connected with the direct-current signal end, so that the shielding structure BS can have a relatively stable potential, which is beneficial to improving the limiting effect of the shielding structure BS on signal interference.

[0215] For example, the direct-current signal end includes a power voltage signal end, and the first power voltage signal line ELVDD can be electrically connected with the power voltage signal end, and the shielding structure BS can be electrically connected with the direct-current signal end through the first power voltage signal line ELVDD.

[0216] Optionally, in the circuit repeating unit EG, a single shielding structure BS can be arranged corresponding to the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y, that is, the single shielding structure BS is arranged on the side away from the substrate 110 of the first circuit column E1 and the third circuit column E3 adjacent in the second direction Y, so that the single shielding structure BS can be used to limit the signal in the first electrode 310 from interfering with the first circuit column E1 and the third circuit column E3 at the same time.

[0217] Similarly, in the circuit repeating unit EG, a single shielding structure BS can be arranged corresponding to the second circuit column E2 and the third circuit column E3 adjacent in the second direction Y, that is, the single shielding structure BS is arranged on the side away from the substrate 110 of the second circuit column E2 and the third circuit column E3 adjacent in the second direction Y, so that the single shielding structure BS can be used to limit the signal in the first electrode 310 from interfering with the second circuit column E2 and the third circuit column E3 at the same time.

[0218] Optionally, the shielding structure BS can be arranged in the substrate 100 in various manners. For example, the shielding structure BS can be arranged between the fifth insulating layer 160 and the sixth insulating layer 170.

[0219] In some optional embodiments, the substrate 100 further includes a conductive structure ES arranged between the first power voltage signal line ELVDD and the pixel circuit 180, the first power voltage signal line ELVDD can be electrically connected to the pixel circuit 180 through the conductive structure ES, and at least part of the conductive structure ES is multiplexed as the shielding structure BS.

[0220] For example, the conductive structure ES can be arranged between the fifth insulating layer 160 and the sixth insulating layer 170, and the first power voltage signal line ELVDD can be electrically connected to the second control transistor T5 and the second plate 182b of the storage capacitor 182 in the pixel circuit 180 through the conductive structure ES.

[0221] Optionally, the conductive structure ES can include an integrally formed conductive part ES1 and a shielding part ES2, the conductive part ES1 can be electrically connected to the second control transistor T5 and the second plate 182b of the storage capacitor 182 in the pixel circuit 180, the normal projection of the virtual symmetry axis DL on the substrate 110 can pass through the normal projection of the conductive part ES1 on the substrate 110, and the shielding part ES2 can be arranged on both sides of the conductive part ES1 in the second direction Y.

[0222] Optionally, the shielding part ES2 can be arranged between the first electrode 310 and the pixel circuit 180. For example, the normal projection of the shielding part ES2 on the substrate 110 at least partially overlaps with the normal projection of the first control transistor T6 on the substrate 110, and / or the normal projection of the shielding part ES2 on the substrate 110 at least partially overlaps with the normal projection of the driving transistor T1 on the substrate 110.

[0223] In these optional embodiments, by multiplexing at least part of the conductive structure ES used for electrically connecting the first power voltage signal line ELVDD and the pixel circuit 180 as the shielding structure BS, the electrical connection between the shielding structure BS and the direct current signal end can be facilitated, and the preparation efficiency of the display panel 10 can be improved. Moreover, by arranging at least part of the conductive structure ES as the shielding structure BS, it is not necessary to add a film layer for serving as the shielding structure BS in the display panel 10, so that the thickness of the display panel 10 can be reduced.

[0224] The display device provided by the second aspect of the present application comprises the display panel 10 of any one of the above embodiments. Therefore, the display device provided by the second aspect of the present application has the beneficial effects of the display panel 10 of any one of the above embodiments of the first aspect, which will not be described here again.

[0225] The display device in the embodiments of the present application includes but is not limited to a mobile phone, a personal digital assistant (PDA), a tablet computer, an electronic book, a television, an access control, a smart fixed telephone, a console, and the like device having a display function.

[0226] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details and do not limit the present application to only the specific embodiments. Obviously, many modifications and variations can be made according to the above description. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited by the claims and their entire scope and equivalents.

Claims

1. A display panel, characterized in that, include: A substrate, the substrate including a substrate and a plurality of pixel circuits disposed on one side of the substrate; A light-emitting device is disposed on one side of the substrate. In a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially. The first electrode includes a main body portion and a connecting portion connected to the main body portion and protruding relative to the main body portion. The light-emitting device includes multiple first-type devices and multiple second-type devices. The first-type devices and second-type devices are alternately arranged along a first direction to form a first device column, and the first-type devices and second-type devices are alternately arranged along a second direction to form a first device row. The light-emitting color of the first-type devices is different from the light-emitting color of the second-type devices. The first direction and the second direction intersect. In the same first device array, the connecting portions of the first type of devices are all connected to one side of the main body in the second direction, and the connecting portions of the second type of devices are all connected to the other side of the main body in the second direction. In the same row of the first devices, the connection portions of each of the first electrodes are located on the same side of the main body in the second direction. The pixel circuit includes a storage capacitor, a first control transistor electrically connected to the connection portion, a driving transistor electrically connected to the first control transistor, and a second control transistor electrically connected to the end of the driving transistor away from the first control transistor. The storage capacitor includes a first electrode plate and a second electrode plate located on the side of the first electrode plate opposite to the substrate. The substrate further includes a shielding structure disposed between the first electrode and the pixel circuit. The display panel further includes a first power supply voltage signal line, and the substrate further includes a conductive structure disposed between the first power supply voltage signal line and the pixel circuit. The first power supply voltage signal line is connected to the conductive structure. The conductive structure includes an integrally formed conductive portion and a shielding portion. The conductive portion is electrically connected to the second control transistor and the second electrode plate. The shielding portion is disposed on both sides of the conductive portion in the second direction. In two adjacent rows of the first device, the overlap area of ​​the orthographic projection of the first electrode on the substrate and the orthographic projection of the corresponding second terminal of the driving transistor on the substrate in one row of the first device is greater than the overlap area of ​​the orthographic projection of the first electrode on the substrate and the orthographic projection of the corresponding second terminal of the driving transistor on the substrate in the other row of the first device. The conductive structure is reused as the shielding structure, and the orthographic projection of the shielding portion on the substrate at least partially overlaps with the orthographic projection of the second end of the driving transistor on the substrate. The two shielding portions of a single conductive structure are respectively disposed corresponding to the second ends of the driving transistors in the two pixel circuits arranged in the second direction.

2. The display panel according to claim 1, characterized in that, At least two of the pixel circuits are arranged in a first direction to form a circuit array, and the display panel further includes a data signal line extending along the first direction. Each pixel circuit in the same circuit array is electrically connected to the same data signal line. The circuit array includes a first circuit array and a second circuit array, which are arranged alternately along the second direction. The connection portion of each of the first type of devices in the first device column is electrically connected to each of the pixel circuits in the same first circuit column, and / or, the connection portion of each of the second type of devices in the first device column is electrically connected to each of the pixel circuits in the same second circuit column.

3. The display panel according to claim 2, characterized in that, In two adjacent columns of the first device, the connection portion of each first type of device is electrically connected to each pixel circuit in the same first circuit column, or the connection portion of each second type of device is electrically connected to each pixel circuit in the same second circuit column.

4. The display panel according to claim 2, characterized in that, The first control transistor is at least partially located on one side of the body portion of the first type of device and / or the second type of device in the second direction.

5. The display panel according to claim 2, characterized in that, The light-emitting device further includes multiple third-type devices whose light-emitting colors are different from both the first-type and second-type devices. These third-type devices are arranged along the first direction to form a second device column. The first and second device columns are arranged alternately along the second direction. The circuit column further includes a third circuit column. The first, second, and third circuit columns are arranged alternately along the second direction, and at least one third circuit column is positioned between adjacent first and second circuit columns. The connection portion of each of the third type devices in the second device column is electrically connected to each of the pixel circuits in the same third circuit column.

6. The display panel according to claim 5, characterized in that, In two adjacent columns of the first device columns, the orthographic projection of the first electrode of one column of the first device column onto the substrate overlaps with the orthographic projection of the first circuit column onto the substrate, and also overlaps with the orthographic projection of the third circuit column onto the substrate. The orthographic projection of the first electrode of the first device column on the substrate overlaps with the orthographic projection of the second circuit column on the substrate, and also overlaps with the orthographic projection of the third circuit column on the substrate. And / or, in two adjacent columns of the second device, the orthographic projection of the first electrode of one column of the second device overlaps with the orthographic projection of the first circuit column on the substrate, and also overlaps with the orthographic projection of the third circuit column on the substrate. The orthographic projection of the first electrode of the second device column on the substrate overlaps with the orthographic projection of the second circuit column on the substrate, and also overlaps with the orthographic projection of the third circuit column on the substrate.

7. The display panel according to claim 5, characterized in that, Multiple third-type devices are arranged along the second direction to form a second device row, and the first device row and the second device row are arranged alternately along the first direction. The connecting portion of the third type of device is connected to one side of the main body in the first direction.

8. The display panel according to claim 7, characterized in that, In the same second device array, the connection portion of each first electrode is located on the same side of the main body in the first direction. And / or, in the same row of the second devices, the connection portion of each of the first electrodes is located on the same side of the main body portion in the first direction.

9. The display panel according to claim 8, characterized in that, The connection portion of the third type of device is located on one side of the connection portion of the first type of device in the first direction. Alternatively, the connection portion of the third type of device may be located on one side of the connection portion of the second type of device in the first direction.

10. The display panel according to claim 9, characterized in that, The substrate further includes a connection structure disposed between the light-emitting device and the pixel circuit. The connection structure includes a first connection structure, a second connection structure, and a third connection structure. The connection portion of the first type of device is electrically connected to the pixel circuit through the first connection structure, the connection portion of the second type of device is electrically connected to the pixel circuit through the second connection structure, and the connection portion of the third type of device is electrically connected to the pixel circuit through the third connection structure. The end of the first connection structure away from the connection portion of the first type of device and the end of the third connection structure away from the connection portion of the third type of device are adjacent to each other and spaced apart in the second direction. And / or, one end of the second connection structure away from the connection portion of the second type of device and one end of the third connection structure away from the connection portion of the third type of device are adjacent to and spaced apart in the second direction.

11. The display panel according to claim 5, characterized in that, A virtual axis of symmetry extending along the first direction passes through the first electrode of the first device array. The adjacent first circuit columns and the third circuit columns are symmetrically arranged about the virtual axis of symmetry extending along the first direction, and / or the adjacent second circuit columns and the third circuit columns are symmetrically arranged about the virtual axis of symmetry extending along the first direction, and / or the adjacent data signal lines are symmetrically arranged about the virtual axis of symmetry extending along the first direction.

12. The display panel according to claim 11, characterized in that, The second control transistor is located on the side of the first control transistor closer to the virtual axis of symmetry, and the end of the second control transistor away from the driving transistor is electrically connected to the first power supply voltage signal line. The orthographic projection of the first power supply voltage signal line on the substrate and the orthographic projection of the first control transistor on the substrate are spaced apart, and a portion of the orthographic projection of the first power supply voltage signal line on the substrate is located between the orthographic projection of the first control transistor on the substrate and the orthographic projection of the virtual axis of symmetry on the substrate.

13. The display panel according to claim 12, characterized in that, The first power supply voltage signal line extends along the first direction, and a plurality of the first power supply voltage signal lines are arranged at intervals along the second direction. The orthographic projection of the first power supply voltage signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the third type of device on the substrate. The first power supply voltage signal line has a clearance opening on the side of the first control transistor away from the substrate, and the connection portion of the first electrode is electrically connected to the first control transistor through the clearance opening.

14. The display panel according to claim 13, characterized in that, The single clearance opening is located on the side of the first control transistor of at least two adjacent pixel circuits in the second direction that faces away from the substrate.

15. The display panel according to claim 12, characterized in that, The pixel circuit further includes a data write transistor electrically connected to one end of the second control transistor near the driving transistor and the other end of the driving transistor away from the first control transistor. The end of the data write transistor away from the driving transistor is electrically connected to the data signal line. The data write transistor is located on the side of the first control transistor near the virtual axis of symmetry. The orthographic projection of the data signal line on the substrate is spaced apart from the orthographic projection of the first control transistor on the substrate, and a portion of the orthographic projection of the data signal line on the substrate is located between the orthographic projection of the first control transistor on the substrate and the orthographic projection of the virtual axis of symmetry on the substrate.

16. The display panel according to any one of claims 11 to 15, characterized in that, The first and second plates of the storage capacitor are located on the side of the semiconductor of the driving transistor facing away from the substrate, and the second control transistor is located on the side of the first control transistor closer to the virtual axis of symmetry, and the second control transistor is located on the side of the driving transistor in the first direction. The second terminal of the driving transistor is electrically connected to the first terminal of the first control transistor, and the second terminal of the first control transistor is electrically connected to the first electrode.

17. The display panel according to any one of claims 11 to 15, characterized in that, The orthogonal projection of the virtual axis of symmetry onto the substrate is via the orthogonal projection of the conductive portion onto the substrate.

18. The display panel according to any one of claims 11 to 15, characterized in that, The two shielding portions of a single conductive structure are respectively disposed at the second ends of the driving transistors in the pixel circuits located on both sides of the virtual axis of symmetry in the second direction.

19. The display panel according to any one of claims 1 to 15, characterized in that, The display panel includes a DC signal terminal, and the shielding structure is electrically connected to the DC signal terminal. The DC signal terminal includes a power supply voltage signal terminal, and the power supply voltage signal terminal is electrically connected to the first power supply voltage signal line.

20. The display panel according to any one of claims 1 to 15, characterized in that, The orthographic projection of the shielding structure onto the substrate at least partially overlaps with the orthographic projection of the first control transistor onto the substrate.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 20.

Images