Process integration method and structure of novel memristor

Abstract

The invention discloses a process integration method of a novel memristor, and belongs to the field of microelectronics, the novel memristor comprises a conductive bridge memristor and an interconnection structure, the size of an electrolyte layer of the conductive bridge memristor is limited by silicon nitride, the silicon nitride is etched by multi-angle ion beams, the electrolyte layer is located between an active electrode and an inert electrode, and the active electrode is connected with the interconnection structure. And in the silicon nitride etching region, the preparation of the high-consistency novel memristor is realized.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and particularly to a process integration method and structure of a novel memristive device. Background Art

[0002] Aiming at the bottleneck problem of the separation of storage and computing in the von Neumann architecture, by embedding computing capabilities in the memory and performing two-dimensional and three-dimensional matrix multiplication / addition operations with a new operation architecture, namely, memory-computation integration. Memristors have the advantages of extremely low power consumption, high integration density, and compatibility with CMOS processes, making them one of the important technical routes for memory-computation integration technology.

[0003] In recent years, significant progress has been made in the research of memristors in terms of material optimization, structure optimization, and process integration. However, the research mainly focuses on the laboratory level and it is difficult to move towards industrialization. The reason is that the consistency of memristor devices in the memory-computation array is poor, which seriously affects the computing accuracy, circuit reliability, and design complexity of the memory-computation array.

[0004] By optimizing the structure of memristor devices and restricting the growth path and range of conductive filaments, although the consistency can be effectively improved, however, limited by the process method, especially the reaction between the etching gas and the electrode surface during the etching process, the device structures developed in the laboratory are difficult to be directly industrialized, resulting in poor consistency of the memory-computation array used in circuits. Summary of the Invention

[0005] The purpose of the present invention is to provide a process integration method and structure of a novel memristive device to solve the problems in the background art.

[0006] To solve the above technical problems, the present invention provides a process integration method of a novel memristive device, including: Depositing silicon dioxide, first silicon nitride, and an active electrode interconnect structure silicon dioxide deposition layer on a silicon substrate in sequence, and forming a first active electrode interconnect structure groove through photolithography and etching; Forming an active electrode interconnect structure barrier layer and an active electrode interconnect structure metal filling layer in the first active electrode interconnect structure groove, and depositing second silicon nitride on the surface after chemical mechanical polishing; Depositing a layer of active electrode silicon dioxide deposition layer on the surface of the second silicon nitride, and forming a second active electrode interconnect structure groove through photolithography and etching; Forming an active electrode silicon dioxide barrier layer and an active electrode in the second active electrode interconnect structure groove, and depositing third silicon nitride on the surface after chemical mechanical polishing; Remove a part of the third silicon nitride to form a silicon nitride groove and form an electrolyte layer inside. Deposit an inert electrode on the surface of the electrolyte layer to form an inert electrode; deposit an inert electrode silicon dioxide deposition layer on the entire surface, and form an interconnect structure groove through photolithography and etching; Form an inert electrode interconnect structure barrier layer and an inert electrode interconnect structure metal filling layer in the interconnect structure groove, and perform chemical mechanical polishing; Deposit a fourth silicon nitride and an active electrode silicon dioxide deposition layer on the entire surface in sequence, and form a metal lead-out terminal groove through photolithography and etching; Form a metal lead-out terminal silicon dioxide barrier layer and a metal lead-out terminal metal filling layer in the metal lead-out terminal groove, and perform chemical mechanical polishing to complete the preparation of the novel memristive device.

[0007] In one embodiment, the material of the active electrode interconnect structure barrier layer is Ta, the material of the active electrode interconnect structure metal filling layer is Cu, and the material of the active electrode is any combination of copper, copper-silver alloy, and copper-titanium.

[0008] In one embodiment, the material of the electrolyte layer is an oxide or a chalcogenide compound; among them, the chalcogenide compound is deposited by magnetron sputtering with a thickness of 20 - 100 nm; the oxide is deposited by atomic layer deposition with a thickness of 3 - 10 nm.

[0009] In one embodiment, the thickness of the active electrode interconnect structure silicon dioxide deposition layer is 200 - 500 nm, the thickness of the active electrode silicon dioxide deposition layer is 200 - 500 nm, the thickness of the inert electrode silicon dioxide deposition layer is 400 - 1000 nm, and the thickness of the active electrode silicon dioxide deposition layer is 200 - 1000 nm.

[0010] In one embodiment, the thicknesses of the first silicon nitride, the second silicon nitride, the third silicon nitride, and the fourth silicon nitride are all 50 - 300 nm.

[0011] In one embodiment, the inert electrode interconnect structure barrier layer in the interconnect structure groove above the second active electrode interconnect structure groove contacts the inert electrode, and the inert electrode interconnect structure barrier layer in the remaining interconnect structure grooves contacts the metal filling layer.

[0012] In one embodiment, the third silicon nitride is etched by multi-angle ion beam etching, and its gas configuration is Ar, the stage angle is 0 - 170°, the rotation speed is 5 - 20 rpm, and the ion energy is 50 - 1500 eV.

[0013] In one embodiment, the electrolyte layer and the inert electrode are etched using ion beam etching, with the gas configured as Ar, the stage angle being 0 to 170°, the rotation speed being 5 to 20 rpm, and the ion energy range being 50 to 1500 eV.

[0014] The present invention also provides a novel memristive device structure prepared by the above method, including a conductive bridge type memristive device and an interconnection structure; wherein, The conductive bridge type memristive device is composed of a bottom active electrode structure, an electrolyte layer, a top inert electrode structure, and a metal lead-out terminal structure, The interconnection structure includes an active electrode interconnection structure silicon dioxide deposition layer, an active electrode interconnection structure barrier layer, and an active electrode interconnection structure metal filling layer; The bottom active electrode structure includes an active electrode silicon dioxide deposition layer, an active electrode silicon dioxide barrier layer, and an active electrode; The top inert electrode structure includes an inert electrode, an inert electrode silicon dioxide deposition layer, an inert electrode interconnection structure barrier layer, and an inert electrode interconnection structure metal filling layer; The metal lead-out terminal structure includes a metal lead-out terminal silicon dioxide deposition layer, a metal lead-out terminal silicon dioxide barrier layer, and a metal lead-out terminal metal filling layer.

[0015] In one embodiment, there is silicon nitride as a barrier layer between the bottom active electrode structure and the top inert electrode structure, and between the top inert electrode structure and the metal lead-out terminal structure; the electrolyte layer is located between the inert electrode and the active electrode.

[0016] A process integration method and structure of a novel memristive device provided by the present invention, including a conductive bridge type memristive device and an interconnection structure, wherein the size of the electrolyte layer of the conductive bridge type memristive device is limited by silicon nitride, the silicon nitride is etched using multi-angle ion beam etching, the electrolyte layer is located between the active electrode and the inert electrode and within the silicon nitride etching region, and by combining ion beam etching (IBE), atomic layer deposition (ALD) or magnetron sputtering process optimization methods, the preparation of a novel memristive device with high consistency is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the device structure after the preparation of the active electrode interconnection structure.

[0018] Figure 2 Schematic diagram of the device structure after the preparation of the third silicon nitride.

[0019] Figure 3 Schematic diagram of the device structure after the preparation of the inert electrode interconnection structure.

[0020] Figure 4It is a schematic structural diagram of a novel memristive device to be fabricated. Specific embodiments

[0021] The following further elaborates in detail on a process integration method for a novel memristive device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0022] As Figure 1 shown, the present invention is based on an n-type or p-type silicon substrate, which is ultrasonically cleaned in acetone and isopropyl alcohol for 10 minutes successively and washed twice with deionized water; a layer of silicon dioxide 1 with a thickness of 100 - 300 nm and a layer of silicon nitride 2 with a thickness of 50 - 300 nm are deposited by plasma-enhanced chemical vapor deposition (PECVD), and the process temperature is 350 °C.

[0023] A layer of active electrode interconnect structure silicon dioxide deposition layer 3 with a thickness of 200 - 500 nm is deposited by PECVD, and photolithography and silicon dioxide etching are carried out to form a first active electrode interconnect structure groove. A reactive electrode interconnect structure barrier layer 4 and a metal filling layer 5 are formed in the first active electrode interconnect structure groove by magnetron sputtering or electroplating process, where the material of the barrier layer is Ta and the material of the metal filling layer is Cu, and chemical mechanical polishing (CMP) is carried out. A layer of silicon nitride 6 with a thickness of 50 - 300 nm is deposited on the surface by PECVD.

[0024] As Figure 2 shown, a layer of active electrode silicon dioxide deposition layer 7 with a thickness of 200 - 500 nm is deposited on the surface of silicon nitride 6 by PECVD, and photolithography and silicon dioxide etching are carried out to form a second active electrode interconnect structure groove. A reactive electrode silicon dioxide barrier layer 8 and a reactive electrode 9 are formed in the second active electrode interconnect structure groove by magnetron sputtering or electroplating process, and chemical mechanical polishing is carried out, where the material of the reactive electrode 9 is any combination of copper, copper-silver alloy, and copper-titanium. A layer of silicon nitride 10 with a thickness of 50 - 300 nm is deposited on the surface by PECVD.

[0025] As Figure 3As shown, part of the silicon nitride 10 is removed by photolithography and etching to form a silicon nitride groove, and an electrolyte layer 11 is formed in the silicon nitride groove and on the outer edge of the silicon nitride groove by atomic layer deposition (ALD) or magnetron sputtering. The material of the electrolyte layer 11 is an oxide or a chalcogenide compound. Among them, the chalcogenide compound is formed by magnetron sputtering process, and the typical thickness is 20 - 100 nm; the oxide is formed by ALD process, and the typical thickness is 3 - 10 nm. By magnetron sputtering, an inert electrode is deposited on the surface of the electrolyte layer 11, including titanium nitride (TiN), tungsten (W), tantalum (Ta), etc., and an inert electrode 12 is formed by ion beam etching (IBE).

[0026] A layer of inert electrode silicon dioxide deposition layer 13 with a thickness of 400 - 1000 nm is deposited on the whole surface by PECVD, and an interconnect structure groove is formed by photolithography and silicon nitride etching. Among them, the interconnect structure groove above the second active electrode interconnect structure groove stops at the inert electrode 12, exposing the inert electrode 12; the remaining interconnect structure grooves stop at the metal filling layer 5, exposing the metal filling layer 5; an inert electrode interconnect structure barrier layer 14 and an inert electrode interconnect structure metal filling layer 15 are formed in the interconnect structure groove by magnetron sputtering or electroplating process, and CMP is carried out. At this time, the inert electrode interconnect structure barrier layer 14 in the interconnect structure groove above the second active electrode interconnect structure groove contacts the inert electrode 12, and the inert electrode interconnect structure barrier layer 14 in the remaining interconnect structure grooves contacts the metal filling layer 5.

[0027] As Figure 4 shown, a layer of silicon nitride 16 with a thickness of 50 - 300 nm and a layer of active electrode silicon dioxide deposition layer 17 with a thickness of 200 - 1000 nm are sequentially deposited on the whole surface by PECVD, and a metal lead-out terminal groove is formed by photolithography and silicon nitride etching. A metal lead-out terminal silicon dioxide barrier layer 18 and a metal lead-out terminal metal filling layer 19 are formed in the metal lead-out terminal groove by magnetron sputtering or electroplating process, and CMP is carried out to complete the preparation of the novel memristive device.

[0028] The structure of the novel memristive device prepared by the process integration method of the present invention is as Figure 4 shown, including a conductive bridge type memristive device and an interconnect structure; the interconnect structure includes an active electrode interconnect structure silicon dioxide deposition layer 3, an active electrode interconnect structure barrier layer 4, and an active electrode interconnect structure metal filling layer 5; the conductive bridge type memristive device is composed of a bottom active electrode structure, an electrolyte layer 11, a top inert electrode structure, and a metal lead-out terminal structure.

[0029] The bottom active electrode structure includes an active electrode silicon dioxide deposition layer 7, an active electrode silicon dioxide barrier layer 8, and an active electrode 9; the top inert electrode structure includes an inert electrode 12, an inert electrode silicon dioxide deposition layer 13, an inert electrode interconnection structure barrier layer 14, and an inert electrode interconnection structure metal filling layer 15; the metal lead-out terminal structure includes a metal lead-out terminal silicon dioxide deposition layer 17, a metal lead-out terminal silicon dioxide barrier layer 18, and a metal lead-out terminal metal filling layer 19.

[0030] There is silicon nitride as a barrier layer between the bottom active electrode structure and the top inert electrode structure, and between the top inert electrode structure and the metal lead-out terminal structure; the electrolyte layer 11 is located between the inert electrode 12 and the active electrode 9.

[0031] In summary, the present invention limits the size of the electrolyte layer of the conductive bridge type memristor device through silicon nitride, and combines ion beam etching IBE, atomic layer deposition ALD or magnetron sputtering process optimization methods to complete the preparation of a novel memristor device with high consistency.

[0032] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A process integration method for a novel memristive device, characterized in that, Including: Deposit silicon dioxide, first silicon nitride, and an active electrode interconnect structure silicon dioxide deposition layer on a silicon substrate in sequence, and form a first active electrode interconnect structure groove through photolithography and etching; Form an active electrode interconnect structure barrier layer and an active electrode interconnect structure metal filling layer in the first active electrode interconnect structure groove, perform chemical mechanical polishing, and then deposit second silicon nitride on the surface; Deposit an active electrode silicon dioxide deposition layer on the surface of the second silicon nitride, and form a second active electrode interconnect structure groove through photolithography and etching; Form an active electrode silicon dioxide barrier layer and an active electrode in the second active electrode interconnect structure groove, perform chemical mechanical polishing, and then deposit third silicon nitride on the surface; Remove a part of the third silicon nitride to form a silicon nitride groove and form an electrolyte layer inside, deposit an inert electrode on the surface of the electrolyte layer to form an inert electrode; deposit an inert electrode silicon dioxide deposition layer on the whole surface, and form an interconnect structure groove through photolithography and etching; Form an inert electrode interconnect structure barrier layer and an inert electrode interconnect structure metal filling layer in the interconnect structure groove, and perform chemical mechanical polishing; Deposit fourth silicon nitride and an active electrode silicon dioxide deposition layer on the whole surface in sequence, and form a metal lead-out terminal groove through photolithography and etching; Form a metal lead-out terminal silicon dioxide barrier layer and a metal lead-out terminal metal filling layer in the metal lead-out terminal groove, and perform chemical mechanical polishing to complete the preparation of the novel memristive device.

2. The process integration method of the novel memristive device according to claim 1, characterized in that, The material of the active electrode interconnect structure barrier layer is Ta, the material of the active electrode interconnect structure metal filling layer is Cu, and the material of the active electrode is any combination of copper, copper-silver alloy, and copper-titanium.

3. The process integration method of the novel memristive device according to claim 1, characterized in that, The material of the electrolyte layer is an oxide or a chalcogenide; among them, the chalcogenide is prepared by magnetron sputtering process with a thickness of 20 - 100 nm; the oxide is prepared by atomic layer deposition process with a thickness of 3 - 10 nm.

4. The process integration method of the novel memristive device according to claim 1, characterized in that The thickness of the active electrode interconnect structure silicon dioxide deposition layer is 200 - 500 nm, the thickness of the active electrode silicon dioxide deposition layer is 200 - 500 nm, the thickness of the inert electrode silicon dioxide deposition layer is 400 - 1000 nm, and the thickness of the active electrode silicon dioxide deposition layer is 200 - 1000 nm.

5. The process integration method of the novel memristive device according to claim 1, characterized in that, The thicknesses of the first silicon nitride, the second silicon nitride, the third silicon nitride, and the fourth silicon nitride are all 50 - 300 nm.

6. The process integration method of the novel memristive device according to claim 1, characterized in that, The inert electrode interconnect structure barrier layer in the interconnect structure groove above the second active electrode interconnect structure groove is in contact with the inert electrode, and the inert electrode interconnect structure barrier layer in the remaining interconnect structure grooves is in contact with the metal filling layer.

7. The process integration method of the novel memristive device according to claim 1, wherein, The third silicon nitride is etched by multi-angle ion beam etching, the gas configuration is Ar, the stage angle is 0 - 170°, the rotation speed is 5 - 20 rpm, and the ion energy is 50 - 1500 eV.

8. The process integration method of the novel memristive device according to claim 1, wherein The electrolyte layer and the inert electrode are etched by ion beam etching, the gas configuration is Ar, the stage angle is 0 - 170°, the rotation speed is 5 - 20 rpm, and the ion energy range is 50 - 1500 eV.

9. A novel memristive device structure, characterized in that, Prepared by the process integration method according to any one of claims 1-8, comprising a conductive-bridge type memristive device and an interconnect structure; wherein, The conductive-bridge type memristive device consists of a bottom active electrode structure, an electrolyte layer, a top inert electrode structure, and a metal lead-out terminal structure, The interconnect structure includes an active electrode interconnect structure silicon dioxide deposition layer, an active electrode interconnect structure barrier layer, and an active electrode interconnect structure metal filling layer; The bottom active electrode structure includes an active electrode silicon dioxide deposition layer, an active electrode silicon dioxide barrier layer, and an active electrode; The top inert electrode structure includes an inert electrode, an inert electrode silicon dioxide deposition layer, an inert electrode interconnect structure barrier layer, and an inert electrode interconnect structure metal filling layer; The metal lead-out terminal structure includes a metal lead-out terminal silicon dioxide deposition layer, a metal lead-out terminal silicon dioxide barrier layer, and a metal lead-out terminal metal filling layer.

10. The novel memristive device structure according to claim 9, characterized in that, There is silicon nitride as a barrier layer between the bottom active electrode structure and the top inert electrode structure, and between the top inert electrode structure and the metal lead-out terminal structure; the electrolyte layer is located between the inert electrode and the active electrode.

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