High-speed high-frequency beam loss diagnosis method and system

Abstract

The invention discloses a high-speed high-frequency beam loss diagnosis method and system. Algorithm development and implementation are carried out mainly based on a low-level digital signal processing board card, the board card collects high-frequency incident power, reflection power, cavity field power and beam signals in real time and stores the collected signals in a DDR3 memory in a round robin mode in real time, and pulse counting of set duration can be triggered after an interlocking fault occurs. After counting is completed, storage of the high-frequency beam loss diagnosis related signal data is stopped; an embedded system of the digital signal processing board card monitors the state of a DDR3 specified register in real time, high-frequency beam loss diagnosis data is obtained from the DDR3 and packaged after a high-frequency beam loss signal is monitored, and a data analysis system carries out operation processing on the packaged data information and draws a beam loss waveform; by analyzing the waveform characteristics of a certain time period before and after the fault beam loss moment, the fault reason of the high-frequency beam loss is diagnosed, and the diagnosis efficiency is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of accelerators, and particularly relates to a high-speed high-frequency beam loss diagnosis method and system, which are used for fault diagnosis of the high-frequency system in an accelerator device and can also be widely applied in related fields involving high-frequency signal data acquisition and waveform analysis. Background Art

[0002] In an accelerator device, high-frequency system faults are the most main and common types of faults and are also a key factor affecting the reliability of the accelerator. According to statistics, in two representative high-performance superconducting accelerators in China - the BEPCII storage ring and the Shanghai Synchrotron Radiation Facility storage ring, superconducting high-frequency cavity faults are both one of the main causes of accelerator faults.

[0003] The high-frequency safety interlock system has the function of displaying the high-frequency fault status, but it can only display the fault result and cannot determine the cause of the fault; the high-frequency database system online and real-time records the main status parameters of the high-frequency, providing a strong guarantee for high-frequency fault analysis. However, at the same time, since the fastest acquisition frequency of the database system is 10Hz, it belongs to a slow signal acquisition system, while the main signals of the high-frequency system, including the amplitude and phase of the cavity field signal, the amplitude and phase of the forward power and reflected power, the beam current signal, the internal signal of the low-level control system, etc., all belong to high-speed signals, and usually need to collect signals at a sampling rate of more than 100kHz, and analyze the waveforms for a period of time before and after the fault moment. According to the characteristics of the waveform curve, the real cause of the high-frequency fault can be accurately judged. Then we can quickly lock the fault source, solve the fault accurately and quickly, quickly restore the high-frequency system, and reduce the accelerator fault time. Therefore, a high-speed high-frequency fault system is crucial for analyzing high-frequency faults.

[0004] At present, the oscillograph recorder used in the high-frequency beam loss diagnosis system of Beijing Electron-Positron Collider BEPCII is the Yokogawa DL750 oscillograph recorder. This instrument includes 16 channels, with a maximum sampling rate of 10 MS / s and can achieve an instantaneous data storage of up to 1 GB. This oscillograph recorder can automatically print the captured data, issue alarms, save data, etc. when a fault state is detected. The Yokogawa DL750 oscillograph recorder is a standard commercial product, which has the advantages of high acquisition rate, large storage capacity, stable operation, etc., but there are also the following disadvantages: First, the high-frequency beam loss diagnosis system mainly analyzes RF high-frequency signals, while the input channels of the DL750 oscillograph recorder can only be DC voltage signals. Therefore, corresponding analog devices such as RF signal detectors and phase discriminators need to be configured before the oscillograph recorder input to convert the amplitude and phase of the RF signal into DC signals, increasing the complexity of the equipment; Second, the DL750 oscillograph recorder can automatically save the fault waveform after detecting the fault state, but it cannot send the data to the low-level database server, and manual operation is required to copy out the data for data analysis, which is not convenient for data processing and analysis, nor for sharing with other systems for data sharing and analysis; Finally, the price of the DL750 oscillograph recorder is relatively high, and the cost will be even higher if the configured detectors and phase discriminators are included. Summary of the Invention

[0005] In view of the importance of high-speed high-frequency beam loss fault diagnosis and the deficiencies of the existing BEPCII high-frequency beam loss diagnosis system, the purpose of the present invention is to provide a high-speed high-frequency beam loss diagnosis method and system. The present invention develops and implements algorithms based on a low-level digital signal processing board. The board card real-time collects high-frequency incident power Pf, reflected power Pr, cavity field power Pt', beam current signals, etc., and circularly stores the collected signals into the DDR3 memory in real time. When an interlock fault occurs, a pulse count for a set duration will be triggered, and when the counting is completed, the storage of the signal data related to high-frequency beam loss diagnosis will stop. The embedded system of the digital signal processing board runs a data acquisition program to monitor the status of the DDR3 specified address register in real time. When a high-frequency beam loss signal is detected, it will obtain the high-frequency beam loss diagnosis data from the DDR3, pack it, and store it as a data file. The database system reads the data storage file, performs arithmetic processing on the packed data information, and draws the beam loss waveform. By analyzing the waveform characteristics in a certain time period before and after the fault beam loss moment, the fault cause of the high-frequency beam loss can be diagnosed.

[0006] The technical solution of the present invention is as follows:

[0007] A high-speed high-frequency beam loss diagnosis method, the steps of which include:

[0008] 1. Acquisition of beam loss diagnosis data signals: The signals mainly acquired by the high-frequency beam loss fault diagnosis system include the incident power Pf of the high-frequency cavity, the reflected power Pr, the cavity field power Pt, the beam current signal Pb, etc. These RF high-frequency signals are first down-converted by the RF front-end board to obtain the corresponding intermediate-frequency signals, and the intermediate-frequency signals are sent to the ADC acquisition board for analog-to-digital conversion to obtain the corresponding digital signals. The ADC acquisition board is connected to the digital signal processing board through a bridge interface, and then the acquired digital signals are sent into the FPGA of the digital signal processing board for data acquisition and processing. The digital intermediate-frequency signals obtained by ADC data acquisition are processed by the Non-IQ sampling method to obtain the quadrature components in the I / Q domain of the corresponding signals.

[0009] 2. Beam loss diagnosis data packing module: The I / Q quadrature signals of the incident power Pf of the high-frequency cavity, the reflected power Pr, the cavity field power Pt, the beam current signal Pb, etc., which are acquired quickly in real time, are packed to generate a data packet signal trip_data_in, which will be sent to the peripheral DDR3 for data storage in a burst mode through the axi4-full-master module in the subsequent process. The number of bits of the acquired signal data is 32 bits. When the 4 signals described above are acquired, the data packet signal trip_data_in is a 16-byte signal.

[0010] 3. Beam Loss Diagnosis Data Parameter Processing Module: The setting parameters of beam loss diagnosis include the beam loss diagnosis clock frequency selection signal clk_sel, the beam loss diagnosis data storage depth signal Length_trip, the waveform trigger position signal Ratio_trip of beam loss diagnosis, etc. The clock input signal of beam loss diagnosis is clk_trigger. The internal clock selection module can flexibly output beam loss diagnosis acquisition clock signals clk_trip with various frequency sizes according to the set value clk_sel, meeting different setting requirements for the sampling rate of beam loss diagnosis stored data. The beam loss diagnosis data storage depth signal Length_trip represents the number of data packet signals trip_data_in stored each time a beam loss is triggered, and is used to calculate the storage address space size Length_trip_addr of storing the beam loss waveform in DDR3 and the total time length T_trip of the beam loss waveform, etc. For example, if the frequency of clk_trip is 1MHz, that is, the period is 1us, and the set Length_trip length is 2^16, then Length_trip_addr = 2^16 * 16 = 1MB, and the waveform duration T_trip = 2^16 * 1us = 65.536ms. The waveform trigger position signal Ratio_trip of beam loss diagnosis represents the ratio value of the time period length before the beam loss trigger moment to the duration of the entire beam loss diagnosis stored waveform curve. The beam loss trigger delay pulse number Count_trip_delay is obtained by subtracting the product of Ratio_trip and Length_trip from Length_trip. This signal will be used as the trigger delay number in the subsequent beam loss trigger enable signal generation module to obtain the trigger enable signal trip_enable.

[0011] 4. Beam loss trigger enable signal generation module: The input signals of this module include the beam loss manual trigger signal manual_trip and the cavity field power signal Pt. The high-frequency beam loss diagnostic method has two trigger modes, namely the manual mode and the automatic mode. The beam loss manual trigger signal manual_trip is usually a high-level signal, which is manually controlled through the upper-layer OPI. When it is set from high level to low level, it will trigger the manual trigger mode of high-frequency beam loss diagnosis and store the waveforms of the signals collected by the high-frequency beam loss diagnosis system during the time periods before and after the manual trigger moment. In the automatic mode, the beam loss diagnosis system needs to set the manual_trip signal to high level to work properly. When it is monitored that the amplitude of the cavity field power signal Pt is less than 70% of the theoretical value of the Pt power (this is a typical value, usually set in the range of 60% - 80%), it will make the beam loss trigger signal auto_en0 low level. The two signals manual_trip and auto_en0 are logically ANDed to obtain the beam loss enable signal auto_en1, and then the auto_en1 is delayed by the number of pulses of Count_trip_delay to obtain the beam loss trigger enable signal trip_enable.

[0012] 5. Beam loss diagnosis burst clock signal generation module: The input signals of this module include the beam loss diagnosis acquisition clock signal clk_trip and the beam loss trigger enable signal trip_enable. After the clk_trip signal and trip_enable are logically ANDed, the clk_axi_txn signal is obtained, and this signal serves as the burst clock of the subsequent axi4_full_master bus module. When trip_enable is high level, the clk_axi_txn signal is the clk_trip pulse signal, continuously bursting and transmitting data packets to the axi4_full_master bus module; when trip_enable is low level, the clk_axi_txn signal is also low level, stopping the burst transmission of data packets to the axi4_full_master bus module.

[0013] 6. Beam Loss Diagnosis Round Robin Address Generation Module: The beam loss diagnosis data storage depth signal Length_trip and the burst clock signal clk_axi_txn of the axi4_full_master bus module are the input signals of this module. When there is a rising edge of the clk_axi_txn signal, the beam loss round robin address axi_awaddr is incremented once. The increment step depends on the number of bytes of the data packet signal trip_data_in of the beam loss diagnosis system. When there are 4 channels of signals, it is 16 Byte. Length_trip determines the bit width of the beam loss round robin address axi_awaddr. When the beam loss round robin address axi_awaddr accumulates to 16 * Length_trip, it will automatically overflow to the 0 address and then start incrementing from the 0 address again after receiving a pulse. When trip_enable is at a low level, the burst clock clk_axi_txn signal will also become low level, and at this time the round robin address axi_awaddr will stop incrementing.

[0014] 7. Data Burst Transmission of the axi4-full-master Module: The data packet signal trip_data_in of the beam loss diagnosis system is a register type signal belonging to the Programmable Logic (PL) part of the FPGA. This data packet signal needs to be continuously stored in the DDR3 memory address segment at the Processing System (PS) end of the FPGA. The data communication between the PL part and the PS part of the FPGA is realized through data interaction of the axi4_full_master bus module. The PL part completes the logical algorithm function of beam loss diagnosis. The axi4_full_master bus module, as the master end, adopts the axi4-full bus. In burst mode, after receiving a pulse of clk_axi_txn each time, it bursts and writes the packed data packet signal trip_data_in into the corresponding address m_axi_awaddr in the storage space allocated to the axi4_full_master bus module in the DDR3 memory. The DDR3 memory allocates a maximum storage area of 1GB for the axi4_full_master bus module. It should be noted that in the 16-Byte interval starting from the starting address of this storage area, the data packet signal trip_data_in is not stored, but the beam loss trigger enable signal trip_enable, a specific packed data composed of special signals such as the beam loss round robin address axi_awaddr and the beam current turn count when trip_enable is at a low level, is stored. In other address spaces, it is normally used to store the data packet signal trip_data_in of the beam loss diagnosis system.

[0015] 8. Automatic storage of data packets at the beam loss moment in the beam loss diagnosis system: In the embedded system running on the digital signal processing board, an automatic acquisition algorithm for storing data packets in DDR3 is run. This algorithm real-time acquires the data packets stored in the 16-byte space starting from the starting address of the storage area of the beam loss diagnosis data packets in DDR3, and parses out the beam loss trigger enable signal trip_enable and the beam loss cycle address axi_awaddr at the beam loss moment. When it is monitored that the beam loss trigger enable signal trip_enable is at a low level, it indicates that a high-frequency fault has just occurred before. At this time, the data stored in the corresponding storage area of the beam loss diagnosis data packets in DDR3 is the waveform data of the sampling signal within the set time period before and after the beam loss moment. Then, a data packet file is created, and the data packets are started to be read from the corresponding storage space in DDR3 and stored into the newly created file. The data packets are read starting from m_axi_awaddr + 16 to read the stored data packets. When the maximum address of the corresponding area in DDR3 is read, it jumps to the offset address 16 to continue reading the data packets until the axi_awaddr address is read, and the data value at the last moment of the beam loss waveform is stored at this address. After the data reading is completed, it waits for the next trip_enable signal to become low level and repeats the previous actions. The newly created data packet file is transmitted to the specified beam loss diagnosis directory in the database system through the network.

[0016] 9. Data packet parsing module of the database system: The database system real-time monitors the data packet files in the beam loss diagnosis directory. When a new data packet file is found, the data is unpacked according to the packing method of the data packet, and the stored forward power signal Pf, reflected power signal Pr, cavity field power signal Pt, beam current signal Pb, etc. are parsed out; and the parsed data is plotted, and the cause of high-frequency beam loss can be analyzed according to the performance characteristics of the plotted curve.

[0017] Furthermore, the high-frequency signals to be collected by the beam loss diagnosis method can be increased or decreased.

[0018] Furthermore, the maximum sampling rate of the beam loss diagnosis method is 1 MHz.

[0019] Furthermore, the automatic storage method of data packets at the beam loss moment in the beam loss diagnosis system is implemented using a bash script under the linux system.

[0020] Furthermore, the parsing method of data packets in the database system is implemented using the python programming language.

[0021] A high-speed high-frequency beam loss diagnosis system, characterized by comprising a beam loss diagnosis data packing module, a beam loss diagnosis data parameter processing module, a beam loss trigger enabling signal generation module, a clock selection module, a beam loss diagnosis burst clock pulse signal generation module, a beam loss diagnosis polling address generation module, an axi4-full-master module, an automatic storage module, and an analysis module;

[0022] The beam loss diagnosis data packing module is used to collect the I / Q domain quadrature quantities of the incident power Pf, reflection power Pr, cavity field power Pt, and beam current signal Pb of the high-frequency system in real time and generate a data packet signal trip_data_in by data packing;

[0023] The beam loss diagnosis data parameter processing module is used to set the beam loss diagnosis clock frequency selection signal clk_sel, the beam loss diagnosis data storage depth signal Length_trip, the waveform trigger position signal Ratio_trip of the beam loss diagnosis, and the clock input signal clk_trigger of the beam loss diagnosis; calculate the beam loss trigger delay pulse number Count_trip_delay = Length_trip - Ratio_trip * Length_trip;

[0024] The clock selection module is used to output a beam loss diagnosis acquisition clock signal clk_trip according to the beam loss diagnosis clock frequency selection signal clk_sel, meeting different setting requirements for the sampling rate of the beam loss diagnosis stored data;

[0025] The beam loss trigger enabling signal generation module is used to store the waveform of the acquisition signal within a certain time period before and after the current moment when receiving the beam loss manual trigger signal manual_trip; if the amplitude of the cavity field power Pt at the current moment is less than the theoretical value of the Pt power, the beam loss trigger enabling signal auto_en0 is set to a low level; then the beam loss enabling signal auto_en1 is obtained by performing a logical AND operation on the manual_trip and auto_en0, and the beam loss trigger enabling signal trip_enable is obtained by delaying the beam loss enabling signal auto_en1 by the number of pulses of Count_trip_delay; the beam loss manual trigger signal manual_trip is a high-level signal;

[0026] The beam loss diagnosis burst clock pulse signal generation module is used to obtain the beam loss diagnosis acquisition clock signal clk_trip from the input clock pulse signal clk_trigger of the beam loss diagnosis through the clock selection module, and then store data packets at the frequency of the beam loss diagnosis acquisition clock signal clk_trip; perform a logical AND operation on the beam loss diagnosis acquisition clock signal clk_trip and the beam loss trigger enable signal trip_enable to obtain the clk_axi_txn signal, which serves as the burst clock of the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a high level, the clk_axi_txn signal is the clk_trip pulse signal, and continuously burst-transmits data packets to the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a low level, it indicates a high-frequency fault, and the clk_axi_txn signal is at a low level, stopping the burst transmission of data packets to the axi4_full_master bus module;

[0027] The beam loss diagnosis cyclic address generation module is used to increment the beam loss cyclic address axi_awaddr by one when there is a rising edge of the clk_axi_txn signal; when the beam loss trigger enable signal trip_enable is at a low level, the burst clock clk_axi_txn signal becomes low, and the cyclic address axi_awaddr will stop incrementing; when the beam loss cyclic address axi_awaddr increments to multiple Length_trip and automatically overflows to the 0 address, it will start incrementing again from the 0 address;

[0028] The axi4-full-master module is used to, after receiving each clk_axi_txn signal, burst-write the data packet signal trip_data_in into the corresponding address m_axi_awaddr in the storage space allocated to the axi4_full_master bus module in the DDR3 memory;

[0029] The automatic storage is used to create a data packet file when it is detected that the beam loss trigger enable signal trip_enable is at a low level; then read the data packet signal trip_data_in from the corresponding storage space in the DDR3 and store it into the created data packet file; after the data reading is completed, wait for the next beam loss trigger enable signal trip_enable to become low, and transmit the created data packet file to the beam loss diagnosis directory of the database system through the network;

[0030] The parsing module is used to monitor the data packet files in the beam loss diagnosis directory in real time. When a new data packet file is found, the data is unpacked according to the packet format of the data packet, and the stored forward power signal Pf, reflected power signal Pr, cavity field power signal Pt, and beam current signal Pb are parsed, and the parsed data is plotted.

[0031] Compared with the prior art, the present invention has the following advantages:

[0032] 1) Compared with the independent device characteristics of the oscilloscope recorder, the beam loss diagnosis data can be packaged online, and data interaction and data analysis between multiple systems can be realized.

[0033] 2) Compared with the oscilloscope recorder that can only perform function adjustment locally, the beam loss diagnosis method can realize remote online parameter adjustment and function control.

[0034] 3) The hardware architecture is simple. The beam loss diagnosis function can be realized by adopting a hardware architecture similar to that of the high-frequency low-level control system, and even the beam loss diagnosis function can be integrated into the low-level control system.

[0035] 4) The beam loss diagnosis method is realized based on a self-developed digital signal processing board, which not only improves the diagnosis efficiency, but also can greatly reduce the equipment cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a hardware framework diagram of the high-frequency beam loss diagnosis system.

[0037] Figure 2 It is a schematic diagram of the technical solution of the high-frequency beam loss diagnosis system.

[0038] Figure 3 It is a functional logic algorithm block diagram of the high-frequency beam loss diagnosis system.

[0039] Figure 4 It is a timing diagram of signals such as the burst clock of the high-frequency beam loss diagnosis system. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The present invention will be further described in detail below with reference to the drawings. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.

[0041] 1. Top-level design

[0042] The forward power signal Pf, reflection power signal Pr, cavity field power signal Pt, and beam current signal Pb collected by the high-speed high-frequency beam loss diagnosis method are all RF high-frequency signals. For signal acquisition, first, the radio frequency front-end board card is used for down-conversion to obtain the intermediate frequency IF signal, and then the intermediate frequency IF signal is converted into a digital signal through the ADC acquisition board card. The ADC acquisition board card accesses the digital signal processing board card through the FMC bridge interface. The data signal processing board card uses the Non-IQ algorithm to obtain the I / Q discrete data values of the sampled signal, and then realizes the packet storage of the power signal at the beam loss moment through the beam loss diagnosis function algorithm. The embedded linux system running on the digital signal processing board card obtains the data packets stored in the DDR3 memory and stores the files. The stored data files are sent to the database system. The database system unpacks the data files, parses the stored acquisition signals, draws the curve waveforms, and analyzes according to the curve waveform characteristics to complete the diagnosis of the beam loss cause.

[0043] The hardware framework diagram of the high-speed high-frequency beam loss diagnosis system is as Figure 1 shown. The system hardware mainly includes a digital signal processing board card, an ADC acquisition board card, a radio frequency front-end board card, a beam loss diagnosis system chassis, a database system, etc. The radio frequency front-end board card completes the function of down-converting the RF signal to the IF intermediate frequency signal, and distributes one path of the RF reference signal to the digital signal processing board card for generating the internal clock signal and ADC sampling clock signal of the board card. The ADC acquisition board completes the conversion of the intermediate frequency IF analog signal to a digital signal. The digital signal processing board card completes the acquisition of digital signals and the beam loss diagnosis algorithm function. The clock distribution unit generates the clock signals required for digital signal processing, such as the ADC sampling clock signal, according to the RF reference signal. The beam loss diagnosis control chassis provides power for the board cards and interfaces with external devices. The database system completes the parsing, data processing and analysis of the data packets at the beam loss moment, and draws the signal waveforms at the beam loss moment.

[0044] 2. Hardware Design

[0045] Altium designer is used for the design of the circuit schematic diagram and the drawing of the PCB printed board. The involved board cards include a digital signal processing board card, an ADC acquisition board card, a radio frequency front-end board card, etc. Among them, the FPGA of the digital signal processing board card uses the XC7Z100-2FFG900I chip of the ZYNQ-7000 series with an embedded arm system from Xilinx, and the peripheral is configured with a DDR3 DRAM memory. The ADC acquisition board card contains 6 ADC input channels, and the maximum sampling rate reaches 125MSPS. The radio frequency front-end board card contains 6 down-conversion channels to realize the down-conversion of the RF frequency to the IF intermediate frequency. The development of hardware devices is not the focus of this invention and will not be introduced in detail.

[0046] 3. Program Development

[0047] The technical solution for high-speed high-frequency beam loss diagnosis is as follows Figure 2 shown

[0048] The FPGA in the digital signal processing board uses the ZYNQ series chips with embedded systems. This chip includes a PL logic processing part and a PS processor system part. The communication between the PL part and the PS part realizes data interaction through the axi4_full_master module based on the AXI4-FULL bus protocol. The PS part of the FPGA is peripherally configured with a DDR3 memory and a network communication chip. The DDR3 is used to store beam loss diagnosis data packets, and the network chip realizes network data communication between the embedded system and the peripheral database system and the OPI client

[0049] The PL part of the FPGA is used to implement the main logic processing function of this beam loss diagnosis algorithm. Its detailed functional block diagram is as follows Figure 3 shown

[0050] The development of the beam loss diagnosis method is divided into the following parts according to functional modules

[0051] Collection of signals in the high-frequency beam loss diagnosis system: Collect 4 RF radio frequency signals, including the cavity field power signal Pt, the forward cavity power signal Pf, the cavity reflected power signal Pr, and the beam current signal Pb. The 4 RF high-frequency signals are down-converted to intermediate-frequency signals by the RF front-end board card, and then converted to digital signals by the ADC acquisition board card. The FPGA obtains the quadrature quantities of the 4 signals in the I / Q domain through the Non-IQ algorithm

[0052] Clock selection module of the high-frequency beam loss diagnosis system: The input signals of this module include the input clock pulse signal clk_trigger and the clock selection signal clk_sel. This module will output multiple clock signals clk_trip with different proportional relationships with clk_trigger according to the magnitude of clk_sel using the case statement, which is used to set the refresh frequency of the stored data in the beam loss diagnosis system

[0053] Packing of data signals in the high-frequency beam loss diagnosis system: For the 4 I / Q domain acquisition signals, each 32 bits, the signals are concatenated front and back to obtain a 128-bit packed data signal trip_data_in

[0054] Trigger events for high-frequency beam loss diagnosis: The input signals of this module include the manual trigger enable signal manual_trip and the I / Q quantities of the cavity field power signal Pt. The I / Q quantities of Pt are squared and added respectively to obtain the power amplitude value. When the power amplitude value is less than 70% of the cavity field power set value, it indicates that high-frequency beam loss has occurred, and the beam loss trigger signal auto_en0 is set to a low level. The beam loss enable signal auto_en1 is obtained by logically ANDing the two signals manual_trip and auto_en0, and this signal will be sent to the subsequent beam loss trigger delay module.

[0055] Trigger delay for high-frequency beam loss diagnosis: The input signals of this module include the beam loss diagnosis acquisition clock clk_trip, the beam loss enable signal auto_en1, and the beam loss trigger pulse delay number Count_trip_delay. This module delays the input auto_en1 by the number of pulses of Count_trip_delay to obtain the beam loss trigger enable signal trip_enable.

[0056] Burst clock for high-frequency beam loss diagnosis: The input signals of this module include the beam loss diagnosis acquisition clock clk_trip and the beam loss trigger enable signal trip_enable. The two signals are logically ANDed to obtain the burst clock clk_axi_txn, that is, there is a pulse signal in the burst clock only when trip_enable is at a high level, and trip_enable is the enable switch for burst transmission. The timing diagram of signals such as the burst clock clk_axi_txn of the high-frequency beam loss diagnosis system is as Figure 4 shown.

[0057] Processing of the set parameters of the high-frequency beam loss diagnosis system: The input signals of this module include the beam loss trigger position setting signal ratio_trip and the beam loss diagnosis storage depth setting signal Length_trip. Subtract the product of Ratio_trip and Length_trip from Length_trip to obtain the beam loss trigger pulse delay number Count_trip_delay, and this signal will be sent to the trigger delay module. Multiply length_trip by 16 to obtain the signal Length_trip_addr of the size of the beam loss diagnosis storage address space, and send this signal to the address cycling module. Address cycling of the high-frequency beam loss diagnosis system: The input signals of this module include two signals, the burst clock clk_axi_txn and the storage address space size Length_trip_addr. Each time a pulse of the burst clock clk_axi_txn is received, the cycling address axi_awaddr is incremented by 16 bytes. When the address accumulates to the maximum address, the address overflows and is automatically assigned 0, and the accumulation continues after the next burst pulse arrives. This cyclically accumulated address axi_awaddr is output as the cycling address to the data packet processing module for subsequent processing.

[0058] Data packet processing of the high-frequency beam loss diagnosis system: The input signals of this module include the beam loss trigger enable signal trip_enable, the cycling address signal axi_awaddr, the number of beam turns, the beam loss data packet trip_data_in, etc., and the output signals include the burst address m_axi_awaddr and the burst data packet m_axi_awdata. When trip_enable is 0, the data such as trip_enable, the cycling address signal axi_awaddr, and the number of beam turns at this moment are concatenated and packed into a 16-byte data, and this data is assigned to the output burst data packet signal m_axi_awdata, and the burst address signal m_axi_awaddr is assigned 0; when trip_enable is not 0, the beam loss data packet signal trip_data_in is assigned to the output burst data packet signal m_axi_awdata, and at the same time the cycling address signal axi_awaddr is assigned to the burst address signal m_axi_awaddr.

[0059] The axi4_full_master module for high-frequency beam loss diagnosis: The inputs of this module include the burst pulse clk_axi_txn, the burst address signal m_axi_awaddr, and the burst data packet m_axi_awdata. As the master side, based on the AXI4-FULL bus protocol, it transmits the data packet m_axi_awdata in the form of a burst at the frequency of the burst clock clk_axi_txn to the m_axi_awaddr address in the specified storage address range of the DDR3 on the PS side, realizing the storage transfer of data from the PL side to the DDR3 on the PS side.

[0060] Data acquisition at high-frequency beam loss moments: The embedded system of the digital signal processing board runs the DDR3 memory reading program in real time, reads the data in the corresponding DDR3 starting address in real time, and parses out the beam loss enable signal trip_enable and the cyclic address axi_awaddr at the beam loss moment. When the beam loss enable signal trip_enable is at a low level, it indicates that a high-frequency fault has occurred at this time. After diagnosing a high-frequency fault, an empty file is created with the high-frequency station name + the current moment as the file name, and the stored data in the DDR3 address range corresponding to the beam loss diagnosis is read and written into the newly created file. After the reading is completed, the newly created data file is automatically transmitted to the specified directory of the database system through the network.

[0061] Data parsing and analysis at high-frequency beam loss moments: The database system monitors the files in the beam loss diagnosis data directory in real time. When a new file is detected, it reads the new data packet file, parses the data packet, converts the I / Q quantity to the amplitude-phase quantity, thereby obtaining four signals such as the cavity field power signal, the cavity forward power signal, the cavity reflection signal, and the beam current signal. After reordering the data according to axi_awaddr, the signal waveform of the real beam loss period is obtained, and the waveform is plotted. According to the waveform characteristics of the amplitude-phase curves of the four signals before and after the beam loss moment, the cause of the high-frequency beam loss is diagnosed. If the beam current drops before the cavity field power signal, it indicates that the high-frequency fault is caused by the beam current. Otherwise, it is a fault of the high-frequency system itself. The cause of the high-frequency self-fault can be analyzed and diagnosed by analyzing the specific waveform characteristics of the forward power, reflection power, and cavity field power signals.

[0062] 4. System integration

[0063] After the hardware test and software development of the high-speed high-frequency beam loss diagnosis system are completed, the chassis design is required, and then it is integrated into a complete high-speed high-frequency beam loss diagnosis system. On the front panel of the chassis are mainly the power switch, LED status lights, RF signal input interfaces, etc., while on the rear panel are the reset switch, trigger interface, UART serial port, network port, and 220V power input, etc.

[0064] Although specific embodiments of the present invention are disclosed for illustrative purposes, which are intended to help understand the content of the present invention and implement it accordingly, those skilled in the art can understand that various substitutions, changes, and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the best embodiments, and the scope of protection required by the present invention shall be subject to the scope defined by the claims.

Claims

1. A high-speed high-frequency beam loss diagnosis method, the steps of which include: 1) Pack the I / Q domain quadrature quantities of the high-frequency cavity incident power Pf, reflected power Pr, cavity field power Pt, and beam signal Pb collected in real time by the high-frequency beam loss diagnosis system to generate a data packet signal trip_data_in; 2) Set the beam loss diagnosis clock frequency selection signal clk_sel, beam loss diagnosis data storage depth signal Length_trip, beam loss diagnosis waveform trigger position signal Ratio_trip, and beam loss diagnosis clock input signal clk_trigger; the clock selection module of the high-frequency beam loss diagnosis system outputs a beam loss diagnosis acquisition clock signal clk_trip according to the beam loss diagnosis clock frequency selection signal clk_sel to meet different setting requirements for the sampling rate of the beam loss diagnosis stored data; calculate the beam loss trigger delay pulse number Count_trip_delay = Length_trip - Ratio_trip * Length_trip; 3) When the high-frequency beam loss diagnosis system receives the beam loss manual trigger signal manual_trip, store the acquisition signal waveforms within a certain time period before and after the current moment; if the amplitude of the cavity field power Pt at the current moment is less than a certain proportion of the Pt power theoretical value, trigger the beam loss enable signal auto_en0 to be set to a low level; then perform a logical AND operation on the manual_trip and auto_en0 to obtain the beam loss enable signal auto_en1, and delay the beam loss enable signal auto_en1 by the number of pulses of Count_trip_delay to obtain the beam loss trigger enable signal trip_enable; the beam loss manual trigger signal manual_trip is a high-level signal; 4) Obtain the beam loss diagnosis acquisition clock signal clk_trip from the input clock pulse signal clk_trigger of the beam loss diagnosis through the clock selection module, and then store the data packet at the frequency of the beam loss diagnosis acquisition clock signal clk_trip; perform a logical AND operation on the beam loss diagnosis acquisition clock signal clk_trip and the beam loss trigger enable signal trip_enable to obtain the clk_axi_txn signal, which is used as the burst clock of the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a high level, the clk_axi_txn signal is the clk_trip pulse signal, and continuously burst-transmit data packets to the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a low level, it indicates that a high-frequency fault has occurred, and the clk_axi_txn signal is at a low level, stopping the burst transmission of data packets to the axi4_full_master bus module; 5) When there is a rising edge of the clk_axi_txn signal, the round-robin address axi_awaddr of the beam loss wheel increases by one; when the beam loss trigger enable signal trip_enable is at a low level, the burst clock clk_axi_txn signal becomes low, and the round-robin address axi_awaddr will stop increasing; among them, when the round-robin address axi_awaddr of the beam loss accumulates to multiple Length_trip, it automatically overflows to the 0 address and then starts accumulating from the 0 address again; 6) After the axi4_full_master bus module receives each clk_axi_txn signal, it bursts and writes the data packet signal trip_data_in into the corresponding address m_axi_awaddr of the storage space allocated to the axi4_full_master bus module in the DDR3 memory; 7) When it is detected that the beam loss trigger enable signal trip_enable is at a low level, a data packet file is created; then the data packet signal trip_data_in is read from the corresponding storage space in the DDR3 and stored in the created data packet file; after the data reading is completed, wait for the next beam loss trigger enable signal trip_enable to become low, and the created data packet file is transmitted to the beam loss diagnosis directory of the database system through the network; 8) The database system monitors the data packet files in the beam loss diagnosis directory in real time. When a new data packet file is found, the data is unpacked according to the packing method of the data packet, and the stored forward power signal Pf, reflection power signal Pr, cavity field power signal Pt, and beam current signal Pb are parsed, and the parsed data is plotted.

2. The method according to claim 1, wherein The method for the high-frequency beam loss diagnosis system to obtain the I / Q domain quadrature quantities of the high-frequency cavity incident power Pf, reflection power Pr, cavity field power Pt, and beam current signal Pb is as follows: The high-frequency beam loss fault diagnosis system real-time collects the high-frequency cavity incident power Pf, reflection power Pr, cavity field power Pt, and beam current signal Pb and down-converts them through the RF front-end board to obtain the corresponding intermediate-frequency signals. The intermediate-frequency signals are subjected to analog-to-digital conversion through the ADC acquisition board to obtain the corresponding digital signals and input them into the FPGA of the digital signal processing board to obtain the I / Q domain quadrature quantities of the corresponding signals through the Non-IQ sampling method.

3. The method according to claim 2, wherein The DDR3 memory allocates a storage area for the axi4_full_master bus module. The starting address of the storage area stores the beam loss trigger enable signal trip_enable, and other address spaces are used to store the data packet signal trip_data_in of the beam loss diagnosis system.

4. The method according to claim 1 or 2 or 3, characterized in that, The step size of each increase of the round-robin address axi_awaddr of the beam loss depends on the size of the number of bytes of the data packet signal trip_data_in.

5. The method according to claim 1 or 2 or 3, characterized in that, The beam loss diagnosis data storage depth signal Length_trip is the number of data packets stored each time a beam loss is triggered, and is used to calculate the storage address space size Length_trip_addr for storing the beam loss waveform in DDR3 and the total time length T_trip of the beam loss waveform; the waveform trigger position signal Ratio_trip of the beam loss diagnosis is the ratio of the time period length before the beam loss trigger moment to the time length of the entire beam loss diagnosis storage waveform curve.

6. The method according to claim 1 or 2 or 3, characterized in that, Determine the cause of high-frequency beam loss based on the performance characteristics of the drawn curve; the value range of the theoretical Pt power ratio is 60% to 80%.

7. A high-speed high-frequency beam loss diagnosis system, characterized in that It includes a beam loss diagnosis data packing module, a beam loss diagnosis data parameter processing module, a beam loss trigger enable signal generation module, a clock selection module, a beam loss diagnosis burst clock pulse signal generation module, a beam loss diagnosis cyclic address generation module, an axi4-full-master module, an automatic storage module, and an analysis module; The beam loss diagnosis data packing module is used to collect the I / Q domain quadrature quantities of the incident power Pf, reflected power Pr, cavity field power Pt, and beam current signal Pb of the high-frequency cavity of the high-frequency system in real time and generate a data packet signal trip_data_in after data packing; The beam loss diagnosis data parameter processing module is used to set the beam loss diagnosis clock frequency selection signal clk_sel, the beam loss diagnosis data storage depth signal Length_trip, the waveform trigger position signal Ratio_trip of the beam loss diagnosis, and the clock input signal clk_trigger of the beam loss diagnosis; calculate the number of beam loss trigger delay pulses Count_trip_delay = Length_trip - Ratio_trip * Length_trip; The clock selection module is used to output a beam loss diagnosis acquisition clock signal clk_trip according to the beam loss diagnosis clock frequency selection signal clk_sel to meet different setting requirements for the sampling rate of the beam loss diagnosis stored data; The beam loss trigger enable signal generation module is used to store the acquisition signal waveforms within a certain time period before and after the current moment when receiving the beam loss manual trigger signal manual_trip; if the amplitude of the cavity field power Pt at the current moment is less than the theoretical Pt power value, the beam loss trigger enable signal auto_en0 is set to a low level; then the beam loss enable signal auto_en1 is obtained by performing a logical AND operation on the manual_trip and auto_en0, and the beam loss trigger enable signal trip_enable is obtained by delaying the beam loss enable signal auto_en1 by the number of pulses of Count_trip_delay; the beam loss manual trigger signal manual_trip is a high-level signal; The beam loss diagnosis burst clock pulse signal generation module is used to obtain the beam loss diagnosis acquisition clock signal clk_trip from the input clock pulse signal clk_trigger of the beam loss diagnosis through the clock selection module, and then store data packets at the frequency of the beam loss diagnosis acquisition clock signal clk_trip; perform a logical AND operation on the beam loss diagnosis acquisition clock signal clk_trip and the beam loss trigger enable signal trip_enable to obtain the clk_axi_txn signal, which serves as the burst clock of the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a high level, the clk_axi_txn signal is the clk_trip pulse signal, and continuously burst-transmits data packets to the axi4_full_master bus module; when the beam loss trigger enable signal trip_enable is at a low level, it indicates a high-frequency fault, and the clk_axi_txn signal is at a low level, stopping the burst transmission of data packets to the axi4_full_master bus module; The beam loss diagnosis cyclic address generation module is used to increment the beam loss cyclic address axi_awaddr once when there is a rising edge of the clk_axi_txn signal; when the beam loss trigger enable signal trip_enable is at a low level, the burst clock clk_axi_txn signal becomes low level, and the cyclic address axi_awaddr will stop incrementing; when the beam loss cyclic address axi_awaddr increments to multiple Length_trip and automatically overflows to the 0 address, and then starts incrementing again from the 0 address; The axi4-full-master module is used to, after receiving each clk_axi_txn signal, burst-write the data packet signal trip_data_in into the corresponding address m_axi_awaddr of the storage space allocated to the axi4_full_master bus module in the DDR3 memory; The automatic storage is used to create a data packet file when it is detected that the beam loss trigger enable signal trip_enable is at a low level; then read the data packet signal trip_data_in from the corresponding storage space in the DDR3 and store it into the created data packet file; after the data reading is completed, wait for the next time the beam loss trigger enable signal trip_enable becomes low level, and transmit the created data packet file to the beam loss diagnosis directory of the database system through the network; The parsing module is used to continuously monitor the data packet files in the beam loss diagnosis directory. When a new data packet file is found, it unpacks the data according to the data packet packaging method, parses out the forward power signal Pf, reflection power signal Pr, cavity field power signal Pt, and beam current signal Pb stored, and plots curves for the parsed data.

8. The system according to claim 7, wherein The DDR3 memory allocates a storage range for the axi4_full_master bus module. The starting address of the storage range stores the beam loss trigger enable signal trip_enable, and other address spaces are used to store the data packet signal trip_data_in of the beam loss diagnosis system.

9. The system according to claim 7, wherein The accumulation step size of the beam loss polling address axi_awaddr accumulated each time depends on the size of the number of bytes of the data packet signal trip_data_in.

10. The system according to claim 7, wherein The beam loss diagnosis data storage depth signal Length_trip is the number of data packets stored each time the beam loss is triggered, and is used to calculate the storage address space size Length_trip_addr of the beam loss waveform stored in the DDR3 and the total time length T_trip of the beam loss waveform; the waveform trigger position signal Ratio_trip of the beam loss diagnosis is the ratio value of the length of the time period before the beam loss trigger moment to the length of the entire beam loss diagnosis storage waveform curve.

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