RISC-V-based processor and electronic device

Abstract

The application provides a RISC-V-based processor and electronic equipment, a pre-decoding module sends N groups of obtained pre-decoding information and a second target instruction to a second register; a decoding module reads information from the second register, sends corresponding source data to a third register according to a source register address in the pre-decoding information, decodes the read second target instruction to obtain N groups of decoding information, and sends the N groups of decoding information to the third register; and a back-end module executes corresponding microcode instructions according to the N groups of decoding information, source data and the latest writing in the third register. The first target instruction includes at least two microcode instructions, so that multiple microcode instructions can be executed in each clock cycle, and the operation performance of the processor can be improved. Through the pre-decoding information, the source data is written into the third register in advance, so that the corresponding source data can be directly called when the microcode instruction is executed, and the running efficiency of the processor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chips, in particular to a RISC-V-based processor and electronic equipment. BACKGROUND

[0002] As a new computing architecture, RISC-V is gradually becoming an important driving force for the development of AI computing power. RISC-V provides great freedom for chip designers due to its open and flexible characteristics, and can customize AI accelerators according to specific needs. Its instruction set is simple and highly extensible, and designers can add custom instruction set extensions to improve the performance and efficiency of AI computing. Most RISC-V processors currently used for AI control are single-issue in-order structures. Although the RISC-V processor with a single-issue in-order structure can meet the requirements of simple program control, in AI applications, the structure has lower performance, and the IPC (instructions per cycle) is usually not greater than 1, which becomes a performance bottleneck in AI applications. SUMMARY

[0003] The purpose of the present application is to provide a RISC-V-based processor and electronic equipment to improve the above problems.

[0004] To achieve the above purpose, the technical scheme adopted by the embodiments of the present application is as follows:

[0005] In a first aspect, the embodiments of the present application provide a RISC-V-based processor, comprising:

[0006] The instruction fetching module is configured to perform instruction extraction according to the instruction fetching start address of the current clock cycle in the sequential instruction fetching state, and write the obtained first target instruction start address to the first register; the first target instruction includes at least two microcode instructions.

[0007] The pre-decoding module is configured to perform pre-decoding processing on the second target instruction, and send the obtained N groups of pre-decoding information and the second target instruction to the second register.

[0008] If the current clock cycle is a safe cycle, the second target instruction is the first target instruction that is recently written and valid in the first register, if the current clock cycle is a non-safe cycle, the second target instruction is the first target instruction that is read from the first register in the last safe cycle, and the jth pre-decoding information includes the destination register address and the source register address corresponding to the jth microcode instruction.

[0009] The decoding module is configured to read the second target instruction and the N sets of pre-decoding information written most recently from the second register, determine whether the current clock cycle is a safe cycle based on the second target instruction and the N sets of pre-decoding information, and feed back the determination result of the safe cycle to the pre-decoding module; send the corresponding source data to the third register according to the source register address in the pre-decoding information, decode the second target instruction read to obtain the N sets of decoding information, and send the N sets of decoding information to the third register;

[0010] The jth decoding information includes an instruction type corresponding to the jth microcode instruction, a destination register address, an operation action, a number of execution cycles, and an immediate number.

[0011] The backend module is configured to execute the corresponding microcode instruction according to the N sets of decoding information, the source data written most recently in the third register.

[0012] Optionally, the instruction fetching module includes a first selector, a program counter, an adder, an instruction memory, and an identification unit.

[0013] The program counter is configured to send a fetching start address of a current clock cycle to the instruction memory and the first register.

[0014] The instruction memory is configured to extract an instruction according to the fetching start address of the current clock cycle in a sequential instruction fetching state, and write the first target instruction extracted into the first register.

[0015] The identification unit is configured to determine whether the first target instruction is a branch instruction; if not, send a sequential execution signal to the first selector; if yes, send a branch execution signal to the first selector.

[0016] The adder is configured to determine a first address according to the fetching start address of the current clock cycle and a preset byte number, and send the first address to the first selector.

[0017] The first selector is further configured to receive a second address fed back by the backend module, the second address being an execution result of the branch instruction.

[0018] The first selector is further configured to send the first address to the program counter when receiving the sequential execution signal, and send the second address to the program counter when receiving the branch execution signal.

[0019] The program counter is further configured to store the address sent by the first selector in the current clock cycle as a fetching start address of a next clock cycle.

[0020] Optionally, the pre-decoding module includes a transmitting queue, a second selector, and N pre-decoding units, where N represents a total number of microcode instructions in the first target instruction.

[0021] In a case that the first type of control signal is obtained in the current clock cycle, the transmitting queue and the second selector are configured to read the first target instruction which is written in the first register and valid last time, wherein the first type of control signal indicates that the current clock cycle is a safe cycle;

[0022] In a case that the second type of control signal is obtained in the current clock cycle, the transmitting queue and the second selector stop reading the instruction from the first register; the second selector is configured to read the first target instruction which is written in the transmitting queue last time; wherein the second type of control signal indicates that the current clock cycle is a non-safe cycle;

[0023] The second selector is configured to send the instruction read in the current clock cycle as the second target instruction to the second register and the N pre-decoding units;

[0024] The jth pre-decoding unit is configured to pre-decode the jth microcode instruction received in the current clock cycle to obtain jth pre-decoding information corresponding to the jth microcode instruction, and send the jth pre-decoding information to the second register.

[0025] Optionally, the decoding module comprises N decoding units, a microcode scoreboard, a register file and a register hazard checking unit;

[0026] The jth decoding unit is configured to read the jth microcode instruction in the second target instruction written in the second register last time in the current clock cycle, and decode to obtain jth decoding information, and send the jth decoding information to the third register and the microcode scoreboard;

[0027] The microcode scoreboard is configured to store hazard-related information, wherein the hazard-related information comprises instruction type corresponding to the microcode instruction, destination register address and execution cycle number;

[0028] The register hazard checking unit is configured to read N sets of pre-decoding information written in the second register last time in the current clock cycle, and query in the microcode scoreboard based on the N sets of pre-decoding information to determine whether there is data hazard and structural hazard;

[0029] If there is data hazard or structural hazard, the register hazard checking unit is configured to send the second type of control signal to the pre-decoding module; if there is no data hazard and structural hazard, the register hazard checking unit is configured to send the first type of control signal to the pre-decoding module;

[0030] The register file is configured to read N sets of pre-decoding information written in the second register last time in the current clock cycle, and send corresponding source data to the third register according to the source register address in the pre-decoding information.

[0031] Optionally, the first register is configured to send the fetched instruction start address received in the last clock cycle to the second register; the second register is configured to send the fetched instruction start address received in the last clock cycle to the third register; the third register is configured to send the source data corresponding to the first type of decoding unit and the first type of decoding information generated by the first type of decoding unit to the fourth register; the first type of decoding information is the decoding information generated by the first type of decoding unit, and the first type of decoding unit is a decoding unit having the capability of processing a store instruction or a load instruction.

[0032] The back-end module comprises an execution module, a fourth register, a memory access module, a fifth register, and a write-back module.

[0033] The execution module is configured to perform a corresponding operation according to the fetched instruction start address written by the third register in the last clock cycle, the N sets of decoding information, and the source data, send the obtained operation result and the corresponding destination register address to the fourth register, and send the obtained second address to the fetch instruction module.

[0034] The fourth register is configured to send the operation result received in the last clock cycle and the corresponding destination register address to the fifth register.

[0035] The memory access module is configured to read the first type of decoding information most recently written in the fourth register, store the source data corresponding to the first type of decoding information to the corresponding address when the operation action in the first type of decoding information is a storage action, obtain the load data from the corresponding address when the operation action in the first type of decoding information is a load action, and send the load data and the corresponding destination register address to the fifth register.

[0036] The write-back module is configured to read the operation result and the load data most recently written in the fifth register in the current clock cycle, and write the operation result and the load data back to the register file according to the corresponding destination register address.

[0037] Optionally, the execution module comprises a branch execution unit and N arithmetic logic units.

[0038] The branch execution unit is configured to read the fetched instruction start address written by the third register in the last clock cycle, the second type of decoding information, and the source data, wherein the second type of decoding information is the decoding information generated by the second type of decoding unit, and the second type of decoding unit is a decoding unit having the capability of processing a system instruction.

[0039] The branch execution unit is configured to generate a second address according to the read information, and feed back the second address to the fetch instruction module.

[0040] The jth arithmetic logic unit is configured to read the jth decoding information and the source data written in the third register in the last clock cycle, and perform a corresponding logical operation based on the two to obtain a jth operation result, and send the jth operation result and a corresponding destination register address of the jth operation result to the fourth register.

[0041] Optionally, the branch execution unit is further configured to feed back a branch instruction completion signal to the instruction fetching module after determining that the branch instruction is executed, so that the instruction fetching module returns from the branch instruction fetching state to the sequential instruction fetching state.

[0042] Optionally, the memory access module comprises a data memory.

[0043] The data memory is configured to read the first type of decoding information written in the fourth register most recently, store the source data corresponding to the first type of decoding information into a corresponding address in the data memory when the operation action in the first type of decoding information is a storage action, obtain load data from the corresponding address in the data memory when the operation action in the first type of decoding information is a load action, and send the load data and a corresponding destination register address to the fifth register.

[0044] In a second aspect, an electronic device is provided, comprising the RISC-V-based processor described above.

[0045] Compared with the prior art, the RISC-V-based processor and the electronic device provided by the embodiments of the present application have the following advantages: the instruction fetching module fetches instructions according to the instruction fetching start address of the current clock cycle in the sequential instruction fetching state, and writes the obtained first target instruction start address into the first register; the first target instruction comprises at least two microcode instructions; the pre-decoding module performs pre-decoding processing on the second target instruction, and sends the obtained N groups of pre-decoding information and the second target instruction to the second register; the decoding module reads the second target instruction and the N groups of pre-decoding information written in the second register most recently, determines whether the current clock cycle is a safe period based on the two, and feeds back the determination result of the safe period to the pre-decoding module; the corresponding source data is sent to the third register according to the source register address in the pre-decoding information, the read second target instruction is decoded to obtain N groups of decoding information, and the N groups of decoding information are sent to the third register; and the backend module executes the corresponding microcode instruction according to the N groups of decoding information, the source data written in the third register most recently. The first target instruction comprises at least two microcode instructions, so that multiple microcode instructions can be executed in each clock cycle, and the operation performance of the processor can be improved. Through the pre-decoding information, the source data is written into the third register in advance, which facilitates the direct calling of the corresponding source data when the microcode instruction is executed, and improves the running efficiency of the processor.

[0046] In order to make the above objectives, characteristics and advantages of the present application more apparent, more comprehensible, the following preferred embodiments are specifically described in detail below, and the accompanying drawings are referred to. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0048] Figure 1 The structure schematic diagram of the processor based on RISC-V provided by the embodiments of the present application is shown.

[0049] Figure 2 The structure schematic diagram of the instruction fetching module provided by the embodiments of the present application is shown.

[0050] Figure 3 The structure schematic diagram of the pre-decoding module provided by the embodiments of the present application is shown.

[0051] Figure 4 The structure schematic diagram of the decoding module provided by the embodiments of the present application is shown.

[0052] Figure 5 The structure schematic diagram of the execution module provided by the embodiments of the present application is shown.

[0053] Figure 6 The connection schematic diagram between the write-back module and the register file provided by the embodiments of the present application is shown.

[0054] In the figure: 10-instruction fetching module; 71-1st register; 20-pre-decoding module; 72-2nd register; 30-decoding module; 73-3rd register; 40-execution module; 74-4th register; 50-memory accessing module; 75-5th register; 60-write-back module. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the embodiments of the present application more apparent, the following will combine the drawings in the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0056] The following detailed description of embodiments of the application in the drawings provided is not intended to limit the scope of the application claimed, but merely represents selected embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the application.

[0057] It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0058] It should be noted that the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0059] In the description of the application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "provided", "connected" should be understood broadly, for example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0060] Some embodiments of the application will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments can be combined with each other without conflict.

[0061] Reference should be made to Figure 1 , Figure 1 The structure schematic diagram of the RISC-V-based processor provided for the embodiments of the application is shown. The processor comprises a fetch instruction module 10, a first register 71, a pre-decoding module 20, a second register 72, a decoding module 30, a third register 73 and a back-end module connected in sequence. Optionally, the back-end module comprises an execution module 40, a fourth register 74, a memory access module 50, a fifth register 75 and a write-back module 60. Figure 1Not shown is that the execution module 40 is also connected with the instruction fetch module 10, and the write back module 60 is also connected with the decode module 30. The processor running conditions are described as follows.

[0062] The instruction fetch module 10 is used to fetch instructions according to the instruction fetch start address of the current clock cycle in the sequential instruction fetch state, and write the obtained first target instruction start address into the first register 71.

[0063] The first target instruction includes at least two microcode instructions. Thus, multiple microcode instructions can be executed in each clock cycle, which can improve the operation performance of the processor. Moreover, there is no dependency between any two microcode instructions in the first target instruction, which reduces the hardware overhead of the processor.

[0064] When the first target instruction written into the first register 71 by the instruction fetch module 10 is a branch instruction, the instruction fetch module 10 is in the branch instruction fetch state after the writing is completed and before a branch instruction completion signal is received; otherwise, the instruction fetch module 10 is in the sequential instruction fetch state. It should be noted that when the instruction fetch module 10 is in the branch instruction fetch state, it will not write a valid first target instruction into the first register 71.

[0065] The pre-decode module 20 is used to perform pre-decode processing on the second target instruction, and send the obtained N groups of pre-decode information and the second target instruction to the second register 72.

[0066] If the current clock cycle is a safe cycle, the second target instruction is the latest written and valid first target instruction in the first register 71, and if the current clock cycle is a non-safe cycle, the second target instruction is the first target instruction read from the first register 71 in the latest safe cycle, the jth pre-decode information is the pre-decode information corresponding to the jth microcode instruction, 1≤j≤N, N represents the total number of microcode instructions in the first target instruction, and the jth pre-decode information includes the destination register address and the source register address corresponding to the jth microcode instruction. The non-safe cycle indicates that one or more microcodes have not been executed, so the execution needs to be continued to wait, at this time, the instruction cannot be covered by a new instruction.

[0067] It should be understood that the pre-decode module 20 can read the first target instruction stored in the first register 71 and cache it.

[0068] The safe cycle indicates that there is no data hazard and structural hazard for the second target instruction written into the second register in the last clock cycle, and the non-safe cycle indicates that there is a data hazard or a structural hazard for the second target instruction written into the second register in the last clock cycle. If the current clock cycle is a safe cycle, the second target instruction written into the second register in the last clock cycle can be executed.

[0069] The decoding module 30 is configured to read the second target instruction and the N sets of pre-decoding information written in the second register 72, determine whether the current clock cycle is a safe cycle based on the second target instruction and the N sets of pre-decoding information, and feed back the determination result of the safe cycle to the pre-decoding module 20; send the corresponding source data to the third register 73 according to the source register address in the pre-decoding information, decode the second target instruction read to obtain the N sets of decoding information, and send the N sets of decoding information to the third register 73.

[0070] The jth decoding information includes the instruction type corresponding to the jth microcode instruction, the destination register address, the operation action (addition, subtraction, multiplication, division, etc.), the number of execution cycles (the number of clock cycles required for the microcode instruction to be executed), and the immediate number.

[0071] It should be understood that, through pre-decoding, the source register address is obtained in advance and output to the second register, and then the register file can be accessed according to the pre-decoding information while decoding, the decoding information and the source data are written into the third register synchronously, so that the corresponding source data can be directly called when the microcode instruction is executed, and the running efficiency of the processor is improved.

[0072] The backend module is configured to execute the corresponding microcode instruction according to the N sets of decoding information, the source data written in the third register 73 in the last time.

[0073] In the RISC-V-based processor provided in the embodiment of the present application, the first target instruction includes at least two microcode instructions, so that a plurality of microcode instructions can be executed in each clock cycle, and the operation performance of the processor can be improved. Through pre-decoding, the source register address is obtained in advance and output to the second register, and then the register file can be accessed according to the pre-decoding information while decoding, the decoding information and the source data are written into the third register synchronously, so that the corresponding source data can be directly called when the microcode instruction is executed, and the running efficiency of the processor is improved.

[0074] On the basis of Figure 1 , the embodiment of the present application further provides an optional implementation of the structure of the instruction fetching module, please refer to Figure 2 , Figure 2 The structure diagram of the instruction fetching module provided in the embodiment of the present application.

[0075] The instruction fetching module 10 includes a first selector S1, a program counter, an adder, an instruction memory, and an identification unit.

[0076] The first input end of the first selector S1 is connected to the output end of the adder, the second input end of the first selector S1 is connected to the backend module, the output end of the first selector S1 is connected to the program counter, and the control end of the first selector S1 is connected to the output end of the identification unit.

[0077] The output end of the program counter is connected with the adder, the instruction memory and the first register 71 respectively; the output end of the instruction memory is connected with the first register 71 and the identification unit respectively.

[0078] In an alternative embodiment, the instruction memory (and / or the identification unit) is also connected with the back-end module (the branch execution unit in the execution module 40) and can receive a branch instruction completion signal (F0).

[0079] The program counter is used to send the instruction fetching start address of the current clock cycle to the instruction memory and the first register 71.

[0080] The instruction memory is used to extract instructions according to the instruction fetching start address of the current clock cycle in the sequential instruction fetching state, and write the extracted first target instruction into the first register 71.

[0081] When the instruction memory is in the branch instruction fetching state, it does not write a valid first target instruction into the first register 71.

[0082] The identification unit is used to determine whether the first target instruction is a branch instruction; if not, it sends a sequential execution signal to the first selector S1; if yes, it sends a branch execution signal to the first selector S1.

[0083] The branch instruction is an instruction that causes a jump in the program execution process and belongs to control hazards.

[0084] The adder is used to determine the first address according to the instruction fetching start address of the current clock cycle and a preset byte number, and send the first address to the first selector S1.

[0085] The preset byte number can be but is not limited to 16 bytes, and the preset byte number is related to the total number of microcode instructions in the first target instruction. The adder adds the instruction fetching start address of the current clock cycle and the preset byte number to determine the first address.

[0086] The first selector S1 is also used to receive a second address fed back by the back-end module (the execution module 40 in the following text), and the second address is the execution result of the branch instruction (i.e. the program jump address after the execution of the branch instruction is completed).

[0087] The first selector S1 is also used to send the first address to the program counter when the sequential execution signal is received, and send the second address to the program counter when the branch execution signal is received.

[0088] The program counter is also used to store the address sent by the first selector S1 in the current clock cycle and use it as the instruction fetching start address of the next clock cycle.

[0089] In Figure 1 addition, the pre-decoding module provided by the embodiment of the present application also provides an optional implementation, please refer to Figure 3 , Figure 3 The structure diagram of the pre-decoding module provided by the embodiment of the present application.

[0090] The pre-decoding module 20 includes a transmit queue, a second selector S2 and N pre-decoding units (also called microcode slot pre-decoding units).

[0091] The input end of the transmit queue and the first input end of the second selector S2 are connected to the first register 71, the second input end of the second selector S2 is connected to the output end of the transmit queue, the control end of the transmit queue and the control end of the second selector S2 are connected to the decoding module 30 (the register hazard checking unit), the output end of the second selector S2 is connected to the second register and the input end of the N pre-decoding units, and the output end of the pre-decoding unit is connected to the second register 72.

[0092] In the case that the first type of control signal is obtained in the current clock cycle, the transmit queue and the second selector S2 are used to read the first target instruction which is written in the first register 71 last time and is valid, wherein the first type of control signal indicates that the current clock cycle is a safe period.

[0093] In the case that the second type of control signal is obtained in the current clock cycle, the transmit queue and the second selector S2 stop reading the instruction from the first register 71; the second selector S2 is used to read the first target instruction which is written in the transmit queue last time; wherein the second type of control signal indicates that the current clock cycle is a non-safe period.

[0094] The second selector S2 is used to send the instruction read in the current clock cycle as the second target instruction to the second register 72 and the N pre-decoding units.

[0095] It should be understood that the second target instruction also includes N microcode instructions, and the pre-decoding unit can obtain the corresponding microcode instruction, for example, the pre-decoding unit 0 obtains the 0-31 bits of the first microcode instruction as the second target instruction, the pre-decoding unit 1 obtains the 31-63 bits of the first microcode instruction as the second target instruction, the pre-decoding unit 2 obtains the 64-95 bits of the first microcode instruction as the second target instruction, and the pre-decoding unit 3 obtains the 96-127 bits of the first microcode instruction as the second target instruction. It should be noted that in the drawings of the embodiment of the present application, N is taken as an example of 4, but it is not limited to this.

[0096] The jth pre-decoding unit is configured to pre-decode the jth microcode instruction received in the current clock cycle to obtain jth pre-decoding information corresponding to the jth microcode instruction, and send the jth pre-decoding information to the second register 72.

[0097] In Figure 1 On the basis of the above, regarding the decoding module, the embodiment of the application further provides an alternative implementation, please refer to Figure 4 , Figure 4 The structural diagram of the decoding module provided by the embodiment of the application.

[0098] The decoding module 30 comprises N decoding units (also referred to as microcode slot decoding units), a microcode scoreboard, a register file and a register hazard checking unit.

[0099] The input end of the N decoding units is connected to the second register 72, the output end of the N decoding units is connected to the microcode scoreboard and the third register 73, and the microcode scoreboard is connected to the register hazard checking unit.

[0100] The register file is connected to the second register 72 through a microcode read port, the number of microcode read ports corresponding to different pre-decoding units can be different, and the number is configured according to user requirements, the output end of the register file is connected to the third register 73, and the register file is also connected to a back-end module (write-back module 60).

[0101] The register hazard checking unit is also connected to the second register, the control end of the transmit queue and the control end of the second selector S2.

[0102] The jth decoding unit is configured to read the jth microcode instruction in the second target instruction written (and valid) most recently in the second register 72 in the current clock cycle, and decode to obtain jth decoding information, and send the jth decoding information to the third register 73 and the microcode scoreboard.

[0103] The microcode scoreboard is configured to store hazard-related information, wherein the hazard-related information comprises an instruction type corresponding to a microcode instruction, a destination register address and a number of execution cycles.

[0104] The instruction type and the number of execution cycles are used to indicate the number of occupied cycles of the destination register, and after the number of occupied cycles, the hazard-related information can be deleted from the microcode scoreboard. The instruction type is used to indicate the execution unit of the instruction, and the number of execution cycles is used to indicate the number of clock cycles required for the completion of the instruction execution. After the completion of the instruction execution, it means that the data of the destination register is ready, and the destination register will no longer exist data and structural hazard.

[0105] The register hazard checking unit is configured to read the N sets of pre-decoding information written in the second register 72 in the current clock cycle, and perform a query in the microcode scoreboard based on the N sets of pre-decoding information, to determine whether there is a data hazard and a structure hazard.

[0106] If the source register address or the destination register address in the pre-decoding information is the same as the destination register address in the microcode scoreboard in the execution state, it is considered that there is an hazard dependent relationship, at this time, there is a data hazard or a structure hazard.

[0107] If there is a data hazard or a structure hazard, the register hazard checking unit is configured to send the second type of control signal to the pre-decoding module 20; if there is no data hazard and structure hazard, the register hazard checking unit is configured to send the first type of control signal to the pre-decoding module 20.

[0108] In an optional embodiment, in the non-safe period, the register hazard checking unit can also send the second type of control signal to the instruction fetch module 10 (in the instruction memory) to avoid writing a new first target instruction into the first register 71 before the first target instruction in the first register 71 is read.

[0109] The register file is configured to read the N sets of pre-decoding information written in the second register 72 in the current clock cycle, and send the corresponding source data to the third register 73 according to the source register address in the pre-decoding information.

[0110] Please continue to refer to Figure 1 After entering the current clock cycle, the first register 71 is configured to send the instruction fetch start address received in the last clock cycle to the second register 72; the second register 72 is configured to send the instruction fetch start address received in the last clock cycle to the third register 73; the third register 73 is configured to send the source data corresponding to the first type of decoding unit and the first type of decoding information received in the last clock cycle to the fourth register 74; wherein the first type of decoding information is the decoding information generated by the first type of decoding unit, and the first type of decoding unit is a decoding unit with the ability to process store instructions or load instructions.

[0111] The execution module 40 is configured to perform a corresponding operation according to the instruction fetch start address, the N sets of decoding information and the source data written in the third register 73 in the last clock cycle, send the obtained operation result and the corresponding destination register address to the fourth register 74, and send the obtained second address to the instruction fetch module 10.

[0112] The fourth register 74 is configured to send the operation result received in the last clock cycle and the corresponding destination register address to the fifth register 75.

[0113] The access module 50 is configured to read the first type of decode information written in the fourth register 74 last time, and when the operation action in the first type of decode information is a storage action, store the source data corresponding to the first type of decode information to a corresponding address, and when the operation action in the first type of decode information is a load action, obtain load data from the corresponding address, and send the load data and a corresponding destination register address to the fifth register 75.

[0114] The corresponding address is an address calculated according to the instruction type, the operation action and the source data.

[0115] The write-back module 60 is configured to read the operation result and the load data written in the fifth register 75 last time in a current clock cycle, and write the operation result and the load data back to the register file according to the corresponding destination register address.

[0116] On the basis of Figure 1 , the embodiment of the present application further provides an optional implementation of the structure of the execution module, please refer to Figure 5 , Figure 5 the structure diagram of the execution module provided by the embodiment of the present application.

[0117] The execution module 40 includes a branch execution unit and N arithmetic logic units (also referred to as microcode slot arithmetic logic units).

[0118] The branch execution unit is connected to the third register 73, input ends of the N arithmetic logic units are connected to the third register 73, and output ends of the N arithmetic logic units are connected to the fourth register 74.

[0119] The branch execution unit is configured to read the instruction fetch start address, the second type of decode information and the source data written in the third register 73 in a last clock cycle, wherein the second type of decode information is decode information generated by a second type of decode unit, and the second type of decode unit is a decode unit having the capability of processing system instructions.

[0120] The branch execution unit is configured to generate a second address according to the information read by the branch execution unit, and feed back the second address to the instruction fetch module 10.

[0121] The jth arithmetic logic unit is configured to read the jth decode information and the source data written in the third register 73 in a last clock cycle, and perform a corresponding logical operation based on the jth decode information and the source data to obtain a jth operation result, and send the jth operation result and a corresponding destination register address to the fourth register 74.

[0122] It should be noted that the arithmetic logic unit includes any one or more of an addition unit, a logic unit, a multiplication unit, a system instruction & system operation unit, a division unit, and a shift unit. In some scenarios, the branch execution unit can be combined with 1 arithmetic logic unit to save space.

[0123] Optionally, the branch execution unit is further configured to feed back a branch instruction completion signal (F0) to the instruction fetching module 10 (to the instruction memory and identification unit) after determining that the branch instruction execution is completed, so that the instruction fetching module 10 returns from the branch instruction fetching state to the sequential instruction fetching state.

[0124] Please continue to refer to Figure 5 The memory access module 50 includes a data memory.

[0125] The data memory is configured to read the first type of decoding information most recently written in the fourth register 74, when the operation action in the first type of decoding information is a storage action, store the source data corresponding to the first type of decoding information into the corresponding address in the data memory, when the operation action in the first type of decoding information is a load action, obtain the load data from the corresponding address in the data memory, and send the load data and the corresponding destination register address to the fifth register 75.

[0126] Please refer to Figure 6 , Figure 6 A connection schematic diagram between the write-back module and the register file provided by the embodiment of the present application is shown. N connection channels are provided between the write-back module 60 and the register file.

[0127] It should be noted that the modules connected to the clock line in the embodiment of the present application can receive the clock signal, but the units or modules receiving the clock signal are not limited to the modules connected to the clock line. In order to ensure the clarity of the drawings, part of them is not drawn.

[0128] The embodiment of the present application further provides an electronic device, which includes the RISC-V-based processor described above.

[0129] In summary, the embodiment of the present application provides a processor based on RISC-V and an electronic device, the instruction fetch module performs instruction extraction according to the instruction fetch start address of the current clock cycle in the sequential instruction fetch state, and writes the obtained first target instruction start address into the first register; the first target instruction includes at least two microcode instructions; the pre-decoding module performs pre-decoding processing on the second target instruction, and sends the obtained N groups of pre-decoding information and the second target instruction to the second register; the decoding module reads the second target instruction and N groups of pre-decoding information written recently from the second register, determines whether the current clock cycle is a safe period based on the second target instruction and N groups of pre-decoding information, and feeds back the judgment result of the safe period to the pre-decoding module; the source data corresponding to the source register address in the pre-decoding information is sent to the third register, the decoding processing is performed on the read second target instruction to obtain N groups of decoding information, and the N groups of decoding information are sent to the third register; the back-end module executes the corresponding microcode instruction according to the N groups of decoding information, the source data and the N groups of decoding information written recently in the third register. The first target instruction includes at least two microcode instructions, so that multiple microcode instructions can be executed in each clock cycle, and the operation performance of the processor can be improved. Through pre-decoding, the source register address is obtained in advance and output to the second register, then the register file can be accessed according to the pre-decoding information at the same time of decoding, the decoding information and the source data are written into the third register synchronously, so that the corresponding source data can be directly called when the microcode instruction is executed, and the running efficiency of the processor is improved.

[0130] The above only describes preferred embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0131] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A RISC-V based processor, characterized in that, include: The instruction fetch module is used to fetch instructions based on the fetch start address of the current clock cycle in sequential fetch mode, and write the obtained first target instruction start address into the first register; the first target instruction includes at least two microcode instructions; The pre-decoding module is used to perform pre-decoding processing on the second target instruction and send the obtained N sets of pre-decoding information and the second target instruction to the second register. If the current clock cycle is a safe cycle, the second target instruction is the first target instruction that was recently written to and is valid in the first register. If the current clock cycle is an unsafe cycle, the second target instruction is the first target instruction that was read from the first register in the most recent safe cycle. The j-th group of pre-decoding information includes the destination register address and the source register address corresponding to the j-th microcode instruction. The safe cycle indicates that the second target instruction written to the second register in the previous clock cycle does not have a data hazard or a structural hazard, while the unsafe cycle indicates that the second target instruction written to the second register in the previous clock cycle has a data hazard or a structural hazard. The decoding module is used to read the most recently written second target instruction and N sets of pre-decoding information from the second register, determine whether the current clock cycle is a safe cycle based on it, and feed back the safe cycle judgment result to the pre-decoding module; send the corresponding source data to the third register according to the source register address in the pre-decoding information, perform decoding processing on the read second target instruction to obtain N sets of decoding information, and send the N sets of decoding information to the third register; The j-th group of decoding information includes the instruction type, destination register address, operation action, number of execution cycles, and immediate value corresponding to the j-th microcode instruction; The backend module is used to execute the corresponding microcode instructions based on the N sets of decoding information and source data recently written to the 3rd register.

2. The RISC-V-based processor as described in claim 1, characterized in that, The instruction fetching module includes a first selector, a program counter, an adder, an instruction memory, and an identification unit; The program counter is used to send the fetch start address of the current clock cycle to the instruction memory and register number 1; The instruction memory is used to fetch instructions according to the start address of the current clock cycle in sequential instruction fetch mode, and write the fetched first target instruction into the first register; The identification unit is used to determine whether the first target instruction is a branch instruction; if not, it sends a sequential execution signal to the first selector; if yes, it sends a branch execution signal to the first selector. The adder is used to determine the first address based on the fetch start address of the current clock cycle and the preset number of bytes, and then sends the first address to the first selector; The first selector is also used to receive the second address fed back by the backend module, where the second address is the execution result of the branch instruction; The first selector is also used to send a first address to the program counter when a sequential execution signal is received, and to send a second address to the program counter when a branch execution signal is received; The program counter is also used to store the address sent by the first selector in the current clock cycle and use it as the start address for fetching the instruction in the next clock cycle.

3. The RISC-V-based processor as described in claim 1, characterized in that, The pre-decoding module includes a transmission queue, a second selector, and N pre-decoding units, where N represents the total number of microcode instructions in the first target instruction. If the first type of control signal is obtained in the current clock cycle, the transmit queue and the second selector are used to read the most recently written and valid first target instruction in the first register, wherein the first type of control signal indicates that the current clock cycle is a safe cycle; If the second type of control signal is received in the current clock cycle, the transmit queue and the second selector stop reading instructions from the first register; the second selector is used to read the first target instruction that was most recently written in the transmit queue; wherein, the second type of control signal indicates that the current clock cycle is an unsafe cycle; The second selector is used to send the instruction it reads in the current clock cycle as the second target instruction to the second register and N pre-decode units; The j-th pre-decoding unit is used to pre-decode the j-th microcode instruction received in the current clock cycle to obtain the j-th group of pre-decoding information corresponding to the j-th microcode instruction, and send the j-th group of pre-decoding information to the second register.

4. The RISC-V-based processor as described in claim 3, characterized in that, The decoding module includes N decoding units, a microcode scoring board, a register file, and a register hazard checking unit. The j-th decoding unit is used to read the j-th microcode instruction from the second target instruction most recently written in the second register during the current clock cycle, and decode it to obtain the j-th group of decoding information, and send the j-th group of decoding information to the third register and the microcode scoring board; The microcode scoring board is used to store hazard-related information, which includes the instruction type, destination register address, and execution cycle number corresponding to the microcode instruction. The register hazard checking unit is used to read the N sets of pre-decoding information most recently written to the second register in the current clock cycle, and to query the microcode scoring board based on the N sets of pre-decoding information to determine whether there are data hazards and structural hazards. If a data hazard or structural hazard exists, the register hazard checking unit is used to send a second type of control signal to the pre-decoding module; if no data hazard or structural hazard exists, the register hazard checking unit is used to send a first type of control signal to the pre-decoding module. The register file is used to read the N sets of pre-decoding information most recently written to the second register in the current clock cycle, and send the corresponding source data to the third register according to the source register address in the pre-decoding information.

5. The RISC-V-based processor as described in claim 4, characterized in that, Register 1 is used to send the fetch start address received in the previous clock cycle to Register 2; Register 2 is used to send the fetch start address received in the previous clock cycle to Register 3; Register 3 is used to send the source data and first-type decoding information corresponding to the first-type decoding unit received in the previous clock cycle to Register 4; wherein, the first-type decoding information is the decoding information generated by the first-type decoding unit, and the first-type decoding unit is a decoding unit with the ability to process store instructions or load instructions; The backend module includes: an execution module, a fourth register, a memory access module, a fifth register, and a write-back module; The execution module is used to perform corresponding operations based on the instruction fetch start address, N sets of decoding information and source data written in the 3rd register in the previous clock cycle, send the obtained operation result and the corresponding destination register address to the 4th register, and send the obtained second address to the instruction fetch module. Register 4 is used to send the result of the operation received in the previous clock cycle and its corresponding destination register address to Register 5; The memory access module is used to read the most recently written first-type decoding information in the 4th register. When the operation action in the first-type decoding information is a storage action, the source data corresponding to the first-type decoding information is stored in the corresponding address. When the operation action in the first-type decoding information is a loading action, the loading data is obtained from the corresponding address, and the loading data and the corresponding destination register address are sent to the 5th register. The write-back module is used to read the most recent operation result and loaded data written to register 5 in the current clock cycle, and write the operation result and loaded data back to the register file according to the corresponding destination register address.

6. The RISC-V-based processor as described in claim 5, characterized in that, The execution module includes a branch execution unit and N arithmetic logic units; The branch execution unit is used to read the instruction fetch start address, second-type decoding information and source data written to the third register in the previous clock cycle. The second-type decoding information is the decoding information generated by the second-type decoding unit, which is a decoding unit capable of processing system instructions. The branch execution unit is used to generate a second address based on the information it reads, and then feeds the second address back to the instruction fetch module; The j-th arithmetic logic unit is used to read the j-th group of decoded information and source data written by the 3rd register in the previous clock cycle, and perform corresponding logical operations based on the two to obtain the j-th operation result, and send the j-th operation result and its corresponding destination register address to the 4th register.

7. The RISC-V-based processor as described in claim 6, characterized in that, The branch execution unit is also used to send a branch instruction completion signal to the instruction fetch module after determining that the branch instruction has been executed, so that the instruction fetch module can return from the branch fetch state to the sequential fetch state.

8. The RISC-V-based processor as described in claim 5, characterized in that, The memory access module includes a data storage device; The data memory is used to read the most recently written first-type decoding information from the fourth register. When the operation in the first-type decoding information is a storage operation, the source data corresponding to the first-type decoding information is stored in the corresponding address in the data memory. When the operation in the first-type decoding information is a loading operation, the loaded data is obtained from the corresponding address in the data memory, and the loaded data and the corresponding destination register address are sent to the fifth register.

9. An electronic device, characterized in that, Includes the RISC-V-based processor according to any one of claims 1-8.

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