High-speed interfaces, chips, and multi-channel data synchronization methods for high-speed interfaces

By introducing a synchronous control circuit into the high-speed interface, the problem of multi-channel data transmission deviation was solved, realizing synchronous transmission of multi-channel data and improving the compatibility of the device and the stability of data transmission.

CN120295948BActive Publication Date: 2026-06-30锐泰微(北京)电子科技有限公司
View PDF 1 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
锐泰微(北京)电子科技有限公司
Filing Date
2025-02-28
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

In modern electronic devices, high-speed interfaces and multi-channel data transmission suffer from discrepancies. Existing synchronization methods struggle to achieve strict synchronization between different channels, impacting system performance and data integrity.

Method used

A synchronization control circuit is introduced into the high-speed interface. By synchronizing the control signals output by the digital circuit sections of multiple channels, first and second synchronization control signals are generated. These signals are used to control the data transmission between the digital and analog circuits and the parallel-to-serial conversion process of the analog circuits, respectively, thereby eliminating multi-channel data deviation.

Benefits of technology

It effectively reduces the multi-channel data deviation of high-speed interfaces, improving device compatibility and data transmission stability.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN120295948B_ABST
    Figure CN120295948B_ABST
Patent Text Reader

Abstract

This application provides a high-speed interface, a chip, and a multi-channel data synchronization method for the high-speed interface. The high-speed interface includes: multiple channels; a synchronization control circuit that performs synchronization processing on multiple control signals output from multiple digital circuit sections in the multiple channels to generate multiple first synchronization control signals and multiple second synchronization control signals synchronized with a high-speed clock signal and / or a low-speed clock signal. Each first synchronization control signal controls the data transmission process between the digital circuit section and the analog circuit section in the corresponding channel, and each second synchronization control signal controls the parallel-to-serial conversion process of data in the analog circuit of the corresponding channel. This application's solution adds synchronization control between digital circuits and analog circuits, and between analog circuits and digital circuits, reducing multi-channel data deviation in the high-speed interface, achieving multi-channel data synchronization, and improving the compatibility of high-speed interface devices.
Need to check novelty before this filing date? Find Prior Art