Large-scale circuit partitioning method based on artificial intelligence adaptive weight distribution

Abstract

The application discloses a large-scale circuit partitioning method based on artificial intelligence adaptive weight distribution, and belongs to the technical field of integrated circuit computer-aided design, and specifically as follows: first, a graph structure is established to obtain data containing circuit topology characteristics; then, a cubic interpolation method is used to convert the input into a uniform length, improving the generality of the model; a gating mechanism is introduced to establish the structures of input gates, output gates and forget gates, helping the model better perceive the dependency relationship between inputs; the data with circuit topology characteristics obtained through the above processing are trained to obtain a weight distribution model, and the partitioning weight is updated; finally, the large-scale circuit is partitioned by using the updated weight, and multi-index balanced parallel system simulation is realized. The application helps to accelerate the circuit simulation process and improve the parallel benefit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit computer-aided design, and particularly relates to a large-scale circuit partitioning method based on artificial intelligence adaptive weight distribution. BACKGROUND

[0002] Circuit simulation technology is a key technology in the integrated circuit design process, which can help circuit design engineers verify the correctness of the functional behavior of the circuit before expensive tape-out and manufacturing, and test the integrity of the circuit connection and function, thereby maximizing cost reduction and shortening product design cycle.

[0003] However, with the increasing integration of integrated circuits and the increasing prominence of nonlinear characteristics, simulation using SPICE simulation tools or direct method simulators is often expensive and time-consuming, and has been unable to meet the requirements of super large scale integrated circuit design. In circuit simulation, transient analysis is the most time-consuming part of all types of simulation, so the key to achieving simulation acceleration of large-scale analog circuits is to accelerate transient analysis, especially post-simulation transient analysis. Partitioning large-scale circuits and then using different transient step sizes for transient multi-rate simulation of different sub-circuits is a very effective acceleration method. The partitioned circuits can be calculated in parallel to improve simulation efficiency.

[0004] Existing partitioning algorithms can be divided into iterative algorithms, computational intelligence algorithms, multi-level partitioning algorithms, and approximation algorithms. Among them, the multi-level partitioning algorithm is a widely used high-efficiency and reliable partitioning algorithm. It can complete partitioning in a relatively short time and fully considers super-edge balance and device balance. However, these partitioning algorithms do not consider step length balance, resulting in a large difference in step length within some partitions, which dramatically increases circuit simulation time. The mismatch between step lengths within a partition reduces parallel gain and makes it difficult to obtain a large speedup ratio. Therefore, how to achieve efficient circuit partitioning and improve transient analysis performance has been a major challenge.

[0005] To solve this problem, the present application proposes a partitioning algorithm for adaptive weight distribution of large-scale circuits that simultaneously considers super-edge balance, device balance, and step length balance. This method uses device, node, step length, and weight data of the circuit to train a better weight distribution result through reinforcement learning algorithm, thereby improving the performance of circuit transient analysis. SUMMARY

[0006] The purpose of this invention is to achieve a large-scale circuit partitioning method with multi-index balancing and adaptive weight allocation. This method not only ensures that the circuit partitioning results are balanced in terms of step size, superedges, and devices, but also improves the efficiency of transient analysis and reduces circuit simulation time. To achieve the above-mentioned objective, this invention adopts the following technical solution: A large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation includes the following steps:

[0007] S1: Graph structure establishment: Input the nodes, devices, weights and step size information of the large-scale circuit, map them to the nodes, edges and weights of the graph, establish the graph structure, and obtain relevant data that can represent the topological characteristics of the circuit.

[0008] S2: Data processing, using cubic interpolation to convert the input into a uniform length, so that the model can be adapted to various circuits;

[0009] S3: Weight allocation, using the proposed reinforcement learning LP algorithm to obtain updated adaptive weights based on the processed data;

[0010] S4: Circuit partitioning, which is implemented in three stages: reducing graph size, dual partitioning, and fine partitioning. The large-scale circuit is partitioned using the redistributed weights.

[0011] In step S1 above, the graph structure establishment includes the following steps: First, the nodes, devices, weights, and step size information of the input circuit are used to establish the graph structure, including the following steps: One-hot encoding is performed according to the device type connected to the circuit node, and the nodes in the circuit are... Mapped to nodes of a graph To the components in the circuit Convert to edges in the graph At the same time, the weights will be divided. Weights of the view graph Node and edge information are calculated separately. Then, sufficient circuit data samples are collected, and a graph convolutional neural network is used to train the model and establish a graph structure. Next, a model is built based on the obtained graph structure to obtain data containing the corresponding topological features of each circuit. The feature update formula is as follows:

[0012]

[0013] in, , They represent the first Layer and first The node feature matrix of the layer, Indicates the first The weight matrix of the layer, Adjacency matrix The sum of the identity matrix, Let the node degree matrix be... This is the activation function.

[0014] In step S2 above, a cubic polynomial function is first used to fit the input data. Determine the coefficients of the interpolation function, where the interpolation function... As shown below, the values ​​of the interpolation points are estimated using the obtained polynomial function, and the data is mapped onto a one-dimensional grid of length 10000.

[0015]

[0016] in, The points to be interpolated. It is the number of known data points. These are the variable value and function value of the m-th known data point, respectively.

[0017] In step S3 above, the process of establishing the weight allocation model is as follows: First, a long short-term memory network is used to extract features from the input data, as shown in the following formula:

[0018]

[0019] in, Indicates the first The weight of each device, Indicates an LSTM network. Indicates the first data processing step. Individual device weights.

[0020] Next, the near-end policy optimization algorithm was improved to train an adaptive weight model. The objective function calculation formula is shown below:

[0021]

[0022] in, for The strategy parameters used at each moment for The advantage of time estimation Control the set clipping threshold within the specified range. This allows the model to converge more stably to the optimal solution.

[0023] The formula for calculating the reward function is as follows:

[0024]

[0025] in, Indicates the use of the first The computational cost required for transient analysis when the weights are partitioned after training. Indicates the first The reward value set for this training session. This indicates the computational cost required for transient analysis when using a partitioning method with fixed weights based on device type.

[0026] Subsequently, the interpolated data is input into the trained model to obtain the newly assigned weights, which are then converted into an array with the same length as the original weights and fixed within a specified interval. The formula for calculating the new weights is as follows:

[0027]

[0028]

[0029]

[0030] in, For activation function, To find a set of means The variance is Normally distributed data. Linear is a linear layer. The data after interpolation. For the updated weights, the following is the specific function form of the activation function with x as input:

[0031]

[0032]

[0033] .

[0034] In step S4 above, the large-scale circuit partitioning process is as follows: First, the number of vertices in the circuit diagram is gradually reduced until a preset threshold is reached, and the original complex circuit diagram is mapped to a simpler equivalent graph, thereby reducing the size of the graph.

[0035] Next, the thickest hypergraph Divided into multiple sub-regions First, select an initial supernode and set it as the initial superregion. Then, select the best neighboring node connected to the current superregion and expand the size of the superregion. Subsequently, iterate the above operations until all nodes are assigned, achieving multi-way partitioning of the graph. The goal of this stage is to achieve the minimum set of superedges, calculated as shown in the following formula:

[0036]

[0037] in, For a set of nodes, This is the weight matrix. and These are the nodes of the i-th and j-th sub-regions in the k sub-regions, respectively.

[0038] Finally, an iteratively improved heuristic algorithm is used to continuously reduce the hyperedge set, thereby improving the partitioning quality. The partitioning results are then mapped back to the original graph to obtain the final partitioning result.

[0039] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the large-scale circuit partitioning method described above for achieving multi-index balancing and adaptive weight allocation.

[0040] A computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the large-scale circuit partitioning method for achieving multi-index balancing and adaptive weight allocation.

[0041] Compared with the prior art, the advantages of the present invention are as follows:

[0042] 1) This invention proposes a partitioning method for large-scale circuits that simultaneously achieves hyperedge balancing, node balancing, and step size balancing through adaptive weight allocation. By combining a multi-level partitioning algorithm with a weight allocation algorithm for circuit partitioning, the computational cost of transient analysis is reduced by up to 39.725%, and the circuit simulation time is reduced by up to 17.283%.

[0043] 2) This invention establishes a graph structure based on the devices, nodes, step size, and weight information in the circuit, thereby avoiding the problem of loss of circuit topology features caused by directly inputting weights and improving weight allocation performance.

[0044] 3) This invention performs three interpolation processes on the input data and maps it to a grid of the same length, thereby solving the problem that the model and the circuit must correspond one-to-one and increasing the versatility of the model.

[0045] 4) In the process of training the weight allocation model, this invention uses a long short-term memory network for feature extraction, thereby better perceiving the complex dependencies between inputs and improving model performance.

[0046] 5) The present invention trains a near-end policy optimization algorithm model, which, combined with multi-step learning strategies, target pruning functions and other techniques, can converge to the global optimum more smoothly and stably. Attached Figure Description

[0047] Figure 1 This is a flowchart illustrating the algorithm for the large-scale circuit partitioning method of the present invention, which achieves multi-index balancing and adaptive weight allocation.

[0048] Figure 2This is a schematic diagram illustrating the structure of the present invention.

[0049] Figure 3 This is a schematic diagram of the data processing of the present invention.

[0050] Figure 4 This is a schematic diagram of the Long Short-Term Memory network and proximal policy optimization algorithm model of the present invention.

[0051] Figure 5 This is a flowchart illustrating the implementation of large-scale circuit partitioning in this invention. Detailed Implementation

[0052] To enhance understanding of the present invention, further description of the invention is provided below in conjunction with the accompanying drawings and specific embodiments.

[0053] Example 1: This specific implementation discloses a large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation, such as... Figure 1 Figure 5 As shown, it includes the following steps:

[0054] S1: As Figure 2 As shown, the nodes, devices, weights, and step size information of a large-scale circuit are input and mapped to the nodes, edges, and weights of a graph. Sufficient data samples are obtained to build a graph structure model, yielding relevant data that can represent the circuit's topological characteristics.

[0055] S2: As Figure 3 As shown, the data is interpolated three times to convert the input into a uniform length, making the model suitable for various circuits and improving its versatility.

[0056] S3: As Figure 4 As shown, the LP algorithm, which is improved based on long short-term memory network and proximal policy optimization algorithm, obtains updated weights based on the processed data.

[0057] S4: As Figure 5 As shown, the large-scale circuit is divided into three implementation stages: reducing graph size, dual partitioning, and fine partitioning. The weights are redistributed to divide the circuit.

[0058] In step S1, such as Figure 2 As shown, the graph structure is first established by inputting the node, device, weight, and step size information of the circuit, including the following steps: performing one-hot encoding based on the device type connected to the circuit node, and encoding the nodes in the circuit... Mapped to nodes of a graph To the components in the circuit Convert to edges in the graph At the same time, the weights will be divided. Weights of the view graph Node and edge information are calculated separately. Then, sufficient circuit data samples are collected, and a graph convolutional neural network is used to train the model and establish a graph structure. Next, a model is built based on the obtained graph structure to obtain data containing the corresponding topological features of each circuit. The feature update formula is shown below:

[0059]

[0060] in, , They represent the first Layer and first The node feature matrix of the layer Indicates the first The weight matrix of the layer, Adjacency matrix The sum of the identity matrix, Let the node degree matrix be... This is the activation function.

[0061] In step S2, such as Figure 3 As shown, the input data is first fitted using a cubic polynomial function. Determine the coefficients of the interpolation function, where the interpolation function... As shown below, the values ​​of the interpolation points are estimated using the obtained polynomial function, and the data is mapped onto a one-dimensional grid of length 10000.

[0062]

[0063] in, The points to be interpolated. It is the number of known data points. These are the variable value and function value of the m-th known data point, respectively.

[0064] In step S3, such as Figure 4 As shown, the process of establishing the weight allocation model is as follows: First, a Long Short-Term Memory (LSTM) network is used to extract features from the input data, as shown in the following formula:

[0065]

[0066] in, Indicates the first The weight of each device, Indicates an LSTM network. Indicates the first data processing step. Individual device weights.

[0067] Next, the near-end policy optimization algorithm was improved to train an adaptive weight model. The objective function calculation formula is shown below:

[0068]

[0069] in, Indicates time step The expected value, i.e. the average value of the sampled data, for The strategy parameters used at each moment for The advantage of time estimation The set clipping threshold. To prune the target function, control it within a specified range. This allows the model to converge more stably to the optimal solution.

[0070] The formula for calculating the reward function is as follows:

[0071]

[0072] in, Indicates the use of the first The computational cost required for transient analysis when the weights are partitioned after training. Indicates the first The reward value set for this training session. This indicates the computational cost required for transient analysis when using a partitioning method with fixed weights based on device type.

[0073] Subsequently, the interpolated data is input into the trained model to obtain the newly assigned weights, which are then converted into an array with the same length as the original weights and fixed within a specified interval. The formula for calculating the new weights is as follows:

[0074]

[0075]

[0076]

[0077] in, For activation function, To find a set of means The variance is Normally distributed data. Linear is a linear layer. The data after interpolation. For the updated weights, the following is the specific function form of the activation function with x as input:

[0078]

[0079]

[0080] .

[0081] In step S4, such as Figure 5 As shown, the number of vertices in the circuit diagram is gradually reduced until a preset threshold is reached, mapping the original complex circuit diagram to a simpler equivalent graph and reducing the size of the graph.

[0082] Next, the thickest hypergraph Divided into multiple sub-regions First, select an initial supernode and set it as the initial superregion. Then, select the best neighboring node connected to the current superregion and expand the size of the superregion. Subsequently, iterate the above operations until all nodes are assigned, achieving multi-way partitioning of the graph. The goal of this stage is to achieve the minimum set of superedges, calculated as shown in the following formula:

[0083]

[0084] in, For a set of nodes, This is the weight matrix. and These are the nodes of the i-th and j-th sub-regions in the k sub-regions, respectively.

[0085] Finally, an iteratively improved heuristic algorithm is used to continuously reduce the hyperedge set, thereby improving the partitioning quality. The partitioning results are then mapped back to the original graph to obtain the final partitioning result.

[0086] Example 1:

[0087] This method uses large-scale industrial circuits for testing, and some test circuit information is shown in Table 1.

[0088] Table 1. Partial Test Circuit Information

[0089]

[0090] The initial learning rate for both the action network and the evaluation network during model training was set to 0.01, and the Adam optimizer was selected for parameter optimization. The number of training epochs was set to 200.

[0091] The circuit partitioning method of the present invention, which integrates weight allocation, the method that only performs circuit partitioning, and the METIS algorithm are compared. The total computational cost required for transient analysis after partitioning is shown in Table 2.

[0092] Table 3 shows the simulation time performance of the circuit partitioning method with integrated weight allocation and the method that only performs circuit partitioning. The smaller the transient analysis time and the total simulation time, the better the partitioning performance.

[0093] Table 4 shows the performance of the circuit partitioning method with integrated weight allocation and the method that only performs circuit partitioning in terms of partition balance and number of decompositions. Indicator 1 is the difference between the maximum and minimum total number of nodes, and indicator 2 is the difference between the maximum and minimum number of internal nodes, used to measure the balance of each partition in the partitioning result. Indicators 3 and 4 are the number of partition decompositions and the number of top decompositions, respectively, which can be used to measure the complexity of the transient analysis task. Smaller indicators indicate better partitioning performance.

[0094] The best performance is highlighted in bold. The method of this invention achieves optimal partitioning performance in terms of total computational cost, simulation time, partition balance, and number of decompositions.

[0095] Table 2 Total computational cost of different partitioning algorithms ( Comparison results

[0096]

[0097] Table 3. Comparison of simulation times for different partitioning algorithms

[0098]

[0099] Table 4 Comparison of partitioning results from different partitioning algorithms

[0100]

[0101] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. A large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation, characterized in that: Includes the following steps: S1: Graph structure establishment. Input the nodes, devices, weights, and step size information of a large-scale circuit, map them to the nodes, edges, and weights of a graph, establish the graph structure, and obtain relevant data that can represent the topological characteristics of the circuit. S2: Data processing, using cubic interpolation to convert the input to a uniform length, making the model suitable for various circuits. S3: Weight allocation, using the proposed reinforcement learning LP algorithm to obtain updated adaptive weights based on the processed data. S4: Circuit partitioning, which is implemented in three stages: reducing graph size, multi-path partitioning, and fine partitioning. The large-scale circuit is partitioned using the redistributed weights. Step S3 mainly includes the following steps: S31: Feature Extraction: First, a Long Short-Term Memory (LSTM) network is used to extract features from the input data, as shown in the following formula: in, Indicates the first The weight of each device, Indicates an LSTM network. Indicates the first data processing step. Individual device weights S32: Reward Function: Next, the near-end policy optimization algorithm is improved to train an adaptive weight model. The objective function calculation formula is shown below: in, for The strategy parameters used at each moment for The advantage of time estimation Control the set clipping threshold within the specified range. This allows the model to converge more stably to the optimal solution. The formula for calculating the reward function is as follows: in, Indicates the use of the first The computational cost required for transient analysis when the weights are partitioned after training. Indicates the first The reward value set for this training session. This indicates the computational cost required for transient analysis when using a partitioning method with fixed weights based on device type. S33: Model Training: Combine multi-step learning strategies, objective function pruning and other techniques to train the data so that the model can smoothly and stably converge to the global optimum and obtain an adaptive weight model. S34: Weight Acquisition: Input the interpolated data into the trained model to obtain the assigned new weights, convert them into an array with the same length as the original weights, and fix them within a specified interval. The formula for calculating the new weights is as follows: in, For activation function, To obtain a set of means The variance is Normally distributed data, with Linear as the linear layer. The data after interpolation. For the updated weights, the following is the specific function form of the activation function with x as input: 。 2. The large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation according to claim 1, characterized in that: In step S1, the graph structure is established by acquiring data obtained from the circuit pre-simulation analysis, including weights. ,node Components and step length One-hot encoding is performed and mapped to graph information to build data samples; the data samples are then trained to obtain a model of the graph structure, thereby obtaining data containing circuit topology features. Among them, the data of circuit topology features The formula is shown below: in, , They represent the first Layer and first The node feature matrix of the layer, Indicates the first The weight matrix of the layer, Adjacency matrix The sum of the identity matrix, Let the node degree matrix be... This is the activation function.

3. The large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation according to claim 1, characterized in that: Step S2 mainly includes the following steps: First, fit the input data using a cubic polynomial function. Determine the coefficients of the interpolation function, where the interpolation function... As shown below, the values ​​of the interpolation points are estimated using the polynomial function obtained from the solution, and the data is mapped onto a one-dimensional grid of length 10000. in, The points to be interpolated. It is the number of known data points. These are the variable value and function value of the m-th known data point, respectively.

4. The large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation according to claim 1, characterized in that: Step S4 mainly includes the following steps: for the large-scale circuit, according to the updated weights, perform three steps to achieve partitioning: mapping the graph to a simpler equivalent graph, performing multi-path partitioning, and using an iterative improved heuristic algorithm to optimize the quality of the graph. Transient analysis is then performed to verify the effectiveness of the proposed partitioning method, as detailed below: The thickest hypergraph Divided into multiple sub-regions First, select an initial supernode and set it as the initial superregion. Then, select the best neighboring node connected to the current superregion and expand the size of the superregion. Subsequently, iterate the above operations until all nodes are assigned, realizing the multi-way partitioning of the graph. The goal of this stage is to achieve the minimum superedge set, calculated as shown in the following formula: in, For a set of nodes, This is the weight matrix. and These are the nodes of the i-th and j-th sub-regions in the k sub-regions, respectively. Finally, an iterative improved heuristic algorithm is used to continuously reduce the number of nodes, improve the partitioning quality, and map the partitioning results back to the original graph to obtain the final partitioning result.

5. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, it implements the large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation as described in any one of claims 1 to 4.

6. A computer-readable storage medium storing computer instructions thereon, characterized in that: When executed by the processor, the computer instructions implement the large-scale circuit partitioning method based on artificial intelligence adaptive weight allocation as described in any one of claims 1-4.

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