Degradation correction circuitry

Abstract

The degradation correction circuitry is capable of continuously providing power and a first signal to the first circuitry to produce a first output. Power and a second signal can be periodically provided to the second circuitry to produce a second output. The first circuitry and the second circuitry are different examples of the same circuitry. Degradation of the first circuitry can be measured by comparing the first output of the first circuitry to the second output of the second circuitry. In response to measuring the degradation of the first circuitry, the degradation of the first circuitry can be compared to a threshold. In response to determining that the degradation is greater than the threshold, a corrective action can be performed based on the degradation of the first circuitry to limit effects of degradation of the system.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to access memories, and more particularly, to a degradation correction circuit system. Background Art

[0002] Various types of electronic devices, such as digital logic circuits and memory systems, can store and process data. A digital logic circuit is an electronic circuit that processes digital signals or binary information, which can take two possible values (commonly represented as 0 and 1). Digital logic circuits can use logic gates to manipulate and transform digital signals or binary information. For example, digital logic circuits can be used in a wide range of electronic devices, including computers, calculators, digital clocks, and many other electronic devices that employ digital processing. Digital logic circuits can be designed to perform specific logic operations on digital inputs to produce digital outputs, and in some examples, can be combined to form more complex circuits to perform more complex operations. Memory devices can include one or more memory devices that store data. For example, the memory devices can be non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory system to store data at and retrieve data from the memory devices. Memory devices may degrade over time based on several factors. Summary of the Invention

[0003] An embodiment of the present disclosure provides a method for implementing a degradation correction circuit system, which includes: continuously supplying power and a first signal (225) to a first circuit system (222-1, 322-1, 322-3) to generate a first output (226); periodically supplying power and a second signal (225) to a second circuit system (222-2, 322-3, 322-4) to generate a second output (227), where the first circuit system and the second circuit system are different examples of the same circuit system; measuring the degradation of the first circuit system by comparing the first output of the first circuit system with the second output of the second circuit system; in response to measuring the degradation of the first circuit system, comparing the degradation of the first circuit system with a threshold; and in response to determining that the degradation is greater than the threshold, performing a correction action based on the degradation of the first circuit system to limit the impact of the degradation of the system.

[0004] Another embodiment of the present disclosure provides an apparatus for implementing a degradation correction circuit system, comprising: a first circuit system (222-1, 322-1, 322-3) including a first logic unit chain (223-1, 223-2, 223-3, 223-4, 223-5); a second circuit system (222-2, 322-2, 322-4) including a second logic unit chain (223-6, 223-7, 223-8, 223-9, 223-10), wherein the first logic unit chain and the second logic unit chain are the same logic unit chain; and a control circuit system (108) coupled to the first circuit system and the second circuit system. The control circuit system is configured to: supply power and signals (225) to the first circuit system to generate an aging signal (226); supply power and the signals to the second circuit system to generate a reference signal (227), wherein power is supplied to the second circuit system based on determining the degradation of the first circuit system, and wherein the signals are continuously supplied to the first circuit system and the second circuit system; and avoid supplying power to the second circuit system in response to measuring the degradation of the first circuit system. The apparatus further includes a measurement circuit system (136, 336-1, 336-2, 436) coupled to the first circuit system and the second circuit system and configured to: compare the aging signal with the reference signal; and use the comparison of the aging signal with the reference signal to measure the degradation of the first circuit system compared to the second circuit system.

[0005] Another embodiment of the present disclosure provides an apparatus for implementing a degradation correction circuit system, comprising: a first aging monitor (112, 212, 312-1, 312-2, 412-1, 412-2, 412-3, 412-4, 512-1, 512-2, 512-N), including a first reference circuit system (222-2, 322-2, 322-4) and a first aging circuit system (222-1, 322-1, 322-3); a second aging monitor (112, 212, 312-1, 312-2, 412-1, 412-2, 412-3, 412-4, 512-1, 512-2, 512-N), including a second reference circuit system (222-2, 322-2, 322-4) and a second aging circuit system (222-1, 322-1, 322-3); and a control circuit system (108) coupled to the first aging monitor and the second aging circuit system. The control circuit system is configured to monitor: provide a first signal to the first aging monitor to generate a first output (226) using the first reference circuit system and a second output (227) using the first aging circuit system; provide a second signal to the second aging monitor to generate a third output (226) using the second reference circuit system and a fourth output (227) using the second aging circuit system. The apparatus further includes a measurement circuit system (136, 336-1, 336-2, 436) coupled to the first aging monitor and the second aging monitor and configured to: compare the first output of the first aging monitor with the second output to determine a first degradation measurement of a first part of the apparatus; and compare the third output of the second aging monitor with the fourth output to determine a second degradation measurement of a second part of the apparatus. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 Illustrate an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 Illustrate a block diagram of an aging monitor according to some embodiments of the present disclosure.

[0009] Figure 3 Illustrate a block diagram of various aging monitors coupled to a plurality of measurement circuit systems according to some embodiments of the present disclosure.

[0010] Figure 4 Illustrate a block diagram of a plurality of aging monitors coupled to a measurement circuit system according to some embodiments of the present disclosure.

[0011] Figure 5 Block diagram of multiple aging monitors that receive power from multiple voltage regulators, according to some embodiments of the present disclosure.

[0012] Figure 6 Is a flowchart corresponding to a method for implementing a degradation correction circuit system, according to some embodiments of the present disclosure.

[0013] Figure 7 Is a block diagram of an example computer system in which embodiments of the present disclosure may operate. Detailed Description

[0014] Aspects of the present disclosure relate to a degradation correction circuit system. Power and a first signal may be continuously provided to a first circuit system to produce a first output. Power and a second signal may be periodically provided to a second circuit system to produce a second output. The first circuit system and the second circuit system may be different examples of the same circuit system. The degradation of the first circuit system may be measured by comparing the first output of the first circuit system with the second output of the second circuit system. In response to measuring the degradation of the first circuit system, the degradation of the first circuit system may be compared with a threshold. In response to determining that the degradation is greater than the threshold, a correction action may be performed based on the degradation of the first circuit system to limit the impact of the degradation on the system. The system may be a memory subsystem. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Examples of storage devices and memory modules are described below in connection with Figure 1 and elsewhere. Generally, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem. The host system may also cause the degradation of the memory subsystem to be measured.

[0015] Although some non-limiting examples herein are generally described in terms of their applicability to memory subsystems and / or memory devices, the embodiments are not so limited, and aspects of the present disclosure may also be applied to systems such as computer systems. The described embodiments may be applicable to systems-on-a-chip, computing subsystems, data collection and processing, storage, networking, communication, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems / subsystems and / or devices.

[0016] In various examples, the latency of the units of a system can degrade (e.g., increase) over the lifetime of the system. For example, due to a combination of the aging of the system, the temperature of the system, and / or the voltage of the system, as well as other factors that may cause the system to degrade, the degradation of the system may accelerate. As the system ages, the units of the system can experience degradation, which can affect the user experience. For example, as the system ages, the system may experience voltage drift. As used herein, the degradation of a system can also be referred to as the degradation of the system. Compared with the specifications of the system, the degradation of the system can refer to the loss of functionality over time. For example, given that the specifications of the system utilize a first voltage and / or the system utilizes a first voltage when the system is manufactured but a second voltage after the system ages, the voltage drift over time can be referred to as the degradation of the system.

[0017] To address these and other deficiencies of current methods, embodiments of the present disclosure implement an aging monitor. The aging monitor emulates the degradation of the system and / or the degradation of an application-specific integrated circuit system (ASIC) of the system. The aging monitor can include two or more equivalent gate chains. One of the gate chains can remain powered to emulate the power state of the system. Before performing the degradation measurement, another gate chain can remain unpowered.

[0018] The gate chain of the aging monitor (e.g., another gate chain) can be periodically powered to generate an output (e.g., an output signal). The output signal can be used to measure the degradation of the system. The degradation of the system can be at least partially attributed to the aging of the system. Based on the degradation of the system and / or the aging of the system measured using the output signal, the system can implement a corrective action to mitigate the degradation of the system. In various examples, the degradation of the system can be mitigated by reducing the clock frequency of the system and / or increasing the supply voltage of the system. The aging of the system approaching an irreparable stage can be indicated to the system and / or the end user of the system.

[0019] Figure 1 An example computing system 100 including a memory subsystem 103 is illustrated in accordance with some embodiments of the present disclosure. The memory subsystem 103 can include media, such as one or more volatile memory devices (e.g., memory device 110), one or more non-volatile memory devices (e.g., memory device 109), or a combination thereof.

[0020] The memory subsystem 103 can be a memory device, a memory module, or a combination of a memory device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0022] In other embodiments, the computing system 100 can be deployed on or otherwise included in a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile computing device, a vehicle (e.g., an airplane, a drone, a train, a car, or other vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a form factor of a tablet computer or a phablet. Generally, the tablet computer form factor can include a display screen between approximately 3 inches and 5.2 inches (diagonal measurement), while the phablet form factor can include a display screen between approximately 5.2 inches and 7 inches (diagonal measurement). However, examples of "mobile computing devices" are not limited thereto, and in some embodiments, a "mobile computing device" can refer to other types of edge computing devices such as IoT devices.

[0023] The computing system 100 can include a host system 102 coupled to one or more memory subsystems 103. In some embodiments, the host system 102 is coupled to different types of memory subsystems 103. Figure 1 Describe an example of a host system 102 coupled to one memory subsystem 103. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0024] The host system 102 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 102 writes data to and reads data from the memory subsystem 103 using, for example, the memory subsystem 103.

[0025] The host system 102 includes a processing unit 104. The processing unit 104 may be a central processing unit (CPU) configured to execute an operating system. In some embodiments, the processing unit 104 includes a complex instruction set computer architecture, such as x86 or other architecture suitable for use as a CPU of the host system 102.

[0026] The host system 102 may be coupled to the memory subsystem 103 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 102 and the memory subsystem 103. The host system 102 can further utilize a Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 109) when the memory subsystem 103 is coupled to the host system 102 via the PCIe interface. The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 103 and the host system 102. Figure 1 The memory subsystem 103 is described as an example. In general, the host system 102 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] The memory devices 109, 110 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., the memory device 110) may be, but is not limited to, a random access memory (RAM), such as a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 109) include NAND-type flash memories and write-in-place memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Additionally, contrary to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] One of memory devices 109, 110 can include one or more memory cell arrays. One type of memory cell (e.g., single-level cell (SLC)) can store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), and penta-level cell (PLC)) can store multiple bits per cell. In some embodiments, each of memory devices 109 can include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device can include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of memory device 109 can be grouped into pages, which can refer to logical units of the memory device for storing data. For some types of memories (e.g., NAND), pages can be grouped to form blocks.

[0030] Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, memory device 109 can be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 105 (or simply the controller 105 for simplicity) can communicate with the memory devices 109, 110 to perform operations such as reading data, writing data, or erasing data at the memory devices 109, 110 and other such operations. The memory subsystem controller 105 can include hardware such as, for example, one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 105 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 105 can include a processor 106 (e.g., a processing device) configured to execute instructions stored in local memory 107. In the illustrated example, the local memory 107 of the memory subsystem controller 105 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 103, the operations including handling communication between the memory subsystem 103 and the host system 102.

[0033] In some embodiments, the local memory 107 can include memory registers for storing memory pointers, fetched data, etc. The local memory 107 can also include read-only memory (ROM) for storing microcode. Although Figure 1 the illustrated memory subsystem 103 has been shown as including the memory subsystem controller 105, in another embodiment of the present disclosure, the memory subsystem 103 does not include the memory subsystem controller 105 but can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Generally, the memory subsystem controller 105 may receive commands or operations from the host system 102 and may convert the commands or operations into instructions or appropriate commands to effect the desired access to the memory device 109 and / or the memory device 110. The memory subsystem controller 105 may be responsible for other operations such as wear leveling operations associated with the memory device 109, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block address (LBA), namespace) and physical addresses (e.g., physical block address, physical media address). The memory subsystem controller 105 may further include host interface circuitry to communicate with the host system 102 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 109 and / or the memory device 110, and convert responses associated with the memory device 109 and / or the memory device 110 into information for the host system 102.

[0035] The memory subsystem 103 may further include additional circuitry or components not shown. In some embodiments, the memory subsystem 103 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive an address from the memory subsystem controller 105 and decode the address to access the memory device 109 and / or the memory device 110.

[0036] In some embodiments, the memory device 109 includes a local media controller 111 that operates in conjunction with the memory subsystem controller 105 to perform operations on one or more memory cells of the memory device 109. An external controller (e.g., the memory subsystem controller 105) may manage the memory device 109 externally (e.g., perform media management operations on the memory device 109). In some embodiments, the memory device 109 is a managed memory device that is an original memory device combined with a local controller (e.g., local media controller 111) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 103 may include an aging control circuitry 108. Although Figure 1 not shown in order to avoid obscuring the figures, the aging control circuitry 108 may include various circuitry to facilitate the operations described herein in Figure 2Aspects of the present disclosure described herein. In some embodiments, in accordance with the present disclosure, the aging control circuitry 108 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, hardware processing device, and / or other logic circuitry that may allow the aging control circuitry 118 to access a memory such as the local memory 107. In various examples, the aging control circuitry 108 may be external to the memory subsystem controller 105.

[0038] In some embodiments, the memory subsystem controller 105 includes at least a portion of the aging control circuitry 108. For example, the memory subsystem controller 105 may include a processor 106 (processing device) configured to execute instructions stored in the local memory 107 for performing the operations described herein. In some embodiments, the aging control circuitry 108 is part of the host system 102, application, or operating system. The aging control circuitry 108 may reside on the memory subsystem 103 and / or the memory subsystem controller 105. As used herein, the term "reside on" refers to something that is physically located on a particular component. For example, the aging control circuitry 108 "residing on the memory subsystem 103" refers to a situation where the hardware circuitry including the aging control circuitry 108 is physically located on the memory subsystem 103. The term "reside on" may be used interchangeably with other terms herein (e.g., "deployed on" or "located on").

[0039] The memory subsystem 103 may also include an aging monitor 112 and measurement circuitry 136. The aging control circuitry 108 may control the aging monitor 112 and the measurement circuitry 136. The aging control circuitry 108 may control the aging monitor 112 to cause the aging monitor 112 to generate two or more signals. The measurement circuitry 136 may compare the two or more signals to each other to measure the degradation of the memory subsystem 103.

[0040] The aging control circuit system 108 can utilize a first circuit system and a second circuit system respectively to generate a first signal and a second signal. The first circuit system can be aged to simulate the aging of the memory subsystem 103. The second circuit system can be a reference circuit system. The first signal and the second signal can respectively reflect the degradation of the first circuit system and the second circuit system. The measurement circuit system 136 can use the second circuit system as a reference to measure the degradation of the first circuit system. The measurement circuit system 136 can provide the measured degradation to the aging control circuit system 108. The aging control circuit system 108 can utilize the measured degradation of the first circuit system to determine the degradation of the memory subsystem 103. The aging control circuit system 108 can utilize the degradation of the memory subsystem 103 to determine whether to take a correction action to minimize the impact of the degradation of the memory subsystem 103 and / or determine what correction action to take to minimize the impact of the degradation of the memory subsystem 103. Although the examples provided herein are given in the context of the memory subsystem 103, the examples are also applicable to other systems, such as the system 100 and / or the host 102.

[0041] Figure 2 A block diagram illustrating an aging monitor 212 according to some embodiments of the present disclosure. The aging monitor 212 includes chained circuit systems 222-1, 222-2 and a power circuit system 229. The chained circuit system 222-1 includes gates 223-1, 223-2, 223-3, 223-4, 223-5. The chained circuit system 222-2 includes gates 223-6, 223-7, 223-8, 223-9, 223-10. The gates 223-1, 223-2, 223-3, 223-4, 223-5, 223-6, 223-7, 223-8, 223-9, 223-10 can be referred to as gates 223.

[0042] The voltage regulator 228 can supply power to the aging monitor 212. For example, the voltage regulator 228 can continuously supply power to the chained circuit system 222-1. The voltage regulator 228 can periodically supply power to the chained circuit system 222-2. For example, the power circuit system 229 can gate the power to the chained circuit system 222-2 based on a reference enable signal 224. The power circuit system 229 can be a power switch among other types of circuit systems that can be implemented to gate the power to the chained circuit system 222-2. The reference enable signal 224 can be provided from a controller (such as Figure 1 the aging control circuit system 108 and / or the processing unit 104). The controller can provide the reference enable signal 224 to enable power to be supplied from the voltage regulator 228 to the chained circuit system 222-2.

[0043] The pilot signal 225 can be continuously supplied to the chain circuit system 222-1 and the chain circuit system 222-2. When powered, the chain circuit system 222-1 can generate an aging signal 226, and the chain circuit system 222-2 can generate a reference signal 227. The pilot signal 225 can be switched between a high value and a low value. The pilot signal 225 can also be used to obtain the specific aging curves of the chain circuit system 222-1 and / or the chain circuit system 222-2 due to switching-related degradation. For example, the aging curves of the chain circuit system 222-1 and / or the chain circuit system 222-2 generated using the pilot signal 225 with a high duty cycle can be different from the aging curves of the chain circuit system 222-1 and / or the chain circuit system 222-2 generated using the pilot signal 225 with a low duty cycle. The pilot signal 225 that is switched between a high value and a low value can be continuously supplied to the chain circuit systems 222-1, 222-2. Supplying the switching pilot signal 225 to the chain circuit systems 222-1, 222-2 can allow the degradation to be measured. If the pilot signal 225 is switched between a high value and a low value, then the pilot signal 225 can be referred to as the switching pilot signal 225, or if the pilot signal 225 maintains a constant value (e.g., is not switched between a high value and a low value), then the pilot signal 225 can be referred to as the static pilot signal 225.

[0044] The chain circuit system 222-1 can be equivalent to the chain circuit system 222-2. The chain circuit system 222-1 and the chain circuit system 222-2 can be different examples of the same chain circuit system. The chain circuit systems 222-1, 222-2 include logic units. The logic units can include flip-flops, latches, level shifters, and / or logic gates (e.g., gate 223), as well as other possible logic units. The chain circuit systems 222-1, 222-2 can include NOT gates, AND gates, OR gates, and / or buffer gates, as well as other types of logic gates. However, the chain circuit systems 222-1, 222-2 can include other logic gates such as flip-flops and latches, etc.

[0045] The gates 223 can be linked. For example, the output of gate 223-1 is provided as the input of gate 223-2, the output of gate 223-2 is provided as the input of gate 223-3, the output of gate 223-3 is provided as the input of gate 223-4, and the output of gate 223-4 is provided as the input of gate 223-5. The output of gate 223-5 can be the aging signal 226. The output of gate 223-6 is provided as the input of gate 223-7, the output of gate 223-7 is provided as the input of gate 223-8, the output of gate 223-8 is provided as the input of gate 223-9, and the output of gate 223-9 is provided as the input of gate 223-10. The output of gate 223-10 can be the reference signal 227.

[0046] Continuously powering the chained circuit system 222-1, periodically powering the chained circuit system 222-2, and providing a switching pilot signal to the chained circuit system 222-1 and / or the chained circuit system 222-2 as necessary can cause the chained circuit system 222-1 to age in a different manner than the chained circuit system 222-2. For example, the chained circuit system 222-1 can continuously receive power to follow the power scheme of the system (e.g., the memory subsystem). When the system receives power, the chained circuit system 222-1 can receive power, and when the system does not receive power, the chained circuit system 222-1 can refrain from receiving power. Powering the chained circuit system 222-1 according to the power scheme of the system can cause the chained circuit system 222-1 to age at the same or a similar rate as the system. In various examples, the chained circuit system 222-1 can receive power according to the power scheme of a portion of the system. The portion of the system can include the devices of the system and / or the circuitry of the system. For example, if the decoding circuitry of the system receives power or if the memory devices of the system receive power, then the chained circuit system 222-1 can receive power.

[0047] Because the chained circuit system 222-2 does not follow the power scheme of the system and / or because the switching pilot signal 225 is provided to the chained circuit system 222-1 and / or the chained circuit system 222-2, the chained circuit system 222-2 can age in a different manner than the chained circuit system 222-1. For example, the chained circuit system 222-2 cannot receive power until it is determined to measure the degradation of the chained circuit system 222-1 to determine the degradation of the system. The chained circuit system 222-2 can receive power to generate a reference signal 227. Once the reference signal 227 is generated and / or measured, the chained circuit system 222-2 can be powered off.

[0048] The aging signal 226 can be referred to as "aging" because the aging signal 226 is generated by the chained circuit system 222-1 that reflects the aging of the system and / or a portion of the system. The reference signal 227 is referred to as "reference" because the reference signal 227 is generated by the chained circuit system 222-2 that reflects the original state of the system or a system state that is younger than the actual age of the system. As used herein, the age of the system can refer to the length of time the system has been used, the intensity of use, and / or the degradation the system has experienced due to the use of the system and / or the operating conditions of the system. The operating conditions of the system can include the temperature and / or voltage of the system when the system is utilized. When the system is utilized at a higher temperature or a specific voltage, the aging of the system can be greatly accelerated. For example, a system utilized at a high temperature may experience greater degradation compared to a system utilized at a lower temperature.

[0049] Compared to a system that has been utilized for a relatively long duration, the system of a newly manufactured product may experience a greater rate or speed of degradation. For example, as the system is utilized, the rate of degradation experienced by the system may slow down. To address the faster aging of new products, the aging monitor 212 may generate the reference signal 227 more frequently than the aging monitor of the aging system.

[0050] Figure 3 A block diagram illustrating various aging monitors 312-1, 312-2 coupled to multiple measurement circuit systems 336-1, 336-2 according to some embodiments of the present disclosure. The aging monitor 312-1 may include chain circuit systems 322-1, 322-2, a multiplexer (MUX) 331, and a NOT gate 332. Although the MUX 331 is shown external to the aging monitor 312-1, the MUX 331 may also be implemented inside the aging monitor 312-1. The aging monitor 312-2 includes chain circuit systems 322-3, 322-4. The aging monitor 312-1 may provide a reference signal and an aging signal to the measurement circuit system 336-1. The aging monitor 312-2 provides a reference signal and an aging signal to the measurement circuit system 336-2. In various examples, a single signal may be provided to the measurement circuit system 336-1. For example, an additional MUX (not shown) may receive the reference signal and the aging signal, and may provide either the reference signal or the aging signal to the measurement circuit system. The additional MUX may select the reference signal or the aging signal based on the signal selected by the MUX 331.

[0051] The MUX 331 and the inverter 332 may be used to place the chain circuit system 322-1 or the chain circuit system 322-2 in an oscillation mode. The frequency of the chain circuit system 322-1 and different frequencies of the chain circuit system 322-2 may be measured based on the MUX 331 and / or one or more additional MUXes (not shown). After measuring the frequencies of the chain circuit systems 322-1, 322-2, the frequencies of the chain circuit systems 322-1 and 322-2 may be used to evaluate the aging of the chain circuit system 322-1. For example, the aging of the chain circuit system 322-1 may be calculated by dividing the frequencies of the chain circuit systems 322-1, 322-2.

[0052] Although a single monitor 336-1 is shown to measure the frequencies of the chain circuit systems 322-1, 322-2, other instances may utilize two monitors (e.g., monitor 336-1 and a different monitor not shown) to simultaneously measure the two frequencies (e.g., the frequency of the chain circuit system 322-1 and the frequency of the chain circuit system 322-2). For example, the first monitor may measure the frequency of the chain circuit system 322-1, and the second monitor may relatively simultaneously measure the frequency of the chain circuit system 322-2. InFigure 3 In an example, in view of using a single monitor 336-1, the frequencies of the chained circuit systems 322-1 and 322-2 can be measured sequentially. An additional MUX (not shown) can be used to measure the frequencies of the chained circuit systems 322-1 and 322-2 sequentially.

[0053] The aging monitor 312-2 does not utilize a MUX because the phase detector 336-2 measures the phase shift between the chained circuit system 322-3 and the chained circuit system 322-4 (e.g., the difference in the total chain delay). The pilot signal can enter the chained circuit systems 322-3 and 322-4 synchronously and can leave the chained circuit systems 322-3 and 322-4 with a phase shift as a result of the aging of the chained circuit system 322-3. The measurement of the phase shift can be used to determine the aging of the circuit system 322-3.

[0054] In various examples, the degradation of the system can be measured and / or generated by measuring the degradation of the chained circuit systems 322-1 and 322-3. The timing degradation can be measured by measuring the circuit systems 336-1 and 336-2. As used herein, the timing degradation is the timing difference of the system compared to the original system. The timing degradation can be expressed as the slower propagation of the signal through the multiple gates of the system compared to the propagation of the signal through the multiple gates of the original system. The frequency ratio measurement performed by the measurement circuit system 336-1 (e.g., the frequency monitor) can be used to measure the timing degradation. The phase measurement performed by the measurement circuit system 336-2 (e.g., the phase detector) can also be used to measure the timing degradation.

[0055] To measure the frequency ratio using the measurement circuit system 336-1, the chained circuit systems 322-1 and 322-2 can be made to oscillate by themselves by closing the loops of the chained circuit systems 322-1 and 322-2. The loops of the chained circuit systems 322-1 and 322-2 can include the output lines 333-1 and 333-2 and the line 335. The loop can be closed using the MUX 331. For example, the MUX 331 can couple the output lines 333-1 and 333-2 to the line 335. Before providing the signals provided by the lines 333-1 and 333-2 to the line 335, the output of the MUX 331 can be inverted using the NOT gate 332. The NOT gate 332 can invert the output of the MUX 331 to place the chained circuit systems 332-1 and 332-2 in self-oscillation. If the chained circuit systems 332-1 and 332-2 have already inverted the signal, the NOT gate 332 can be omitted.

[0056] The MUX 331 can couple the line providing the pilot signal, the line 333-1 providing the aging signal of the chained circuit system 322-1, and the line 333-2 providing the reference signal of the chained circuit system 322-2 to the line 335.

[0057] The frequencies of the chain circuit systems 322-1 and 322-2 can be measured by the measurement circuit system 336-1. The measurement circuit system 336-1 can calculate degradation based on two frequency ratios generated from the frequencies of the chain circuit systems 322-1 and 322-2. The measurement circuit system 336-1 can utilize the chain circuit system 322-1 to generate a first frequency ratio and utilize the chain circuit system 322-2 to generate a second frequency ratio. In some examples, the measurement circuit system 336-1 can generate frequencies, and different circuit systems (e.g., an aging control circuit system) can generate frequency ratios and generate degradation based on the ratios. The benefit of performing frequency ratio measurements is that frequency ratio measurements can be more accurate in measuring degradation and more robust than performing phase measurements.

[0058] However, powering the chain circuit system 322-2 (e.g., a reference circuit system) for performing frequency ratio measurements can take longer than powering the chain circuit system 322-4 for performing phase measurements, which can cause the chain circuit system 322-2 to age faster than the chain circuit system 322-4. Performing frequency ratio measurements can also include subjecting the chain circuit system 322-2 to a higher oscillation frequency than the chain circuit system 322-4, which can also cause the chain circuit system 322-2 to experience faster degradation than the chain circuit system 322-4. Additionally, performing frequency ratio measurements can also include calculating frequency ratios, which can utilize circuit systems in the measurement circuit system 336-1 that are not utilized by the measurement circuit system 336-2, resulting in a higher manufacturing cost for the measurement circuit system 336-1 and causing the measurement circuit system 336-1 to consume more power than the measurement circuit system 336-2.

[0059] The phases of the chain circuit systems 322-3 and 322-4 can be measured by the measurement circuit system 336-2. The measurement circuit system 336-2 can measure the timing difference between the chain circuit systems 322-3 and 322-4 based on the phases of the chain circuit systems 322-3 and 322-4. Pilot signals propagating through the chain circuit system 322-3 (e.g., an aging circuit system) and the chain circuit system 322-4 (e.g., a reference circuit system) can arrive at the measurement circuit system 336-2 with different phases. The measurement circuit system 336-2 measures the different phases and / or the difference between the phases.

[0060] The measurement circuitry 336-2 can directly measure the phase of the chained circuitry 322-3, 322-4 via a high-speed clock, or can apply circuitry similar to a delay-locked loop (DLL), which is a self-adjusting circuitry and can count taps added to a zero phase. The DLL can align the phase by adding some delays to an earlier line. These delays are buffers that can be referred to as taps. The buffers can be of the same type, called the same weight, or of different types. Using buffers of different types (e.g., different weights) can indicate different delays. The DLL (e.g., DLL control) can MUX in and out as many such delays as needed to balance the two phases. Once the two phases are balanced, the DLL can determine the phase shift by counting such delays (taps) and their types (weights).

[0061] Measuring the phase of the chained circuitry 322-3, 322-4 can include powering the chained circuitry 322-4 for a shorter time than the chained circuitry 322-2, which can cause the chained circuitry 322-4 to age more slowly than the chained circuitry 322-2. Measuring the phase of the chained circuitry 332-3, 322-4 can include powering the chained circuitry 322-4 for a shorter duration than the chained circuitry 322-2, which can cause the chained circuitry 322-4 to age more slowly than the chained circuitry 322-2. Measuring the phase of the chained circuitry 322-3, 322-4 to calculate the degradation of the chained circuitry 322-3 can be done without using the firmware of a circuitry with mathematical capabilities, which can make the measurement circuitry 336-2 less expensive and can cause the measurement circuitry 336-2 to consume less power than the measurement circuitry 336-1. However, the accuracy of the measurement circuitry 336-2 may be lower than that of the measurement circuitry 336-1. Creating a high-resolution measurement circuitry 336-2 (e.g., a high-resolution phase detector) may be more complex than the measurement circuitry 336-1 (e.g., a frequency monitor).

[0062] Figure 4 A block diagram illustrating a plurality of aging monitors 412-1, 412-2, 412-3, 412-4 coupled to a measurement circuitry 436 according to some embodiments of the present disclosure. The aging monitors 412-1, 412-2, 412-3, 412-4 can be referred to as the aging monitor 412. Each of the aging monitors 412 can correspond to Figure 2 the aging monitor 212 or Figure 3 the aging monitors 312-1, 312-2 of

[0063] The aging monitor 412 can receive several pilot signals 425-1, 425-2, 425-3, 425-4. For example, the aging monitor 412-1 can receive the pilot signal 425-1, the aging monitor 412-2 can receive the pilot signal 425-2, the aging monitor 412-3 can receive the pilot signal 425-3, and the aging monitor 412-4 can receive the pilot signal 425-4. The pilot signals 425-1, 425-2, 425-3, 425-4 can be referred to as the pilot signal 425.

[0064] Each of the pilot signals 425 can be different from the other pilot signals. For example, in addition to other possible differences between the pilot signals 425, the pilot signal 425-1 can be a fast signal, the pilot signal 425-2 can be a slow signal, the pilot signal 425-3 can be a high duty cycle signal, and the pilot signal 425-4 can be a low duty cycle signal. The pilot signal 425-1 and the pilot signal 425-2 can be fast or slow respectively as compared to a threshold and / or as compared to each other. For example, the pilot signal 425-1 can be fast as compared to the pilot signal 425-2. The fast signal and the slow signal can refer to the frequency of the signal being fast or slow.

[0065] As previously described, the frequency of a signal can be fast or slow relative to each other or a threshold. The duty cycle is a measure of asymmetry. A symmetric wave can have a 50% duty cycle (e.g., the duration of the upper wave divided by the wave period). A high duty cycle can indicate that the upper wave (e.g., 1 in the digital world) is longer than 0. A low duty cycle can indicate that the upper wave is shorter than 0. The high duty cycle and the low duty cycle can activate a reference circuit system. For example, the upper wave can activate some transistors, and the lower wave can activate other transistors. A 50% duty cycle can activate all transistors in the same proportion. The high duty cycle and the low duty cycle can activate one transistor or another group of transistors for a longer time than other transistors. Most systems switch asymmetrically and are used continuously. When some circuit systems stop, it disconnects some transistors and closes other transistors. The duration of transistor operation can be very different. What is happening in a circuit system that does not always switch and does not switch symmetrically can be determined based on having different duty cycle measurements.

[0066] The duty cycle can be higher or lower relative to each other or relative to a threshold. The differences shown between the pilot signals 425 (e.g., fast signal and slow signal, high duty cycle and low duty cycle) are illustrative. Other differences can be applied to the pilot signals 425.

[0067] The aging mechanism can include channel hot carriers (CHC) (e.g., hot electrons) and negative bias temperature instability (NBTI) and / or electromigration, as well as other examples of aging mechanisms. The examples of aging mechanisms are given as illustrative and not restrictive. Other examples of aging mechanisms can be implemented with respect to the examples provided herein.

[0068] The pilot signal 425 can be selected based on the monitored aging mechanisms. For example, a first aging monitor and a first pilot signal can be used to simulate the degradation experienced by the hot carriers (CHC) of the system, while a second aging monitor and a second pilot signal are used to simulate the degradation experienced due to negative bias temperature instability (NBTI). The first pilot signal can be generated based on the characteristics of the CHC, and the second pilot signal can be generated to address the characteristics of NBTI. Although the examples provided herein are given in terms of the characteristics of the CHC and the characteristics of NBTI, other characteristics can be utilized.

[0069] The pilot signal 425, monitor connections, and the cells used in the monitors can also be selected based on the power domain (e.g., power scheme variance), clock domain (e.g., clock frequency and activity variance), dominant cell type (e.g., cell voltage threshold or cell channel length), topology (e.g., location on the die), and / or temperature, as well as other characteristics utilized in the system. The clock domain can be addressed by pilot signals of different frequencies. To address the power and voltage domains, the monitors can be powered with an appropriate domain. To address cells of different voltage thresholds and channel lengths, monitors can be created from cells representing the thresholds and lengths. The pilot signal 425 can be selected based on different locations on the die of the system (e.g., hot regions versus cold regions). For example, a first location on the die of the system can experience a temperature above a threshold, while a second location on the die experiences a temperature below the threshold. A first pilot signal can be selected such that the aging monitor (e.g., the aging circuitry of the aging monitor) degrades in a manner consistent with the degradation experienced by the circuitry in the first location.

[0070] Due to the infrequent measurements made by the measurement circuitry 436, a single measurement circuitry 436 can be utilized to service the aging monitors 412. In various examples, each of the aging monitors 412 can provide an output signal to a different measurement circuitry 436, or any two or more of the aging monitors 412 can provide an output signal to the measurement circuitry 436.

[0071] Figure 5Block diagram of a plurality of aging monitors 512-1, 512-2, …, 512-N that receive power from a plurality of voltage regulators 528-1, 528-2, …, 528-N according to some embodiments of the present disclosure. The aging monitors 512-1, 512-2, …, 512-N may be referred to as aging monitor 512. The voltage regulators 528-1, 528-2, …, 528-N may be referred to as voltage regulator 528. The voltage regulator 528 may supply power to the aging monitor 512 and / or monitor-specific devices and / or systems. For example, the voltage regulator 528-1 may supply power to the aging monitor 512-1, the voltage regulator 528-2 may supply power to the aging monitor 512-2, …, and the voltage regulator 528-N may supply power to the aging monitor 512-N. Although examples are provided in the context of the voltage domain, Figure 5 the examples Figure 5 are equally applicable to the clock domain, the power domain, and the regional domain, as well as other domains.

[0072] Each of the voltage regulators 528 may supply power with a specific voltage to the aging monitor 512. For example, the voltage regulator 528-1 may supply power with a first voltage to the aging monitor 512-1, while the voltage regulator 528-2 supplies power with a second voltage to the aging monitor 512-2.

[0073] Each of the aging monitors 512 may generate an aging signal and a reference signal. The aging signal and the reference signal may be compared with each other to measure the degradation of the aging circuitry of the aging monitor 512. The measured degradation may be provided to a controller of a system such as the CPU 504.

[0074] After determining some timing degradation, the system (e.g., the CPU 504) may apply a corrective action to extend the production life of the system or restore the degraded performance of the system. For example, the clock of the system may be scaled down (e.g., clock scaling 551) to mimic the aging timing of the system. Scaling down the clock may extend the error-free operation of the system (e.g., the circuitry of the system) for an additional duration.

[0075] A boosted voltage may be set to improve the degraded performance of the system. The voltage may be boosted using voltage scaling 552. Boosting the voltage may also accelerate the aging of the system. Boosting the voltage may result in the restoration of performance within an additional duration.

[0076] In some instances, to counteract system degradation, the system may be set to a lower voltage from when the system is first utilized. Utilizing the system with a lower voltage may extend the life of the system. Both clock and voltage scaling can be used to achieve the desired performance of the system and / or extend the life of the system. Changes made to the clock (e.g., clock scaling 551) and / or voltage (e.g., voltage scaling) may be reflected in the power supplied from the voltage regulator 528 to the aging monitor 512 and / or the system.

[0077] Figure 6 is a flowchart corresponding to a method 680 for implementing a degradation correction circuit system according to some embodiments of the present disclosure. Method 680 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 680 is executed by Figure 1 the aging control circuit system 108. Although shown in a particular sequence or order, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated process may be executed in a different order, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0078] Method 680 includes controlling a degradation correction circuit system. At operation 681, power and a first signal may be continuously supplied to Figure 2 a first circuit system 222-1 to produce a first output. The first circuit system may reflect the aging and / or degradation experienced by the system and / or a part of the system. At operation 682, power and a second signal may be periodically supplied to Figure 2 a second circuit system 222-2 to produce a second output. The first circuit system and the second circuit system are different examples of the same circuit system. The first circuit system and the second circuit system may be the same circuit system because both the first circuit system and the first circuit system include the same logic gates. For example, the first circuit system may include an AND gate, and the second circuit system may also include an AND gate. The second circuit system may be a reference circuit system. The first circuit system and the second circuit system may be included in Figure 2 the aging monitor 212.

[0079] At operation 683, the degradation of the first circuit system may be measured by comparing the first output of the first circuit system with the second output of the second circuit system. The first output may be the first signal, and the second output may be the second signal. The first output may be an aging signal, and the second output may be a reference signal. Figure 1The measurement circuit system 136 can measure the first signal and the second signal, and / or can compare the first signal with the second signal to measure the degradation of the first circuit system. Since the power curve of the first circuit system can reflect the power curve of the system and / or a part of the system, the degradation of the first circuit system can reflect the degradation of the system.

[0080] At operation 684, in response to measuring the degradation of the first circuit system, the degradation of the first circuit system can be compared with a threshold. Figure 1 The aging control circuit system 108 can compare the degradation (e.g., the measurement of degradation) with a threshold. The measurement circuit system can provide the degradation measurement to the aging control circuit system.

[0081] At operation 685, in response to determining that the degradation is greater than the threshold, a corrective action can be performed based on the degradation of the first circuit system to limit the impact of the degradation of the system. The aging control circuit system can perform the corrective action.

[0082] In various examples, power can be provided to the second circuit system while power is provided to the first circuit system to generate a second output. Most of the time, power can be provided to the first circuit system and not provided to the second circuit system. When a degradation measurement is requested, power can be provided to the second circuit system. The first output can be continuously generated, while the second output is generated when the second circuit system receives power. If the first circuit system and the second circuit system receive power simultaneously to generate the first output and the second output simultaneously, then a degradation measurement can be generated.

[0083] The signals received by the first circuit system and the second circuit system can be the same signal. For example, the first signal and the second signal can be the same signal called a pilot signal. In various instances, the second signal and the first signal can be the inverse signals of the signals provided by the control circuit system to the first circuit system and the second circuit system. For example, the control circuit system can provide a pilot signal. A NOT gate can be used to invert the pilot signal to provide the inverted pilot signal to the first circuit system and the second circuit system.

[0084] In response to determining to measure the degradation of the first circuit system, power can be provided to the second circuit system. The second circuit system can remain unpowered until it is determined to measure the degradation of the first circuit system. In response to generating the second output, the aging control circuit system can avoid providing power to the second circuit system. After the second circuit system generates the second output, power can be not given to the second circuit system. Not giving power to the second circuit system before requesting the second output and after generating the second output can ensure that the second circuit system remains unpowered most of the time, which can limit the impact of aging compared to the first circuit system that remains continuously powered.

[0085] In various examples, the first circuit system may include a first plurality of logic units, and the second circuit system includes a second plurality of logic units. The logic units may be, for example, logic gates, and other possible logic units. The first plurality of logic units and the second plurality of logic units may be different examples of the same plurality of logic units. For example, the first plurality of logic units may include a first AND gate, and the second plurality of logic units includes a second AND gate and other types of logic units, such as flip-flops, latches, and registers. The logic units may be linked such that the output of one of the logic units is the input of the next logic unit. The logic units may be linked to produce an output. For example, the first plurality of logic units are linked to produce a first output, and the second plurality of logic units are linked to produce a second output.

[0086] In various examples, the aging monitor may include a first circuit system including a first chain of logic units and a second circuit system including a second chain of logic units. The first chain of logic units and the second chain of logic units are the same chain of logic units. The first circuit system and the second circuit system may be different examples of the same chain of logic units. A control circuit system may be coupled to the first circuit system and the second circuit system. The control circuit system may provide power and signals to the first circuit system to generate an aging signal. Power may be continuously provided to the first circuit system. Power and signals may be discontinuously provided to the second circuit system to generate a reference signal. Power is provided to the second circuit system based on determining the degradation of the first circuit system. Signals may be continuously provided to the first circuit system and the second circuit system.

[0087] In response to measuring the degradation of the first circuit system, power may not be given to the second circuit system. For example, the controller may avoid providing power to the second circuit system in response to measuring the degradation of the first circuit system.

[0088] The system may further include a measurement circuit system coupled to the first circuit system and the second circuit system. The measurement circuit system may compare the aging signal with the reference signal. The measurement circuit system may use the comparison of the aging signal with the reference signal to measure the degradation of the first circuit system compared to the second circuit system.

[0089] In various examples, the first circuit system and the second circuit system may be made to oscillate by themselves by closing the loop via a MUX, another gate, and / or in other ways. The loop may include coupling a first output line of the first circuit system and a second output line of the second circuit system to an input line that provides signals to the first circuit system and the second circuit system. For example, the aging monitor may include a MUX and a NOT gate. The MUX and the NOT gate may also be implemented outside the aging monitor. The MUX may be implemented outside the aging monitor, while the NOT gate is implemented inside the aging monitor. The NOT gate is further configured to receive the output of the MUX and invert the output of the MUX to produce a signal that is provided to the first circuit system and the second circuit system.

[0090] The measurement circuitry may compare the aging signal with a reference signal to produce a frequency ratio measurement. The measurement circuitry may compare the aging signal with a reference signal to measure the timing difference between the aging signal and the reference signal. The measurement circuitry may utilize the timing difference to produce a degradation measurement. The system may also include one or more voltage regulators to provide power to a second circuitry based on receipt of a reference enable signal.

[0091] In various examples, the system may include a device that includes a first aging monitor that includes a first reference circuitry and a first aging circuitry. The device may also include a second aging monitor that includes a second reference circuitry and a second aging circuitry. The control circuitry may provide a first signal to the first aging monitor to produce a first output using the first reference circuitry and a second output using the first aging circuitry. The control circuitry may provide a second signal to the second aging monitor to produce a third output using the second reference circuitry and a fourth output using the second aging circuitry. The measurement circuitry may compare the first output of the first aging monitor with the second output to determine a first degradation measurement of a first portion of the device. The measurement circuitry may compare the third output of the second aging monitor with the fourth output to determine a second degradation measurement of a second portion of the device.

[0092] The control circuitry may utilize the first degradation measurement to take corrective action to mitigate the effects of degradation of the first portion of the device. The control circuitry may utilize the second degradation measurement to take corrective action to mitigate the effects of degradation of the second portion of the device.

[0093] The first signal and the second signal may be different pilot signals. The first signal and the second signal may be selected to identify degradation of a particular aspect of the device. For example, the first signal and the second signal may be selected based on, for example, the timing degradation of the device and the voltage drift of the device, respectively. Different pilot signals may be provided to the first aging monitor and the second aging monitor to address different aging effects of the first portion of the device and the second portion of the device, respectively.

[0094] The device may also include a power circuitry configured to provide a first power to the first aging monitor and a second power to the second aging monitor, where the first power is provided to the first portion of the device and the second power is provided to the second portion of the device to mimic the power provided to the first portion of the device and the second portion of the device.

[0095] The control circuitry can perform a first corrective action in response to a first degradation measurement to extend the life of a first portion of the device or restore the degraded performance of the first portion of the device. The control circuitry can perform a second corrective action in response to a second degradation measurement to extend the life of a second portion of the device or restore the degraded performance of the second portion of the device.

[0096] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. For example, Figure 7 illustrates an example machine of computer system 790, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 790 may correspond to a host system (e.g., Figure 1 host system 102), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 103), or can be used to execute the operations of a controller (e.g., execute an operating system to perform operations corresponding to Figure 1 aging control circuitry 108). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The computer can operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0097] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0098] Example computer system 790 includes a processing device 791, a main memory 793 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 797 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 798, which communicate with each other via a bus 796.

[0099] The processing device 791 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 791 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 791 is configured to execute instructions 792 for performing the operations and steps discussed herein. The computer system 790 can further include a network interface device 794 for communicating via a network 795.

[0100] The data storage system 798 can include a machine-readable storage medium 799 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 792 or software embodying any one or more of the methods or functions described herein. During execution of the instructions 792 by the computer system 790, the instructions 792 can also reside, in whole or at least in part, within the main memory 793 and / or within the processing device 791, which also constitutes a machine-readable storage medium. The machine-readable storage medium 799, the data storage system 798, and / or the main memory 793 can correspond to Figure 1 the memory subsystem 103.

[0101] In one embodiment, the instructions 792 include instructions for implementing the functionality corresponding to an aging control circuit system (e.g., Figure 1 the aging control circuit system 108). Although the machine-readable storage medium 799 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for a machine to execute and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0102] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0103] However, it should be borne in mind that all of these terms and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other physical quantities similarly represented within the computer system memory or registers or other such information storage systems.

[0104] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0105] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will appear as set forth in the description below. In addition, the present disclosure has not been described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0106] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read-only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0107] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for implementing a degradation correction circuit system, comprising: continuously supplying power and a first signal (225) to a first circuit system (222-1, 322-1, 322-3) to generate a first output (226); periodically supplying power and a second signal (225) to a second circuit system (222-2, 322-3, 322-4) to generate a second output (227), wherein the first circuit system and the second circuit system are different examples of the same circuit system; measuring the degradation of the first circuit system by comparing the first output of the first circuit system with the second output of the second circuit system; comparing the degradation of the first circuit system with a threshold value in response to measuring the degradation of the first circuit system; and performing a correction action based on the degradation of the first circuit system to limit the impact of the degradation of the system in response to determining that the degradation is greater than the threshold value.

2. The method according to claim 1, further comprising supplying power to the second circuit system while supplying power to the first circuit system to generate the second output.

3. The method according to claim 1, wherein the first signal and the second signal are the same signal (225).

4. The method according to claim 1, wherein the second signal and the first signal are inverse signals of the signals provided by a control circuit system to the first circuit system and the second circuit system.

5. The method according to any one of claims 1 to 4, further comprising: supplying power to the second circuit system in response to determining to measure the degradation of the first circuit system; and avoiding supplying power to the second circuit system in response to generating the second output.

6. The method according to any one of claims 1 to 4, wherein: the first circuit system includes a first plurality of logic units (223-1, 223-2, 223-3, 223-4, 223-5), and the second circuit system includes a second plurality of logic units (223-6, 223-7, 223-8, 223-9, 223-10), the first plurality of logic units and the second plurality of logic units are different examples of the same plurality of logic units, and the first plurality of logic units are linked to generate the first output, and the second plurality of logic units are linked to generate the second output.

7. An apparatus for implementing a degradation correction circuit system, comprising: a first circuit system (222-1, 322-1, 322-3), which includes a first logic unit chain (223-1, 223-2, 223-3, 223-4, 223-5); a second circuit system (222-2, 322-2, 322-4), which includes a second logic unit chain (223-6, 223-7, 223-8, 223-9, 223-10), wherein the first logic unit chain and the second logic unit chain are the same logic unit chain; A control circuit system (108) coupled to the first circuit system and the second circuit system and configured to: Provide power and a signal (225) to the first circuit system to generate an aging signal (226); Provide power and the signal to the second circuit system to generate a reference signal (227), wherein power is provided to the second circuit system based on determining degradation of the first circuit system, and wherein the signal is continuously provided to the first circuit system and the second circuit system; And Avoid providing power to the second circuit system in response to measuring the degradation of the first circuit system; and A measurement circuit system (136, 336-1, 336-2, 436) coupled to the first circuit system and the second circuit system and configured to: Compare the aging signal with the reference signal; and Use the comparison of the aging signal with the reference signal to measure the degradation of the first circuit system compared to the second circuit system.

8. The apparatus according to claim 7, wherein the first circuit system and the second circuit system are made to oscillate self-excitedly by closing a loop via a gate (331).

9. The apparatus according to claim 7, wherein the first circuit system and the second circuit system are made to oscillate self-excitedly by closing the loop via a gate (331), wherein the loop includes coupling a first output line (331-1) of the first circuit system and a second output line (331-2) of the second circuit system to an input line (335) that provides the signal to the first circuit system and the second circuit system.

10. The apparatus according to any one of claims 7 to 9, wherein the measurement circuit system is further configured to compare the aging signal with the reference signal to produce a frequency ratio measurement.

11. The apparatus according to any one of claims 7 to 9, wherein the measurement circuit system is further configured to: Compare the aging signal with the reference signal to measure a timing difference between the aging signal and the reference signal; and Utilize the timing difference to produce a degradation measurement.

12. The apparatus according to any one of claims 7 to 9, further comprising a voltage regulator (228, 328-1, 328-2, 528-1, 528-2, 528-N) configured to provide power to the second circuit system based on receipt of a reference enable signal (224).

13. An apparatus for implementing a degradation correction circuit system, comprising: A first aging monitor (112, 212, 312-1, 312-2, 412-1, 412-2, 412-3, 412-4, 512-1, 512-2, 512-N) including a first reference circuit system (222-2, 322-2, 322-4) and a first aging circuit system (222-1, 322-1, 322-3); A second aging monitor (112, 212, 312-1, 312-2, 412-1, 412-2, 412-3, 412-4, 512-1, 512-2, 512-N), which includes a second reference circuit system (222-2, 322-2, 322-4) and a second aging circuit system (222-1, 322-1, 322-3); A control circuit system (108), which is coupled to the first aging monitor and the second aging circuit system and is configured to monitor: Provide a first signal to the first aging monitor to generate a first output (226) using the first reference circuit system and a second output (227) using the first aging circuit system; Provide a second signal to the second aging monitor to generate a third output (226) using the second reference circuit system and a fourth output (227) using the second aging circuit system; A measurement circuit system (136, 336-1, 336-2, 436), which is coupled to the first aging monitor and the second aging monitor and is configured to: Compare the first output of the first aging monitor with the second output to determine a first degradation measurement of the first part of the device; And Compare the third output of the second aging monitor with the fourth output to determine a second degradation measurement of the second part of the device.

14. The device according to claim 13, wherein the first signal and the second signal are different pilot signals, and wherein the different pilot signals are provided to the first aging monitor and the second aging monitor to address different aging effects.

15. The device according to claim 13, further comprising a power circuit system, the power circuit system being configured to provide first power to the first aging monitor and second power to the second aging monitor, wherein the first power is provided to the first part of the device, and the second power is provided to the second part of the device to mimic the power provided to the first part of the device and the second part of the device.

16. The device according to any one of claims 13 to 15, wherein the control circuit system is further configured to: Perform a first correction action in response to the first degradation measurement to extend the life of the first part of the device or restore the degraded performance of the first part of the device; and Perform a second correction action in response to the second degradation measurement to extend the life of the second part of the device or restore the degraded performance of the second part of the device.

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