Bus balance control method and system of three-level PWM inverter

Abstract

The embodiment of the invention discloses a bus balance control method and system for a three-level PWM inverter. The control method comprises the steps of obtaining initial balance state data and initial coefficient data of the inverter; acquiring a compensation voltage value based on the initial balance state data and the initial coefficient data; the modulation wave of the inverter is corrected based on the newest compensation voltage value; the corrected balance state data of the inverter after the modulation wave is corrected and the balance state data change condition of the inverter before and after the modulation wave is corrected are obtained; adjusting the current coefficient data based on the change condition of the balance state data of the inverter before and after the modulation wave correction so as to obtain new coefficient data; and a new compensation voltage value is obtained based on the corrected balance state data of the inverter after the modulation wave is corrected and the new coefficient data, and the modulation wave is corrected again. Dynamic coefficient data can adapt to changes of loads or working conditions, voltage fluctuation or oscillation caused by excessive compensation can be avoided, and stability is improved.

Description

Technical Field

[0001] Multiple embodiments of this specification relate to the field of inverter control technology, and specifically to a bus balance control method and system for a three-level PWM inverter. Background Art

[0002] A three-level PWM (Pulse Width Modulation) inverter is an advanced power electronic device that uses three different levels to generate an AC output voltage. Two bus capacitors are connected in series on the DC bus of the three-level inverter, and the midpoint of the two bus capacitors is connected to the inverter bridge arm. Two sets of switching devices (usually IGBTs or MOSFETs) are used and are respectively connected to the positive and negative terminals of the DC power supply. When the three-level inverter operates, it charges and discharges the positive and negative bus capacitors. By changing the switching time (i.e., pulse width) of each switching device, the magnitude of the output voltage can be controlled, and the desired AC voltage waveform can be synthesized by quickly switching the switching devices in the inverter.

[0003] The imbalance of the DC bus midpoint voltage is an inherent problem of three-level inverters. Due to problems such as uneven loads and control circuit differences, the average value of the current flowing in and out of the midpoint of the bus capacitor is not zero, and the charging and discharging of the positive and negative bus capacitors are asymmetric, which further causes the voltage imbalance across the positive and negative capacitors. Usually, the DC component of the output voltage is very strictly calibrated before the inverter leaves the factory. However, in actual use, due to the difference between the operating environment temperature and the calibration environment temperature, device aging of the inverter, etc., the problem of DC bus midpoint voltage imbalance still occurs. Currently, the general method to solve the bus midpoint voltage balance problem of three-level inverters is to add a balance bridge structure, and the balance bridge charges and discharges between the positive and negative bus capacitors to maintain the bus voltage balance.

[0004] However, adding a balance bridge structure means additional hardware is required, such as switching devices and inductors, which increases the cost and complexity. Summary of the Invention

[0005] Embodiments of this specification provide a bus balance control method and system for a three-level PWM inverter, which convert the originally regarded harmful DC component of the current and the resulting bus imbalance phenomenon into a control signal, and realize automatic bus balance through a negative feedback mechanism by software algorithms without increasing hardware costs.

[0006] The technical solutions are as follows: In a first aspect, embodiments of this specification provide a bus balance control method for a three-level PWM inverter, including: Obtain the initial positive and negative bus voltage difference and / or the initial DC component of the current of the inverter as the initial balance state data, and obtain the corresponding initial coefficient data for the initial balance state data; Obtain the compensation voltage value based on the initial balance state data and the initial coefficient data; Modify the modulation wave of the inverter based on the latest compensation voltage value; Obtain the corrected positive and negative bus voltage difference and / or the corrected DC component of the current of the inverter after the modulation wave is corrected as the corrected balance state data, and obtain the change in the balance state data of the inverter before and after the modulation wave is corrected; Adjust the current coefficient data based on the change in the balance state data of the inverter before and after the modulation wave is corrected to obtain new coefficient data; Obtain a new compensation voltage value based on the corrected balance state data of the inverter after the modulation wave is corrected and the new coefficient data, and return to the step of modifying the modulation wave of the inverter based on the latest compensation voltage value.

[0007] As a preferred solution, the adjusting the current coefficient data based on the change in the balance state data of the inverter before and after the modulation wave is corrected to obtain new coefficient data includes: When the balance state data of the inverter before and after the modulation wave is corrected is both positive or both negative, increase the current coefficient data to obtain new coefficient data; When the balance state data of the inverter before and after the modulation wave is corrected is positive and negative, decrease the current coefficient data to obtain new coefficient data.

[0008] As a preferred solution, the balance state data includes the positive and negative bus voltage difference and the DC component of the current; the coefficient data includes a first droop coefficient corresponding to the positive and negative bus voltage difference and a second droop coefficient corresponding to the DC component of the current; the obtaining of the compensation voltage value includes: Obtain a first compensation sub-voltage value based on the first droop coefficient and the positive and negative bus voltage difference, and obtain a second compensation sub-voltage value based on the second droop coefficient and the DC component of the current; Obtain the compensation voltage value based on the first compensation sub-voltage value and the second compensation sub-voltage value.

[0009] As a preferred solution, the obtaining the compensation voltage value based on the first compensation sub-voltage value and the second compensation sub-voltage value includes: Obtain a balance control mode based on the change in the balance state data of the inverter before and after the modulation wave is corrected, and the balance control mode is a dynamic response mode or a steady state mode; Obtain a first weight coefficient corresponding to the positive and negative bus voltage difference and a second weight coefficient corresponding to the DC component of the current based on the type of the balance control mode; Obtain a compensation voltage value based on a first weight coefficient, a second weight coefficient, a first compensated sub-voltage value, and a second compensated sub-voltage value; Among them, the first weight coefficient corresponding to the dynamic response mode is less than the second weight coefficient, and the first weight coefficient corresponding to the steady state mode is greater than the second weight coefficient.

[0010] As a preferred solution, the obtaining of the balance control mode based on the change situation of the balance state data of the inverter before and after the modulation wave is corrected includes: When the change amplitude of the positive and negative bus voltage differences of the inverter before and after the modulation wave correction continuously exceeds a first determination value for a first preset time, or the change amplitude of the DC component of the current of the inverter before and after the modulation wave correction continuously exceeds a second determination value for a first preset time, the balance control mode is the dynamic response mode; When the change amplitude of the positive and negative bus voltage differences of the inverter before and after the modulation wave correction continuously is less than or equal to the first determination value for a second preset time, or the change amplitude of the DC component of the current of the inverter before and after the modulation wave correction continuously is less than or equal to the second determination value for a second preset time, the balance control mode is the steady state mode.

[0011] By adopting the above technical solution, when the change amplitude is greater than the determination value, the balance control mode is not immediately switched, but the overall situation of the change amplitude within a certain time is used as the switching basis, so as to prevent the triple degradation of the stability, efficiency, and reliability of the balance control caused by the frequent switching of the balance control mode.

[0012] As a preferred solution, the obtaining of the first compensated sub-voltage value based on the first droop coefficient and the positive and negative bus voltage differences includes: Obtain the historical data of the positive and negative bus voltage differences; Based on the first droop coefficient, the positive and negative bus voltage differences, and the historical data of the positive and negative bus voltage differences, obtain the first compensated sub-voltage value.

[0013] As a preferred solution, the correcting of the modulation wave of the inverter based on the latest compensated voltage value includes: When the latest compensated voltage value is greater than the limit value, correct the modulation wave of the inverter based on the limit value.

[0014] By adopting the above technical solution, setting the limit value ensures that it does not exceed the carrier amplitude and prevents overmodulation.

[0015] In a second aspect, an embodiment of this specification provides a bus balance control system for a three-level PWM inverter, including: A first obtaining module, which obtains the initial positive and negative bus voltage differences and / or the initial DC component of the current of the inverter as initial balance state data, and obtains initial coefficient data corresponding to the initial balance state data; The first processing module obtains a compensation voltage value based on initial balance state data and initial coefficient data; The correction module corrects the modulation wave of the inverter based on the latest compensation voltage value; The second acquisition module acquires the corrected positive and negative bus voltage differences and / or the corrected DC component of the current of the inverter after the modulation wave is corrected as the corrected balance state data, and acquires the change in the balance state data of the inverter before and after the modulation wave is corrected; The adjustment module adjusts the current coefficient data based on the change in the balance state data of the inverter before and after the modulation wave is corrected to obtain new coefficient data; The second processing module obtains a new compensation voltage value based on the corrected balance state data of the inverter after the modulation wave is corrected and the new coefficient data.

[0016] In a third aspect, an embodiment of this specification provides an electronic device, including a processor and a memory; the processor is connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory to execute the steps described in the first aspect of the above embodiment.

[0017] In a fourth aspect, an embodiment of this specification provides a computer storage medium, which stores multiple instructions, and the instructions are suitable for being loaded and executed by a processor to execute the steps described in the first aspect of the above embodiment.

[0018] The beneficial effects brought by the technical solutions provided by some embodiments of this specification at least include: 1. Deviations in the DC component of the voltage will cause the DC component of the current and the positive and negative bus voltage differences, both of which are the results of this bus imbalance. Proportional control with fixed coefficients easily leads to excessive compensation oscillations. By adjusting the coefficient data according to the change in the balance state data of the inverter before and after correction to obtain dynamic coefficient data to adapt to changes in the load or working conditions, it is also possible to avoid voltage fluctuations or oscillations caused by excessive compensation and improve stability; 2. The inverter using the technical solution of the present invention does not need to additionally add hardware for solving the problem of bus midpoint balance, and does not need to strictly calibrate the DC component of its output voltage during factory production. The inverter will not fail in balance adjustment due to component aging or environmental temperature changes during use; 3. When the load suddenly changes, the change in the switching state of the power device will immediately cause the DC component in the current, while the change in the bus voltage requires the capacitor to charge or discharge, which takes a longer time. At the same time, dual-factor compensation of the bus voltage difference and the DC component of the current is introduced to achieve multi-dimensional coordinated control; 4. By dividing the dynamic response stage and the steady state stage and allocating weights during the bus voltage balance control process, the balance between fast response and high precision is achieved. During the dynamic process, the rapidly changing current may cause immediate damage to the system, while the cumulative impact of voltage deviation is more significant in the steady state and requires more precise control. In the dynamic response stage, the control of the DC component of the current dominates, quickly suppressing the DC current. In the steady state stage, the control of the voltage difference between the positive and negative buses dominates, precisely maintaining the bus balance. The remaining weight is borne by the other control as an auxiliary adjustment to prevent the side effects brought by a single control. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a schematic structural diagram of the architecture for implementing the bus balance control process in the prior art.

[0021] Figure 2 It is a schematic flow diagram of a bus balance control method for a three-level PWM inverter provided by an embodiment of this specification.

[0022] Figure 3 It is a schematic structural diagram of a bus balance control system for a three-level PWM inverter provided by an embodiment of this specification.

[0023] Figure 4 It is a schematic structural diagram of an electronic device provided by an embodiment of this specification. Detailed Embodiments

[0024] The following will clearly and completely describe the technical solutions in the embodiments of this specification in conjunction with the drawings in the embodiments of this specification.

[0025] The terms "first", "second", "third", etc. in the specification, claims and drawings of this specification are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0026] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the described elements without departing from the scope of the content of this specification. Various processes or components may be appropriately omitted, substituted, or added to each example. For example, the described method may be performed in a different order than the described order, and various steps may be added, omitted, or combined. In addition, the features described for some examples may be combined into other examples.

[0027] Referring to Figure 1 as shown, Figure 1 is a schematic diagram of the architecture for implementing the bus balance control process in the prior art. Before the inverter leaves the factory, the DC component of its output voltage is calibrated very strictly so that the DC component of the voltage is 0. And during use, the DC component of the output circuit voltage is detected in real time, and a compensation voltage is added to the modulation wave of the inverter based on this to eliminate the DC component and avoid the imbalance of the bus. When a DC component appears in the output circuit of the inverter after calibration, the DC component can be directly inverted and used as the compensation voltage to be added to the modulation wave, which is equivalent to setting a fixed given value of 0, and the compensation voltage = given value - DC component of the voltage. However, in actual use, due to the difference between the operating environment temperature and the calibration environment temperature, the device aging of the inverter, etc., the above method cannot eliminate the DC component that appears in the output circuit of the inverter. Since the DC impedance of the inductive load is very small, a little DC component of the current will generate a large positive and negative bus power difference, and these power differences will cause the bus voltage to become unbalanced quickly, resulting in the shutdown of the system.

[0028] Therefore, a bus balance control method and system for a three-level PWM inverter are proposed.

[0029] Referring to Figure 2 as shown, Figure 2 is a schematic flow diagram of a balance control method, which may at least include the following steps: Step 102, obtain the initial positive and negative bus voltage differences and / or the initial DC component of the current of the inverter as the initial balance state data, and obtain the initial coefficient data corresponding to the initial balance state data; Step 104, obtain the compensation voltage value based on the initial balance state data and the initial coefficient data; Step 106, correct the modulation wave of the inverter based on the latest compensation voltage value; Step 108, obtain the corrected positive and negative bus voltage differences and / or the corrected DC component of the current of the inverter after the modulation wave is corrected as the corrected balance state data, and obtain the change in the balance state data of the inverter before and after the modulation wave is corrected; Step 110: Adjust the current coefficient data based on the change in the balanced state data of the inverter before and after the modulation wave correction to obtain new coefficient data; Step 112: Obtain a new compensation voltage value based on the corrected balanced state data of the inverter and the new coefficient data after the modulation wave is corrected, and return to the step of correcting the modulation wave of the inverter based on the latest compensation voltage value.

[0030] Illustratively, the positive and negative bus voltage differences are calculated from the sampled data of the positive and negative bus voltages within one modulation wave period, and the DC component of the current is calculated from the sampled data of the output current within one modulation wave period. The positive and negative bus voltage differences can be obtained through a bus voltage sensor (voltage dividing resistor + ADC sampling), and the DC component of the current is extracted through a current sensor and a digital filter. Either the positive and negative bus voltage differences or the DC component of the current can be used as the balanced state data, or both can be used together as the balanced state data. The initial coefficient data is an empirical value obtained through testing. Since the load types are different, it is difficult to calculate an accurate value.

[0031] Exemplarily, if the coefficient data of the positive and negative bus voltage differences is 0.02, that is, when the bus deviation is 50V, the corresponding compensation voltage value is 1V. If the coefficient data of the DC component of the current is 1, that is, when the current deviation is 1A, the corresponding compensation voltage value is 1V.

[0032] Illustratively, the modulation wave of the inverter is corrected according to the compensation voltage value, and then the corrected balanced state data is obtained based on the sampled data within one modulation wave period after correction. The corrected balanced state data is compared with the balanced state data before correction to judge the bus balance control effect, and the coefficient data is adjusted accordingly to improve the balance control quality and efficiency. The compensation voltage value is superimposed on the modulation wave to adjust the duty cycle of the PWM, so that the output voltage waveform of the inverter contains a DC component opposite to the voltage offset caused by the DC component of the current, thereby affecting the midpoint current and changing the charging and discharging conditions of the bus voltage. After multiple corrections of the modulation wave, the inverter bus is finally balanced.

[0033] Explanatorily, the deviation of the DC component of the voltage will cause the DC component of the current and the positive and negative bus voltage differences, both of which are the results of this bus imbalance. The proportional control with a fixed coefficient is prone to excessive compensation oscillation. Adjusting the coefficient data according to the change in the balanced state data of the inverter before and after correction to obtain dynamic coefficient data to adapt to the changes in the load or working conditions can also avoid voltage fluctuations or oscillations caused by excessive compensation and improve stability.

[0034] In an embodiment of this specification, adjusting the current coefficient data based on the change in the balanced state data of the inverter before and after the modulation wave correction to obtain new coefficient data includes: When the balance state data of the inverter before and after the modulation wave correction are both positive or both negative, increase the current coefficient data to obtain new coefficient data; When the balance state data of the inverter before and after the modulation wave correction have different signs, decrease the current coefficient data to obtain new coefficient data.

[0035] Exemplarily, if the bus deviation is 50V before the modulation wave correction, the current coefficient data of the positive and negative bus voltage differences is 0.02, and the compensation voltage value is 1V. After the modulation wave correction, the bus deviation becomes -20V, indicating that the compensation voltage value is too large and overshoot occurs, that is, the coefficient data of the positive and negative bus voltage differences needs to be decreased. The decreasing or increasing method can be a fixed value change or successive multiplication, division, etc.

[0036] In an embodiment of this specification, the balance state data includes the positive and negative bus voltage differences and the DC component of the current; the coefficient data includes a first droop coefficient corresponding to the positive and negative bus voltage differences and a second droop coefficient corresponding to the DC component of the current; the acquisition of the compensation voltage value includes: Obtain a first compensation sub-voltage value based on the first droop coefficient and the positive and negative bus voltage differences, and obtain a second compensation sub-voltage value based on the second droop coefficient and the DC component of the current; Obtain the compensation voltage value based on the first compensation sub-voltage value and the second compensation sub-voltage value.

[0037] Explanatorily, when the load suddenly changes, the switching state change of the power device will immediately cause the DC component in the current, while the change of the bus voltage requires capacitor charging or discharging, which takes a longer time. Therefore, the response speed of the DC component of the current is faster, while the change of the positive and negative bus voltage differences is slower and requires a longer integration effect. In the inverter, if the load suddenly changes and causes a DC component in the current, relying only on the voltage difference adjustment may not be timely enough, or a larger droop coefficient may be required, but this may cause oscillation. By introducing current feedback, adjustment can be made in advance before the voltage difference increases significantly, suppressing the accumulation of the DC component, and thus preventing voltage imbalance earlier. Although they have the same origin, due to the different time constants of the physical processes, different control strategies need to be adopted. At the same time, double-factor compensation of the bus voltage difference and the DC component of the current is introduced to achieve multi-dimensional coordinated control. This time-sharing and hierarchical control mechanism not only ensures the dynamic safety of the system but also achieves high static precision.

[0038] In an embodiment of this specification, obtaining the compensation voltage value based on the first compensation sub-voltage value and the second compensation sub-voltage value includes: Obtain a balance control mode based on the change of the balance state data of the inverter before and after the modulation wave correction, and the balance control mode is a dynamic response mode or a steady state mode; Obtain a first weight coefficient corresponding to the positive and negative bus voltage differences and a second weight coefficient corresponding to the DC component of the current based on the type of the balance control mode; Obtain a compensation voltage value based on a first weight coefficient, a second weight coefficient, a first compensated sub-voltage value, and a second compensated sub-voltage value; Among them, the first weight coefficient corresponding to the dynamic response mode is less than the second weight coefficient, and the first weight coefficient corresponding to the steady state mode is greater than the second weight coefficient.

[0039] Explanatory, in the bus voltage balance control system, the division and weight allocation between the dynamic response stage and the steady state stage are the key to achieving fast response and high-precision balance. When the load suddenly changes, the change in the switching state of the power device will immediately cause a DC component in the current, while the change in the bus voltage requires the capacitor to charge or discharge, which takes a longer time. The difference between the two is essentially an embodiment of the time-scale separation principle. During the dynamic process, the rapidly changing current may cause immediate damage to the system, while the cumulative impact of the voltage deviation is more significant in the steady state and requires more precise control. The DC component control of the current dominates in the dynamic response stage to quickly suppress the DC current, and the control of the positive and negative bus voltage differences dominates in the steady state stage to precisely maintain the bus balance. The remaining weight is borne by the other control as an auxiliary adjustment to prevent the side effects brought by a single control.

[0040] Exemplarily, the first weight coefficient corresponding to the dynamic response mode is 0.3, and the second weight coefficient is 0.7; the first weight coefficient corresponding to the steady state mode is 0.8, and the second weight coefficient is 0.2.

[0041] In an embodiment of the present specification, obtain a balance control mode based on the change of the balance state data of the inverter before and after the modulation wave is corrected, including: When the change amplitude of the positive and negative bus voltage differences of the inverter before and after the modulation wave is corrected continuously exceeds a first determination value for a first preset time, or the change amplitude of the DC component of the current of the inverter before and after the modulation wave is corrected continuously exceeds a second determination value for a first preset time, the balance control mode is the dynamic response mode; When the change amplitude of the positive and negative bus voltage differences of the inverter before and after the modulation wave is corrected continuously is less than or equal to the first determination value for a second preset time, or the change amplitude of the DC component of the current of the inverter before and after the modulation wave is corrected continuously is less than or equal to the second determination value for a second preset time, the balance control mode is the steady state mode.

[0042] Explanatory, when the change amplitude is greater than the determination value, the balance control mode is not immediately switched, but the overall situation of the change amplitude within a certain time is used as the switching basis to prevent the triple degradation of the stability, efficiency, and reliability of the balance control caused by the frequent switching of the balance control mode.

[0043] In an embodiment of the present specification, obtain a first compensated sub-voltage value based on a first droop coefficient and the positive and negative bus voltage differences, including: Obtain historical data of the positive and negative bus voltage differences; Obtain a first compensated sub - voltage value based on the first droop coefficient, the positive and negative bus voltage differences, and the historical data of the positive and negative bus voltage differences.

[0044] Explanatory, integrating historical data over a period of time as an integral term to calculate the first compensated sub - voltage value together, integrating the error over time, gradually eliminating the steady - state error to prevent the final residual static error. The static error refers to the persistent deviation between the actual output and the desired target after the system enters the steady state. The first compensated sub - voltage value = -(the first droop coefficient * the positive and negative bus voltage difference+K * the integral of the historical data of the positive and negative bus voltage differences). Observe the voltage recovery time, adjust the integral time constant K to eliminate the static error within 0.5 seconds. The accumulation of the integral term may cause overshoot or system instability, and K needs to be set reasonably, K = 0.1~0.5×the first droop coefficient.

[0045] In multiple embodiments of this specification, the modulation wave of the inverter is corrected based on the latest compensated voltage value, including: When the latest compensated voltage value is greater than the limit value, the modulation wave of the inverter is corrected based on the limit value.

[0046] Explanatory, setting an appropriate limit value ensures that the compensated voltage value of the balanced control output does not exceed the carrier amplitude, preventing over - modulation.

[0047] The above describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0048] Next, please refer to Figure 3 , Figure 3 which shows a schematic structural diagram of a bus balance control system for a three - level PWM inverter provided by an embodiment of this specification.

[0049] As Figure 3 shown, the bus balance control system 300 includes a first acquisition module 301, a first processing module 302, a correction module 303, a second acquisition module 304, an adjustment module 305, and a second processing module 306.

[0050] The first acquisition module 310 acquires the initial positive and negative bus voltage differences and / or the initial DC component of the current of the inverter as initial balance state data, and acquires the initial coefficient data corresponding to the initial balance state data; The first processing module 302 obtains a compensation voltage value based on the initial balance state data and the initial coefficient data; The correction module 303 corrects the modulation wave of the inverter based on the latest compensation voltage value; The second acquisition module 304 acquires the corrected positive and negative bus voltage differences and / or the corrected DC component of the current of the inverter after the modulation wave is corrected as the corrected balance state data, and acquires the change in the balance state data of the inverter before and after the modulation wave is corrected; The adjustment module 305 adjusts the current coefficient data based on the change in the balance state data of the inverter before and after the modulation wave is corrected to obtain new coefficient data; The second processing module 306 obtains a new compensation voltage value based on the corrected balance state data of the inverter after the modulation wave is corrected and the new coefficient data.

[0051] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. The key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the embodiment of the balance control system, since it is basically similar to the embodiment of the balance control method, the description is relatively simple, and the relevant parts can refer to the partial description of the embodiment of the balance control method.

[0052] Please refer to Figure 4 the schematic structural diagram of an electronic device provided by the embodiment of this specification shown.

[0053] As Figure 4 shown, the electronic device 400 may include: at least one processor 401, at least one network interface 404, a user interface 403, a memory 405, and at least one communication bus 402.

[0054] Among them, the communication bus 402 can be used to realize the connection and communication of the above-mentioned various components.

[0055] Among them, the user interface 403 may include buttons, and the optional user interface may further include a standard wired interface and a wireless interface.

[0056] Among them, the network interface 404 may include, but is not limited to, a Bluetooth module, an NFC module, a Wi-Fi module, etc.

[0057] Among them, the processor 401 may include one or more processing cores. The processor 401 connects various parts within the entire electronic device 400 through various interfaces and lines. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 405, and by calling the data stored in the memory 405, it performs various functions of the electronic device 400 and processes data. Optionally, the processor 401 may be implemented in at least one hardware form of DSP, FPGA, or PLC. The processor 401 may integrate a combination of one or several of CPU, GPU, and modem, etc. Among them, the CPU mainly processes the operating system, user interface, application programs, etc.; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor 401 and may be implemented separately through a single chip.

[0058] Among them, the memory 405 may include RAM and may also include ROM. Optionally, the memory 405 includes a non-transitory computer-readable medium. The memory 405 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 405 may include a program storage area and a data storage area. Among them, the program storage area can store instructions for implementing the operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area can store the data involved in the above-mentioned various method embodiments. Optionally, the memory 405 may also be at least one storage device located far from the aforementioned processor 401. As a computer storage medium, the memory 405 may include an operating system, a network communication module, a user interface module, and a balance control application program. The processor 401 can be used to call the balance control application program stored in the memory 405 and execute the steps of the balance control method mentioned in the foregoing embodiments.

[0059] The embodiments of this specification also provide a computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When they run on a computer or a processor, they cause the computer or the processor to execute one or more steps in the above-mentioned balance control method embodiments. If the various component modules of the above-mentioned electronic device are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0060] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of this specification are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, Digital Versatile Disc (DVD)), or a semiconductor medium (for example, Solid State Disk (SSD)), etc.

[0061] Those of ordinary skill in the art can understand that all or part of the processes in the above embodiments of the method can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above embodiments of each method. The foregoing storage medium includes various media that can store program codes, such as ROM, RAM, magnetic disk, or optical disc. Without conflict, the technical features in this embodiment and the implementation scheme can be combined arbitrarily.

[0062] The above embodiments are only described in the preferred implementation manners of this specification, and do not limit the scope of this specification. Without departing from the design spirit of this specification, various deformations and improvements made by those of ordinary skill in the art to the technical solutions of this specification shall fall within the protection scope determined by the claims of this specification.

Claims

1. A bus balance control method for a three-level PWM inverter, characterized in that, Including: Obtain the initial positive and negative bus voltage difference and / or the initial DC component of the current of the inverter as the initial balance state data, and obtain the initial coefficient data corresponding to the initial balance state data; Obtain the compensation voltage value based on the initial balance state data and the initial coefficient data; Correct the modulation wave of the inverter based on the latest compensation voltage value; Obtain the corrected positive and negative bus voltage difference and / or the corrected DC component of the current of the inverter after the modulation wave is corrected as the corrected balance state data, and obtain the change of the balance state data of the inverter before and after the modulation wave is corrected; Adjust the current coefficient data based on the change of the balance state data of the inverter before and after the modulation wave is corrected to obtain new coefficient data; Obtain a new compensation voltage value based on the corrected balance state data of the inverter after the modulation wave is corrected and the new coefficient data, and return to the step of correcting the modulation wave of the inverter based on the latest compensation voltage value.

2. The bus balance control method of a three-level PWM inverter according to claim 1, characterized in that The adjusting the current coefficient data based on the change of the balance state data of the inverter before and after the modulation wave is corrected to obtain new coefficient data includes: When the balance state data of the inverter before and after the modulation wave is corrected are both positive or both negative, increase the current coefficient data to obtain new coefficient data; When the balance state data of the inverter before and after the modulation wave is corrected are positive and negative, decrease the current coefficient data to obtain new coefficient data.

3. A bus balance control method for a three-level PWM inverter according to claim 2, characterized in that, The balance state data includes the positive and negative bus voltage difference and the DC component of the current; the coefficient data includes the first droop coefficient corresponding to the positive and negative bus voltage difference and the second droop coefficient corresponding to the DC component of the current; The obtaining of the compensation voltage value includes: Obtain the first compensation sub-voltage value based on the first droop coefficient and the positive and negative bus voltage difference, and obtain the second compensation sub-voltage value based on the second droop coefficient and the DC component of the current; Obtain the compensation voltage value based on the first compensation sub-voltage value and the second compensation sub-voltage value.

4. The bus balance control method of a three-level PWM inverter according to claim 3, characterized in that, The obtaining the compensation voltage value based on the first compensation sub-voltage value and the second compensation sub-voltage value includes: Obtain the balance control mode based on the change of the balance state data of the inverter before and after the modulation wave is corrected, and the balance control mode is a dynamic response mode or a steady state mode; Obtain the first weight coefficient corresponding to the positive and negative bus voltage difference and the second weight coefficient corresponding to the DC component of the current based on the type of the balance control mode; Obtain the compensation voltage value based on the first weight coefficient, the second weight coefficient, the first compensation sub-voltage value, and the second compensation sub-voltage value; Wherein, the first weight coefficient corresponding to the dynamic response mode is less than the second weight coefficient, and the first weight coefficient corresponding to the steady state mode is greater than the second weight coefficient.

5. A bus balance control method for a three-level PWM inverter according to claim 4, characterized in that, The obtaining the balance control mode based on the change of the balance state data of the inverter before and after the modulation wave is corrected includes: When the change amplitude of the positive and negative bus voltage difference of the inverter before and after the modulation wave is corrected continuously exceeds the first determination value for more than the first preset time, or the change amplitude of the DC component of the current of the inverter before and after the modulation wave is corrected continuously exceeds the second determination value for more than the first preset time, the balance control mode is the dynamic response mode; When the change amplitude of the positive and negative bus voltage differences of the inverter before and after the modulation wave correction continuously remains less than or equal to the first determination value for more than the second preset time, or when the change amplitude of the DC component of the inverter current before and after the modulation wave correction continuously remains less than or equal to the second determination value for more than the second preset time, the balance control mode is the steady state mode.

6. The bus balance control method of a three-level PWM inverter according to claim 5, characterized in that, The obtaining of the first compensated sub-voltage value based on the first droop coefficient and the positive and negative bus voltage differences includes: Obtaining historical data of the positive and negative bus voltage differences; Obtaining the first compensated sub-voltage value based on the first droop coefficient, the positive and negative bus voltage differences, and the historical data of the positive and negative bus voltage differences.

7. A bus balance control method for a three-level PWM inverter according to claim 1, characterized in that The correcting of the modulation wave of the inverter based on the latest compensated voltage value includes: When the latest compensated voltage value is greater than the limit value, the modulation wave of the inverter is corrected based on the limit value.

8. A bus balance control system for a three-level PWM inverter, characterized in that, including: A first obtaining module, which obtains the initial positive and negative bus voltage differences and / or the initial DC component of the current of the inverter as initial balance state data, and obtains initial coefficient data corresponding to the initial balance state data; A first processing module, which obtains a compensated voltage value based on the initial balance state data and the initial coefficient data; A correcting module, which corrects the modulation wave of the inverter based on the latest compensated voltage value; A second obtaining module, which obtains the corrected positive and negative bus voltage differences and / or the corrected DC component of the current of the inverter after the modulation wave is corrected as corrected balance state data, and obtains the change situation of the balance state data of the inverter before and after the modulation wave correction; An adjusting module, which adjusts the current coefficient data based on the change situation of the balance state data of the inverter before and after the modulation wave correction to obtain new coefficient data; A second processing module, which obtains a new compensated voltage value based on the corrected balance state data of the inverter after the modulation wave is corrected and the new coefficient data.

9. An electronic device, including a processor and a memory; The processor is connected to the memory; The memory is used for storing executable program codes; The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the steps of a method for bus balance control of a three-level PWM inverter according to any one of claims 1 to 7.

10. A computer storage medium, which stores multiple instructions, and the instructions are suitable for being loaded and executed by a processor to execute the steps of a method for bus balance control of a three-level PWM inverter according to any one of claims 1 to 7.

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