Relaxation oscillator and motor

Abstract

The present application discloses a relaxation oscillator and motor, relating to the field of electronic power. The relaxation oscillator includes: a reference voltage module, a high-side comparator, a low-side comparator, a control module, and a filter. The control module is configured to set a high-side reset terminal to a high level when the high-side comparator outputs a high level, thereby clamping the output of the high-side comparator to a low level, thereby forming a preset narrow pulse at the high-side output terminal. The preset narrow pulse is sequentially composed of a low level, a high level, and a low level. The control module is also configured to set a low-side reset terminal to a low level when the low-side comparator outputs a high level, thereby clamping the output of the low-side comparator to a low level, thereby forming a preset narrow pulse at the low-side output terminal. The control module is also configured to jump the level of a clock signal outputted from a first output terminal when either the high-side comparator outputs a high level or the low-side comparator outputs a high level. The present application solves the problem of poor accuracy of the clock signal outputted by the relaxation oscillator.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic power technology, and in particular to a relaxation oscillator and a motor. Background Art

[0002] Motor driver chip applications typically require a clock frequency between 1MHz (Megahertz) and 24MHz. Traditional ping-pong symmetrical relaxation oscillators directly generate a triangular wave signal by switching to control the charge and discharge of a capacitor, thereby generating a clock signal. However, this switching introduces charge injection, which causes voltage imbalance and reduces clock accuracy. Consequently, the clock signal output by relaxation oscillators currently suffers from poor accuracy.

[0003] The above content is only used to assist in understanding the technical solutions of the embodiments of the present application and does not constitute an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to provide a relaxation oscillator and a motor, aiming to solve the technical problem of poor accuracy of the clock signal output by the relaxation oscillator.

[0005] To achieve the above objectives, an embodiment of the present application provides a relaxation oscillator, comprising: a reference voltage module, a high-side comparator, a low-side comparator, a control module, and a filter, wherein the reference voltage module is connected to a high-side reference terminal of the high-side comparator and a low-side reference terminal of the low-side comparator, and the high-side comparison terminal of the high-side comparator and the low-side comparison terminal of the low-side comparator are connected to a voltage output terminal of the filter;

[0006] The high-side output terminal of the high-side comparator and the low-side output terminal of the low-side comparator are both connected to the input terminal of the control module, and the high-side reset terminal of the high-side comparator and the low-side reset terminal of the low-side comparator are both connected to the first output terminal of the control module;

[0007] The control module is used to set the high-side reset terminal to a high level when the high-side comparator outputs a high level, so as to clamp the output of the high-side comparator to a low level, so as to form a preset narrow pulse at the high-side output terminal, wherein the preset narrow pulse is composed of a low level, a high level and a low level in sequence;

[0008] The control module is further configured to set the low-side reset terminal to a low level when the low-side comparator outputs a high level, so as to clamp the output of the low-side comparator to a low level, thereby forming a preset narrow pulse at the low-side output terminal;

[0009] The control module is further configured to change the level of the clock signal outputted by the first output terminal when the high-side comparator outputs a high level or the low-side comparator outputs a high level.

[0010] In one embodiment, the high-side comparator includes a first current source unit, a high-side comparison unit, and a high-side secondary clamping unit connected in sequence;

[0011] The high-side comparison unit is connected to the high-side reference terminal, the high-side comparison terminal and the high-side output terminal, the high-side secondary clamping unit is connected to the high-side reset terminal and the high-side output terminal, the first current source unit is connected to the high-side enable terminal of the high-side comparator, and the high-side enable terminal is connected to the second output terminal of the control module;

[0012] The high-side comparator is configured to output a high level when the high-side enable terminal is at a high level and the voltage of the high-side comparison terminal is greater than the voltage of the high-side reference terminal;

[0013] The high-side secondary clamping unit is used for clamping the high-side output terminal to a low level when the high-side reset terminal is set to a high level, so as to form a preset narrow pulse at the high-side output terminal;

[0014] The first current source unit is configured to output a first preset maximum current when the high-side enable terminal is at a high level, and is also configured to output a first preset low-power consumption current when the high-side enable terminal is at a low level.

[0015] In one embodiment, the first current source includes a first switch tube and a second switch tube; the high-side comparison unit includes a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and a ninth switch tube;

[0016] The first end of the first switch tube is connected to the high-side enable terminal, the first end of the second switch tube is connected to a first preset bias voltage, the second end of the second switch tube is connected to a preset low voltage terminal, and the third end of the second switch tube is connected to the second end of the first switch tube;

[0017] The third end of the first switch tube is connected to the second end of the third switch tube and the second end of the fourth switch tube, the first end of the third switch tube is connected to the high-side reference end, and the first end of the fourth switch tube is connected to the high-side comparison end;

[0018] The third end of the fourth switch tube is connected to the third end of the fifth switch tube, the second end of the fifth switch tube is connected to the second end of the sixth switch tube, the first end of the sixth switch tube is connected to the first end of the fifth switch tube, and the third end of the sixth switch tube is connected to the third end of the third switch tube;

[0019] The second end of the fourth switch tube is connected to the third end of the ninth switch tube, the first end of the ninth switch tube and the first end of the seventh switch tube are both connected to a first preset bias voltage, the second end of the seventh switch tube is connected to the second end of the ninth switch tube, and the third end of the seventh switch tube is connected to the high-side output terminal and the high-side secondary clamping unit;

[0020] The high-side output end is also connected to the third end of the eighth switch tube, and the first end and the second end of the eighth switch tube are both connected to the high-side secondary clamping unit.

[0021] In one embodiment, the high-side secondary clamping unit includes a first clamping switch tube, a second clamping switch tube, a first inverter, and a second inverter;

[0022] The first end of the first clamping switch tube is connected to the output end of the first inverter, the output end of the first inverter is also connected to the input end of the second inverter, the input end of the first inverter is connected to the high-side reset end, the second end of the first clamping switch tube is connected to the second end of the eighth switch tube, and the third end of the first clamping switch tube is connected to the first end of the eighth switch tube;

[0023] The output end of the second inverter is connected to the first end of the second clamping switch tube, the second end of the second clamping switch tube is connected to the preset low voltage end, and the third end of the second clamping switch tube is connected to the high-side output end.

[0024] In one embodiment, the low-side comparator includes a second current source unit, a low-side comparison unit, and a low-side secondary clamping unit connected in sequence;

[0025] The low-side comparison unit is connected to the low-side reference terminal, the low-side comparison terminal and the low-side output terminal, the low-side secondary clamping unit is connected to the low-side reset terminal and the low-side output terminal, the second current source unit is connected to the low-side enable terminal of the low-side comparator, and the low-side enable terminal is connected to the second output terminal of the control module;

[0026] The low-side comparator is configured to output a high level when the low-side enable terminal is at a low level and the voltage of the low-side comparison terminal is greater than the voltage of the low-side reference terminal;

[0027] The low-side secondary clamping unit is used for clamping the low-side output terminal to a low level when the low-side reset terminal is set to a low level, so as to form a preset narrow pulse at the low-side output terminal;

[0028] The second current source unit is configured to output a second preset maximum current when the low-side enable terminal is at a low level, and is also configured to output a second preset low-power consumption current when the low-side enable terminal is at a high level.

[0029] In one embodiment, the second current source unit includes a tenth switch tube and an eleventh switch tube;

[0030] The low-side comparison unit includes: a twelfth switch tube, a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube, a sixteenth switch tube, a seventeenth switch tube, an eighteenth switch tube and a third inverter;

[0031] The first end of the tenth switch tube is connected to the low-side enable terminal, the first end of the eleventh switch tube is connected to the second preset bias voltage, the second end of the eleventh switch tube is connected to the preset power supply terminal, and the third end of the eleventh switch tube is connected to the second end of the tenth switch tube;

[0032] The third end of the tenth switch tube is connected to the second end of the twelfth switch tube and the second end of the thirteenth switch tube, the first end of the twelfth switch tube is connected to the low-side reference end, and the first end of the thirteenth switch tube is connected to the low-side comparison end;

[0033] The third end of the thirteenth switch tube is connected to the third end of the fourteenth switch tube, the second end of the fourteenth switch tube is connected to the second end of the fifteenth switch tube, the first end of the fifteenth switch tube is connected to the first end of the fourteenth switch tube, and the third end of the fifteenth switch tube is connected to the third end of the twelfth switch tube;

[0034] The second end of the twelfth switch tube is connected to the third end of the eighteenth switch tube, the first end of the eighteenth switch tube and the first end of the seventeenth switch tube are connected to a second preset bias voltage, and the second end and the third end of the seventeenth switch tube are connected to the low-side secondary clamping unit;

[0035] The third end of the seventeenth switch tube is connected to the input end of the third inverter and the third end of the sixteenth switch tube, the first end and the second end of the sixteenth switch tube are connected to the low-side secondary clamping unit, and the output end of the third inverter is connected to the low-side output end.

[0036] In one embodiment, the low-side secondary clamping unit includes: a third clamping switch tube, a fourth clamping switch tube, a fourth inverter, and a fifth inverter;

[0037] The low-side reset terminal is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is connected to the input terminal of the fifth inverter and the first terminal of the third clamping switch tube, the second terminal of the third clamping switch tube is connected to the second terminal of the sixteenth switch tube, and the third terminal of the third clamping switch tube is connected to the first terminal of the sixteenth switch tube;

[0038] The output end of the fifth inverter is connected to the first end of the fourth clamping switch tube, the second end of the fourth clamping switch tube is connected to the preset power supply end, and the third end of the fourth clamping switch tube is connected to the input end of the third inverter.

[0039] In one embodiment, the reference voltage module further includes a preset inverting unit and a preset voltage dividing unit, the preset inverting unit is connected to the preset voltage dividing unit, and the preset voltage dividing unit is connected to the high-side reference terminal and the low-side reference terminal;

[0040] The preset inverting unit includes a first preset switching tube and a second preset switching tube, the first end of the first preset switching tube and the first end of the second preset switching tube are both connected to the preset input control end, the second end of the first preset switching tube is connected to the preset power supply end, and the third end of the first preset switching tube and the second end and third end of the second preset switching tube are all connected to the preset voltage dividing unit.

[0041] In one embodiment, the preset voltage dividing unit includes a first voltage dividing switch tube, a second voltage dividing switch tube and a third voltage dividing switch tube;

[0042] The first end of the first voltage-dividing switch tube is connected to the high-side reference end, the second end of the first voltage-dividing switch tube is connected to the preset power supply end, and the third end of the first voltage-dividing switch tube is connected to the second end of the second voltage-dividing switch tube;

[0043] The first end of the second voltage-dividing switch tube is connected to the third end of the first preset switch tube and the third end of the second preset switch tube, and the third end of the second voltage-dividing switch tube is connected to the second end of the third voltage-dividing switch tube and the low-side reference end;

[0044] The first end and the third end of the third voltage-dividing switch tube are both connected to a preset low voltage end.

[0045] In addition, to achieve the above-mentioned purpose, an embodiment of the present application further provides a motor, comprising the relaxation oscillator as described above.

[0046] One or more technical solutions proposed in the embodiments of the present application have at least the following technical effects: the embodiments of the present application provide a reference voltage module, a high-side comparator, a low-side comparator, a control module, and a filter, wherein the reference voltage module is connected to the high-side reference terminal of the high-side comparator and the low-side reference terminal of the low-side comparator, the high-side comparison terminal of the high-side comparator and the low-side comparison terminal of the low-side comparator are connected to the voltage output terminal of the filter; the high-side output terminal of the high-side comparator and the low-side output terminal of the low-side comparator are both connected to the input terminal of the control module, and the high-side reset terminal of the high-side comparator and the low-side reset terminal of the low-side comparator are both connected to the first output terminal of the control module. Thus, the control module can jump the level of the clock signal output by the first output terminal when the high-side comparator outputs a high level or the low-side comparator outputs a high level, thereby realizing the generation of the clock signal by the high-side comparator and the low-side comparator without generating oscillation by switching to generate the clock signal, thereby avoiding the switch charge injection during the switching process, and also avoiding the influence of voltage imbalance on the clock signal, thereby improving the accuracy of the clock signal.

[0047] Furthermore, since the present application realizes the output of the clock signal through the levels output by the high-side comparator and the low-side comparator, and since the levels output by the high-side comparator and the low-side comparator are delayed, it is possible that the high-side comparator and the low-side comparator simultaneously output a high level, which may cause the clock signal to be disordered and reduce the accuracy of the clock signal. Therefore, the present application sets the high-side reset terminal to a high level when the high-side comparator outputs a high level, so as to clamp the output of the high-side comparator to a low level, thereby forming a preset narrow pulse consisting of a low level, a high level and a low level in sequence, and also sets the low-side reset terminal to a low level when the low-side comparator outputs a high level, so as to clamp the output of the low-side comparator to a low level, thereby also forming a preset narrow pulse and thus avoiding the situation where the low-side comparator and the high-side comparator simultaneously have a high level, so as to improve the accuracy of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the embodiments of the present application, and together with the specification are used to explain the principles of the embodiments of the present application.

[0049] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1This is a schematic diagram of module connections of an embodiment of a relaxation oscillator according to an embodiment of the present application;

[0051] Figure 2 This is a schematic diagram of module connections of a high-side comparator in a relaxation oscillator according to an embodiment of the present application;

[0052] Figure 3 This is a circuit connection diagram of a high-side comparator in a relaxation oscillator according to an embodiment of the present application;

[0053] Figure 4 This is a schematic diagram of module connections of a low-side comparator in a relaxation oscillator according to an embodiment of the present application;

[0054] Figure 5 This is a circuit connection diagram of a low-side comparator in a relaxation oscillator according to an embodiment of the present application;

[0055] Figure 6 This is a schematic diagram of module connections in another embodiment of the relaxation oscillator of the present application;

[0056] Figure 7 This is a circuit connection diagram of a specific circuit structure including a control module and a filter in the relaxation oscillator according to an embodiment of the present application;

[0057] Figure 8 Schematic diagram of an ideal VRC (Voltage of Resistance-Capacitance Filter, RC filter output voltage) waveform of the filter output in the relaxation oscillator according to an embodiment of the present application;

[0058] Figure 9 Schematic diagram of an actual VRC waveform output by a filter in a relaxation oscillator according to an embodiment of the present application;

[0059] Figure 10 Schematic diagram of waveforms of the actual VRC waveform output by the filter, the clock signal, the output of the high-side comparator, and the output of the low-side comparator when the comparator does not have a secondary clamp and when the comparator has a secondary clamp in the relaxation oscillator according to an embodiment of the present application;

[0060] Figure 11 This is a circuit connection diagram of a specific circuit structure of a reference voltage module included in an embodiment of a relaxation oscillator according to an embodiment of the present application;

[0061] Figure 12 Schematic diagram of the waveform of the relaxation oscillator soft start in the embodiment of the present application;

[0062] Figure 13 1 is a circuit connection diagram of a specific circuit structure of a reference voltage module included in another embodiment of the relaxation oscillator in the embodiments of the present application.

[0063] Description of Figure Numbers:

[0064] 100, reference voltage module; 200, high-side comparator; 300, low-side comparator; 400, control module; 500, filter; PI1, high-side comparison terminal; NI1, high-side reference terminal; PI2, low-side reference terminal; NI2, low-side reference terminal; PD, high-side reset terminal; PU, low-side reset terminal; GT, high-side output terminal; DT, low-side output terminal; R, first input terminal of the control module; S, second input terminal of the control module; QBD, first output terminal of the control module; VRC, voltage output of the filter; Q, second output terminal of the control module; SW, high-side enable terminal; SWB, low-side enable terminal; 210, first current source unit; 220, high-side comparison unit; 230, high-side secondary clamp unit; VBN, first preset bias voltage; M1~M18, first switch tube The eighteenth switch tube; MQ1-MQ4, the first clamping switch tube to the fourth clamping switch tube; F1-F8, the first inverter to the eighth inverter; 310, the second current source unit; 320, the low-side comparator unit; 330, the low-side secondary clamping unit; VBP, the second preset bias voltage; 600, the buffer; H1, the first NOR gate; H2, the second NOR gate; YM, the AND gate; PBD, the second input terminal of the AND gate; R1, the first resistor; 510, the filter switch tube; 410, the RS latch; VSS, the preset low voltage terminal; VDD, the preset power terminal; My1-My2, the first preset switch tube to the second preset switch tube; Mf1-Mf3, the first voltage divider switch tube to the third voltage divider switch tube; Md1-Md2, the first preset grounding switch tube to the second preset grounding switch tube.

[0065] The purpose, features and advantages of the embodiments of the present application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0066] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the embodiments of the present application and are not intended to limit the embodiments of the present application.

[0067] In order to better understand the technical solutions of the embodiments of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0068] Motor driver chip applications generally require a clock frequency of 1MHz to 24MHz. For driver chips, clock accuracy may not be as critical, but the lowest possible power consumption is desirable. Traditional ping-pong symmetrical relaxation oscillators use resistors, capacitors, or a combination of reference current and capacitors to generate clock signals, but this suffers from large size and high power consumption. Furthermore, relaxation oscillators directly generate triangular waves by controlling the charge and discharge of capacitors through switches. However, due to the switch control, the triangular wave is subject to switch charge injection, which in turn introduces voltage offsets. Voltage offsets are sensitive to PVT (Process, Voltage, and Temperature) variations, thus reducing clock accuracy.

[0069] Therefore, the present application provides a relaxation oscillator. The clock signal generated by the relaxation oscillator in the present application is not affected by the switching charge introduced by the switch switching, thereby improving the clock accuracy. In the present application, a comparator with a faster single-edge response is adopted, namely a high-side comparator and a low-side comparator, thereby saving the power consumption of the relaxation oscillator. A two-level clamping control is added to both the high-side comparator and the low-side comparator, thereby achieving the goal of avoiding clock confusion while reducing power consumption, so as to improve the robustness of the relaxation oscillator.

[0070] Based on this, the embodiment of the present application provides a relaxation oscillator, referring to Figure 1 , Figure 1 This is a module diagram of a relaxation oscillator according to an embodiment of the present application. It includes a reference voltage module 100, a high-side comparator 200, a low-side comparator 300, a control module 400, and a filter 500. The reference voltage module 100 is connected to the high-side reference terminal NI1 of the high-side comparator 200 and the low-side reference terminal PI2 of the low-side comparator 300. The high-side comparison terminal PI1 of the high-side comparator 200 and the low-side comparison terminal NI2 of the low-side comparator 300 are connected to the voltage output terminal of the filter 500.

[0071] The high-side output terminal GT of the high-side comparator 200 and the low-side output terminal DT of the low-side comparator 300 are both connected to the input terminal of the control module 400, and the high-side reset terminal PD of the high-side comparator 200 and the low-side reset terminal PU of the low-side comparator 300 are both connected to the first output terminal QBD of the control module 400;

[0072] The control module 400 is configured to set the high-side reset terminal PD to a high level when the high-side comparator 200 outputs a high level, so as to clamp the output of the high-side comparator 200 to a low level, thereby forming a preset narrow pulse at the high-side output terminal GT, wherein the preset narrow pulse is sequentially composed of a low level, a high level, and a low level;

[0073] The control module 400 is further configured to set the low-side reset terminal PU to a low level when the low-side comparator 300 outputs a high level, so as to clamp the output of the low-side comparator 300 to a low level, thereby forming a preset narrow pulse at the low-side output terminal DT;

[0074] The control module 400 is further configured to change the level of the clock signal outputted from the first output terminal when the high-side comparator 200 outputs a high level or the low-side comparator 300 outputs a high level.

[0075] It should be noted that the reference voltage module 100 is used to generate a reference voltage. The reference voltage can be input to the high-side reference terminal NI1 of the high-side comparator 200 and the low-side reference terminal PI2 of the low-side comparator 300. The voltage input to the high-side reference terminal NI1 of the reference voltage module 100 is different from the voltage input to the low-side reference terminal PI2. For example, the voltage of the high-side reference terminal NI1 is VDD or 2 / 3 VDD, and the voltage of the low-side reference terminal PI2 is VSS or 1 / 3 VDD. VDD is a preset power supply terminal, which can be the positive voltage of the power supply connected to the reference voltage module 100. VSS can be a preset low voltage terminal, which is the negative voltage of the power supply connected to the reference voltage module 100.

[0076] The filter 500 may be a resistor-capacitor filter 500 , which may generate a triangular wave. The voltage output of the filter 500 may be connected to the high-side comparison terminal PI1 of the high-side comparator 200 and the low-side comparison terminal NI2 of the low-side comparator 300 . The high-side comparison terminal PI1 and the high-side reference terminal NI1 are both input terminals of the high-side comparator 200 , while the low-side comparison terminal NI2 and the low-side reference terminal PI2 are both input terminals of the low-side comparator 300 . The filter 500 is connected to the high-side comparison terminal PI1 and the low-side comparison terminal NI2 , and the reference voltage module 100 is connected to the high-side reference terminal NI1 and the low-side reference terminal PI2 . This allows the high-side comparator 200 and the low-side comparator 300 to output different voltage levels based on their respective inputs, thereby facilitating the subsequent generation of a clock signal.

[0077] In this embodiment, the high-side reference terminal NI1 may be the negative input terminal of the high-side comparator 200, the high-side comparison terminal PI1 may be the positive input terminal of the high-side comparator 200, the low-side reference terminal PI2 may be the positive input terminal of the low-side comparator 300, and the low-side comparison terminal NI2 may be the negative input terminal of the low-side comparator 300. When the voltage of the high-side comparison terminal PI1 is greater than the high-side reference terminal NI1, the high-side output terminal GT of the high-side comparator 200 outputs a high level, otherwise it outputs a low level. When the voltage of the low-side comparison terminal NI2 is less than the low-side reference terminal PI2, the low-side output terminal DT of the low-side comparator 300 outputs a high level, otherwise it outputs a low level.

[0078] The input end of the filter 500 is connected to the first output end of the control module 400. The filter 500 can output a corresponding triangular wave based on the level signal output from the first output end, and then the high-side comparator 200 and the low-side comparator 300 output corresponding levels according to the voltage of the triangular wave.

[0079] When the voltage at the high-side comparison terminal PI1 changes from being less than the voltage at the high-side reference terminal NI1 to being greater than the voltage at the high-side reference terminal NI1, the corresponding high-side output terminal GT of the high-side comparator 200 will jump from a low level to a high level. Therefore, before the high-side comparator 200 outputs a high level, the high-side comparator 200 will output a low level. The high-side reset terminal PD can be the power-down terminal of the high-side comparator 200. When the high-side reset terminal PD is at a high level, the output of the high-side comparator 200 can be clamped to a low level. Therefore, the low level output by the high-side comparator 200 before outputting a high level, the high level output by the high-side comparator, and the clamped low level output can form a preset narrow pulse. The preset narrow pulse consists of a low level, a high level, and a low level in sequence. The first low level in the preset narrow pulse is the low level before the output of the comparator jumps to a high level, and the last low level in the preset narrow pulse is the clamped output. This can avoid output clock disorder caused by the slow falling edge of the high-side comparator 200 .

[0080] When the voltage of the low-side comparison terminal NI2 changes from being greater than the voltage of the low-side reference terminal PN2 to being less than the voltage of the low-side reference terminal PN2, the low-side output terminal DT of the corresponding low-side comparator 300 will jump from a low level to a high level. Therefore, before the low-side comparator outputs a high level, the low-side comparator will output a low level. The low-side reset terminal PU can be the power-on terminal of the low-side comparator 300. When the low-side reset terminal PU is at a low level, the output of the low-side comparator 300 can be clamped to a low level, so that the low level, high level and low level of the clamped output of the low-side comparator 300 form a preset narrow pulse, which can avoid the output clock disorder caused by the arrival of the slower falling edge of the low-side comparator 300. This is convenient for improving the accuracy of the clock signal.

[0081] The control module 400 can jump the level of the clock signal output from the first output terminal when the high-side comparator 200 outputs a high level, and jump the level of the clock signal output from the first output terminal when the low-side comparator 300 outputs a low level. The jumping level refers to jumping from a high level to a low level, or from a low level to a high level.

[0082] In other embodiments, the first output terminal of the control module 400 may be further connected to a buffer, and the clock signal may be output to the outside through the buffer, so as to improve the stability of the clock signal output to the outside. Figure 1The input terminal of the control module 400 may include a first input terminal and a second input terminal. Figure 1 Where outs may represent the output of a clock signal, R may be the first input terminal of the control module 400, and S may be the second input terminal of the control module 400. The control module may include an RS latch, the first input terminal of the control module may be the R terminal of the RS latch, and the second input terminal of the control module may be the S terminal of the RS latch.

[0083] The embodiment of the present application can realize the generation of a clock signal through the high-side comparator 200 and the low-side comparator 300, without generating oscillation through switch switching to generate a clock signal, thereby avoiding switch charge injection during the switch switching process and avoiding the influence of voltage imbalance on the clock signal, thereby improving the accuracy of the clock signal.

[0084] In addition, since the present application realizes the output of the clock signal through the levels output by the high-side comparator 200 and the low-side comparator 300, and since the levels output by the high-side comparator 200 and the low-side comparator 300 respectively have a certain delay, it is possible that the high-side comparator 200 and the low-side comparator 300 output a high level at the same time. Since the control module includes an RS latch, when the high-side comparator and the low-side comparator output a high level at the same time, the RS latch will also receive two high levels at the same time, which will destroy the complementary relationship of the RS latch, resulting in clock signal disorder and reduced clock signal accuracy. Therefore, the present application sets the high-side reset terminal PD to a high level when the high-side comparator 200 outputs a high level, so as to clamp the output of the high-side comparator 200 to a low level, and also sets the low-side reset terminal PU to a low level when the low-side comparator 300 outputs a high level, so as to clamp the output of the low-side comparator 300 to a low level, thereby avoiding the situation where the low-side comparator 300 and the high-side comparator 200 appear at a high level at the same time, so as to improve the accuracy of the clock signal.

[0085] In a possible embodiment, please refer to Figure 2 , the high-side comparator 200 includes a first current source unit 210, a high-side comparison unit 220 and a high-side secondary clamping unit 230 connected in sequence;

[0086] The high-side comparison unit 220 is connected to the high-side reference terminal NI1, the high-side comparison terminal PI1 and the high-side output terminal GT, the high-side secondary clamping unit 230 is connected to the high-side reset terminal PD and the high-side output terminal GT, the first current source unit 210 is connected to the high-side enable terminal SW of the high-side comparator 200, and the high-side enable terminal SW is connected to the second output terminal Q of the control module 400;

[0087] The high-side comparator 200 is configured to output a high level when the high-side enable terminal SW is at a high level and the voltage of the high-side comparison terminal PI1 is greater than the voltage of the high-side reference terminal NI1;

[0088] The high-side secondary clamping unit 230 is used to clamp the high-side output terminal GT to a low level when the high-side reset terminal PD is set to a high level, so as to form a preset narrow pulse, which is composed of a low level, a high level and a low level in sequence;

[0089] The first current source unit 210 is configured to output a first preset maximum current when the high-side enable terminal SW is at a high level, and is also configured to output a first preset low-power current when the high-side enable terminal SW is at a low level.

[0090] It should be noted that the high-side comparator 200 is a comparator with a fast single-edge response. For example, when the voltage of the high-side comparison terminal PI1 is greater than the voltage of the high-side reference terminal NI1, the high-side comparator 200 can output a high level relatively quickly. When the voltage of the high-side comparison terminal PI1 is less than the voltage of the high-side reference terminal NI1, the high-side comparator 200 outputs a low level relatively slowly.

[0091] The first current source unit 210 can generate a current to drive the high-side comparator 200 to output a corresponding level, such as a high level. The first current source is connected to the high-side enable terminal SW of the high-side comparator 200. The high-side enable terminal SW is connected to the second output terminal of the control module 400. The second output terminal is also connected to the low-side enable terminal SWB of the low-side comparator 300. The level received by the low-side enable terminal SWB is consistent with the level received by the high-side enable terminal SW because both are output from the second output terminal.

[0092] The current generated by the first current source is dynamic. For example, when the high-side enable terminal SW is at a high level, it outputs a first preset maximum current. It is also used to output a first preset low-power current when the high-side enable terminal SW is at a low level. The first preset maximum current can be the maximum current that the first current source can generate. The first preset low-power current can be determined based on actual conditions. The first preset low-power current indicates that the first current source is not completely turned off and a weaker current source is still retained. This allows the first current source to respond quickly the next time the high-side enable terminal SW is reset, thereby enabling the high-side comparator 200 to respond quickly and output a high level quickly. The greater the current output by the first current source, the faster the response speed of the high-side comparator 200, and vice versa.

[0093] The high-side secondary clamping unit 230 is connected to the high-side comparison unit 220 and the high-side output terminal GT. The high-side secondary clamping unit 230 can clamp the output of the high-side comparator 200 to a low level when the high-side comparator 200 outputs a high level and the high-side reset terminal PD is at a high level, which is also convenient for saving power consumption of the high-side comparator 200 because the time that the high-side comparator 200 is at a high level is reduced, thereby saving power consumption.

[0094] The high-side comparison unit 220 can enable the high-side comparator 200 to respond quickly to the situation where the voltage of the high-side comparison terminal PI1 is greater than the high-side reference terminal NI1, and respond slowly when the voltage of the high-side comparison terminal PI1 is less than the high-side reference terminal NI1. Therefore, there is no need to respond quickly in both situations, which helps save power consumption. Because if both sides need to respond faster, then higher energy consumption needs to be provided for the slow response situation to make the response fast.

[0095] In a possible embodiment, please refer to Figure 3 , the first current source includes a first switch tube M1 and a second switch tube M2; the high-side comparison unit 220 includes a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, a sixth switch tube M6, a seventh switch tube M7, an eighth switch tube M8 and a ninth switch tube M9;

[0096] A first end of the first switch tube M1 is connected to the high-side enable terminal SW, a first end of the second switch tube M2 is connected to a first preset bias voltage VBN, a second end of the second switch tube M2 is connected to a preset low voltage terminal VSS, and a third end of the second switch tube M2 is connected to the second end of the first switch tube M1;

[0097] The third end of the first switch tube M1 is connected to the second end of the third switch tube M3 and the second end of the fourth switch tube M4, the first end of the third switch tube M3 is connected to the high-side reference terminal NI1, and the first end of the fourth switch tube M4 is connected to the high-side comparison terminal PI1;

[0098] The third end of the fourth switch tube M4 is connected to the third end of the fifth switch tube M5, the second end of the fifth switch tube M5 is connected to the second end of the sixth switch tube M6, the first end of the sixth switch tube M6 is connected to the first end of the fifth switch tube M5, and the third end of the sixth switch tube M6 is connected to the third end of the third switch tube M3;

[0099] The second end of the fourth switch tube M4 is connected to the third end of the ninth switch tube M9, the first end of the ninth switch tube M9 and the first end of the seventh switch tube M7 are both connected to the first preset bias voltage VBN, the second end of the seventh switch tube M7 is connected to the second end of the ninth switch tube M9, and the third end of the seventh switch tube M7 is connected to the high-side output terminal GT and the high-side secondary clamping unit 230;

[0100] The high-side output terminal GT is further connected to the third terminal of the eighth switch tube M8 , and the first terminal and the second terminal of the eighth switch tube M8 are both connected to the high-side secondary clamping unit 230 .

[0101] It should be noted that each switch is a field-effect transistor. For any switch, the first terminal of the switch can be the gate of the switch, the second terminal of the switch can be the source of the switch, and the third terminal of the switch can be the drain of the switch. The first current source includes the first switch M1 and the second switch M2, both of which can be NMOS.

[0102] The high-side enable terminal SW can serve as a switch for the first current source. For example, when the high-side enable terminal SW is at a high level, the first current source outputs a first preset maximum current, and the high-side comparator 200 responds at the fastest speed until the high-side comparator 200 outputs a high level. The high-side enable terminal SW is switched to a low level. When the high-side enable terminal SW is switched to a low level, the first current source outputs a first preset low-power current so that the comparator can respond quickly the next time SW is pulled high. Since the first current source does not need to continuously output the first preset maximum current, it only needs to output the first preset maximum current when the high-side comparator 200 needs to output a high level, thereby saving power consumption without affecting the original function. The preset low voltage terminal VSS can be the negative pole of the power supply.

[0103] The control module 400 is configured to output a low level at the second output terminal after the high-side comparator 200 outputs a high level, thereby setting both the high-side enable terminal SW and the low-side enable terminal SWB to a low level. Furthermore, when the low-side comparator 300 outputs a high level, the control module 400 outputs a high level at the second output terminal, thereby setting both the high-side enable terminal SW and the low-side enable terminal SWB to a high level. That is, after the high-side comparator 200 completes comparison, the low-side comparator 300 performs comparison, and this cycle repeats.

[0104] The first preset bias voltage VBN can provide a bias voltage for the second switch M2, the ninth switch M9, and the seventh switch M7 to ensure normal operation of the circuit. The third switch M3, the fourth switch M4, the seventh switch M7, and the ninth switch M9 can all be NMOS transistors, and the fifth switch M5, the sixth switch M6, and the eighth switch M8 can all be PMOS transistors.

[0105] The following describes, in conjunction with high-side comparison unit 220, the process of the output level of high-side output terminal GT when the voltages of high-side comparison terminal PI1 and high-side reference terminal NI1 change. When the voltage at high-side comparison terminal PI1 is greater than the voltage at high-side reference terminal NI1, the drain level of fourth switch M4 is pulled low, the current of eighth switch M8 increases, the drain level of eighth switch M8 is pulled high, and high-side output terminal GT outputs a high level.

[0106] When the voltage at high-side comparison terminal PI1 is lower than high-side reference terminal NI1, the drain level of the third switch M3 is pulled low, the current of the fifth switch M5 increases, the drain level of the fifth switch M5 is pulled high, the current of the eighth switch M8 decreases, the drain level of the eighth switch M8 is pulled low, and the high-side output terminal GT outputs a low level. Therefore, when the voltage at high-side comparison terminal PI1 is higher than the voltage at high-side reference terminal NI1, the signal passes through the fourth switch M4 and the eighth switch M8. When the voltage at high-side comparison terminal PI1 is lower than the voltage at high-side reference terminal NI1, the signal passes through the third switch M3, the fifth switch M5, the sixth switch M6, and the eighth switch M8. When the voltage at high-side comparison terminal PI1 is higher than the voltage at high-side reference terminal NI1, the signal passes through fewer devices, resulting in less delay and a faster response. However, when the voltage at high-side comparison terminal PI1 is lower than the voltage at high-side reference terminal NI1, the signal passes through more devices, resulting in greater delay and a slower response.

[0107] In a possible embodiment, please refer to Figure 3 The high-side secondary clamping unit 230 includes a first clamping switch tube MQ1, a second clamping switch tube MQ2, a first inverter F1 and a second inverter F2;

[0108] A first end of the first clamping switch tube MQ1 is connected to the output end of the first inverter F1, the output end of the first inverter F1 is also connected to the input end of the second inverter F2, the input end of the first inverter F1 is connected to the high-side reset end PD, a second end of the first clamping switch tube MQ1 is connected to the second end of the eighth switch tube M8, and a third end of the first clamping switch tube MQ1 is connected to the first end of the eighth switch tube M8;

[0109] The output end of the second inverter F2 is connected to the first end of the second clamping switch tube MQ2, the second end of the second clamping switch tube MQ2 is connected to the preset low voltage end VSS, and the third end of the second clamping switch tube MQ2 is connected to the high-side output end GT.

[0110] It should be noted that the first clamping switch tube MQ1 can be a PMOS, and the second clamping switch tube MQ2 can be an NMOS. The connection relationship between the first clamping switch tube MQ1 and the second clamping switch tube MQ2 and the high-side comparison unit 220 can be specifically referred to. Figure 3 The first inverter F1 and the second inverter F2 are used to invert the input. For example, when the input is high, the inverter outputs a low level. When the input is low, the inverter outputs a high level.

[0111] Reference Figure 3The clamping process of the high-side secondary clamping unit 230 is briefly described. When the high-side comparator 200 outputs a high level, the first output terminal of the control module 400 outputs a high level. The first output terminal is connected to the high-side reset terminal PD, so the high-side reset terminal PD is pulled high, the first clamping switch MQ1 is turned on, the eighth switch M8 is turned off, and the second clamping switch MQ2 is turned on. The second stage of the high-side comparator 200 is clamped to a low level, and the high-side output terminal GT of the high-side comparator 200 outputs a low level. Clamping the second stage of the high-side comparator 200 to a low level can save power consumption of the second stage of the comparator. The high level output of the high-side comparator 200 and the low level output of the second clamping stage form a narrow pulse, which can avoid output clock distortion caused by the slow falling edge of the high-side comparator 200.

[0112] In a possible embodiment, please refer to Figure 4 , the low-side comparator 300 includes a second current source unit 310, a low-side comparison unit 320 and a low-side secondary clamping unit 330 connected in sequence;

[0113] The low-side comparison unit 320 is connected to the low-side reference terminal PI2, the low-side comparison terminal NI2 and the low-side output terminal DT, the low-side secondary clamping unit 330 is connected to the low-side reset terminal PU and the low-side output terminal DT, the second current source unit 310 is connected to the low-side enable terminal SWB of the low-side comparator 300, and the low-side enable terminal SWB is connected to the second output terminal of the control module 400;

[0114] The low-side comparator 300 is configured to output a high level when the low-side enable terminal SWB is at a low level and the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2;

[0115] The low-side secondary clamping unit 330 is used to clamp the low-side output terminal DT to a low level when the low-side reset terminal PU is set to a low level, so as to form a preset narrow pulse;

[0116] The second current source unit 310 is configured to output a second preset maximum current when the low-side enable terminal SWB is at a low level, and is further configured to output a second preset low-power consumption current when the low-side enable terminal SWB is at a high level.

[0117] It should be noted that the low-side comparator 300 is also a comparator with a fast single-edge response. For example, when the voltage of the low-side comparison terminal NI2 is less than the voltage of the low-side reference terminal PI2, the low-side comparator 300 can output a high level relatively quickly. When the voltage of the low-side comparison terminal NI2 is greater than the voltage of the low-side reference terminal PI2, the low-side comparator 300 outputs a low level relatively slowly.

[0118] The second current source unit 310 can generate a current to drive the low-side comparator 300 to output a corresponding level, such as a high level. The second current source is connected to the low-side enable terminal SWB of the low-side comparator 300. The low-side enable terminal SWB is connected to the second output terminal of the control module 400. The second output terminal is also connected to the low-side enable terminal SWB of the low-side comparator 300. The level received by the low-side enable terminal SWB is consistent with the level received by the low-side enable terminal SWB because both are output by the second output terminal.

[0119] The current generated by the second current source is dynamic. For example, when the low-side enable terminal SWB is at a low level, it outputs a second preset maximum current. It is also used to output a second preset low-power current when the low-side enable terminal SWB is at a high level. The control module 400 sets the low-side enable terminal SWB to a high level after the low-side comparator 300 outputs a high level.

[0120] The second preset maximum current can be the maximum current that the second current source can produce, the second preset low-power consumption current can be determined based on actual conditions, the second preset low-power consumption current characterizes that the second current source is not completely closed, and still retains a weaker current source operation, so that when the low-side enable terminal SWB is pulled low next time, the second current source can respond quickly, thereby enabling the low-side comparator 300 to respond quickly, to quickly output a high level. The larger the current output by the second current source, the faster the response speed of the low-side comparator 300, and vice versa. The first preset maximum current and the second preset maximum current can be the same or different.

[0121] The low-side secondary clamping unit 330 is connected to the low-side comparison unit 320 and the low-side output terminal DT. The low-side secondary clamping unit 330 can clamp the output of the low-side comparator 300 to a low level when the low-side comparator 300 outputs a high level and the low-side reset terminal PU is a low level, which is also convenient for saving power consumption of the low-side comparator 300 because the time that the low-side comparator 300 is at a high level is reduced, thereby saving power consumption.

[0122] The low-side comparison unit 320 can enable the low-side comparator 300 to respond quickly to the situation where the voltage of the low-side comparison terminal NI2 is less than the low-side reference terminal PI2, and respond slowly when the voltage of the low-side comparison terminal NI2 is greater than the low-side reference terminal PI2. Therefore, there is no need to respond quickly in both situations, which helps save power consumption. Because if both sides need to respond faster, then higher energy consumption needs to be provided for the slow response situation in order to achieve a fast response.

[0123] In one possible embodiment, referring to Figure 5 , the second current source unit 310 includes a tenth switch tube M10 and an eleventh switch tube M11;

[0124] The low-side comparison unit 320 includes: a twelfth switch tube M12, a thirteenth switch tube M13, a fourteenth switch tube M14, a fifteenth switch tube M15, a sixteenth switch tube M16, a seventeenth switch tube M17, an eighteenth switch tube M18 and a third inverter F3;

[0125] A first end of the tenth switch tube M10 is connected to the low-side enable terminal SWB, a first end of the eleventh switch tube M11 is connected to the second preset bias voltage VBP, a second end of the eleventh switch tube M11 is connected to the preset power supply terminal VDD, and a third end of the eleventh switch tube M11 is connected to the second end of the tenth switch tube M10;

[0126] The third end of the tenth switch tube M10 is connected to the second end of the twelfth switch tube M12 and the second end of the thirteenth switch tube M13, the first end of the twelfth switch tube M12 is connected to the low-side reference terminal PI2, and the first end of the thirteenth switch tube M13 is connected to the low-side comparison terminal NI2;

[0127] The third end of the thirteenth switch tube M13 is connected to the third end of the fourteenth switch tube M14, the second end of the fourteenth switch tube M14 is connected to the second end of the fifteenth switch tube M15, the first end of the fifteenth switch tube M15 is connected to the first end of the fourteenth switch tube M14, and the third end of the fifteenth switch tube M15 is connected to the third end of the twelfth switch tube M12;

[0128] The second end of the twelfth switch tube M12 is connected to the third end of the eighteenth switch tube M18, the first end of the eighteenth switch tube M18 and the first end of the seventeenth switch tube M17 are connected to the second preset bias voltage VBP, and the second end and the third end of the seventeenth switch tube M17 are connected to the low-side secondary clamping unit 330;

[0129] The third end of the seventeenth switch tube M17 is connected to the input end of the third inverter F3 and the third end of the sixteenth switch tube, the first end and the second end of the sixteenth switch tube are connected to the low-side secondary clamping unit 330, and the output end of the third inverter F3 is connected to the low-side output end DT.

[0130] It should be noted that the tenth switch tube and the eleventh switch tube M11 included in the second current source can both be PMOS. The low-side enable terminal SWB can serve as a switch for the second current source. For example, when the low-side comparator 300 is required to perform a comparison, the low-side enable terminal SWB can be set to a low level. When the low-side enable terminal SWB is low, the second current source outputs a second preset maximum current, and the response speed of the low-side comparator is fastest at this time. After the low-side comparator 300 outputs a high level, the low-side enable terminal SWB is switched to a high level. After the low-side enable terminal SWB is switched to a low level, the second current source outputs a second preset low-power current so that the low-side comparator 300 can respond quickly the next time SWB is pulled low. Since the second current source does not need to continuously output the second preset maximum current, it only needs to output the second preset maximum current when the low-side comparator 300 needs to output a high level, thereby saving power consumption without affecting the original function. The preset power supply terminal VDD can be the positive pole of the power supply.

[0131] The control module 400 is configured to output a high level at the second output terminal after the low-side comparator 300 outputs a high level, thereby setting both the high-side enable terminal SW and the low-side enable terminal SWB to a high level.

[0132] The second preset bias voltage VBP can provide a bias voltage for the eleventh switch M11, the seventeenth switch M17, and the eighteenth switch M18 to ensure normal operation of the circuit. The twelfth switch M12, the thirteenth switch M13, the seventeenth switch M17, and the eighteenth switch M18 are PMOS transistors, while the fourteenth switch M14, the fifteenth switch M15, and the sixteenth switch M16 can all be NMOS transistors. The third inverter F3, the fourth inverter F4, and the fifth inverter F5 can all be used for inverting inputs.

[0133] The following describes, in conjunction with the low-side comparison unit 320, the process of the output level of the low-side output terminal DT when the low-side comparison terminal NI2 and the low-side reference terminal PI2 change. When the voltage at the low-side comparison terminal NI2 is less than the voltage at the low-side reference terminal PI2, the drain level of the thirteenth switch transistor M13 is pulled high, the current of the sixteenth switch transistor M16 increases, the drain level of the sixteenth switch transistor M16 is pulled low, and the third inverter F3 inverts the input low level to a high level, causing the low-side output terminal DT to output a high level.

[0134] When the voltage at the low-side comparison terminal NI2 is greater than the voltage at the low-side reference terminal PI2, the drain level of the twelfth switch tube M12 is pulled high, the current of the fourteenth switch tube M14 increases, the drain level of the fourteenth switch tube M14 is pulled low, the current of the sixteenth switch tube M16 decreases, the drain level of the sixteenth switch tube M16 is pulled high, and a low level is output through the third inverter F3.

[0135] When the voltage at the low-side comparison terminal NI2 is greater than the voltage at the low-side reference terminal PI2, the signal passes through the thirteenth switch M13, the sixteenth switch M16, and the third inverter F3. When the voltage at the low-side comparison terminal NI2 is less than the voltage at the low-side reference terminal PI2, the signal passes through the twelfth switch M12, the fourteenth switch M14, the fifteenth switch M15, the sixteenth switch M16, and the third inverter F3. Therefore, when the voltage at the low-side comparison terminal NI2 is less than the voltage at the low-side reference terminal PI2, the signal passes through fewer devices, resulting in less delay and a faster response. However, when the voltage at the low-side comparison terminal NI2 is greater than the voltage at the low-side reference terminal PI2, the signal passes through more devices, resulting in greater delay and a slower response. This saves power when an excessively fast response speed is not required. Furthermore, since both the low-side comparator 300 and the high-side comparator 200 are present in this embodiment, each comparator can respond quickly when it needs to output a high level, thereby reducing delay.

[0136] In a possible embodiment, please refer to Figure 5 The low-side secondary clamping unit 330 includes: a third clamping switch tube MQ3, a fourth clamping switch tube MQ4, a fourth inverter F4 and a fifth inverter F5;

[0137] The low-side reset terminal PU is connected to the input terminal of the fourth inverter F4, the output terminal of the fourth inverter F4 is connected to the input terminal of the fifth inverter F5 and the first terminal of the third clamping switch tube MQ3, the second terminal of the third clamping switch tube MQ3 is connected to the second terminal of the sixteenth switch tube M16, and the third terminal of the third clamping switch tube MQ3 is connected to the first terminal of the sixteenth switch tube M16;

[0138] The output end of the fifth inverter F5 is connected to the first end of the fourth clamping switch tube MQ4, the second end of the fourth clamping switch tube MQ4 is connected to the preset power supply terminal VDD, and the third end of the fourth clamping switch tube MQ4 is connected to the input end of the third inverter F3.

[0139] It should be noted that the third clamping switch tube MQ3 can be an NMOS, the fourth clamping switch tube MQ4 can be a PMOS, and the second end and the third end of the third clamping switch tube MQ3 can be connected to the low-side comparison unit 320. The connection relationship between the third clamping switch tube MQ3 and the fourth clamping switch tube MQ4 and the low-side comparison unit 320 can be specifically referred to. Figure 5 The fourth inverter F4 and the fifth inverter F5 are both used for inverting input.

[0140] Reference Figure 5The clamping process of the low-side secondary clamping unit 330 is briefly described. When the low-side comparator 300 outputs a high level, the first output terminal of the control module 400 outputs a low level. The first output terminal is connected to the low-side reset terminal PU. Therefore, the low-side reset terminal PU is pulled low, the third clamping switch tube MQ3 is turned on, the sixteenth switch tube M16 is turned off, and the fourth clamping switch tube MQ4 is turned on. The second stage of the low-side comparator 300 is clamped to a low level, and the low-side output terminal DT of the low-side comparator 300 outputs a low level, thereby saving power consumption of the second stage of the low-side comparator 300. In addition, the high level output by the low-side comparator 300 and the low level output by the second-stage clamping form a narrow pulse, which can avoid output clock confusion caused by the slow falling edge of the low-side comparator 300.

[0141] It can be understood that when the first output terminal outputs a low level, both the low-side reset terminal PU and the high-side reset terminal PD are pulled low. At this time, the output of the low-side comparator 300 is clamped to a low level, while the high-side comparator 200 outputs a high level when the voltage at the high-side comparison terminal PI1 is greater than the voltage at the high-side reference terminal NI1. The high-side comparator is not clamped, that is, the high-side comparator 200 performs the comparison. When the first output terminal outputs a high level, both the low-side reset terminal PU and the high-side reset terminal PD are pulled high. At this time, the output of the high-side comparator 200 is clamped to a low level, while the low-side comparator 300 outputs a high level when the voltage at the low-side comparison terminal NI2 is less than the voltage at the low-side reference terminal PI2. That is, the low-side comparator 300 performs the comparison.

[0142] In addition, to better understand the circuit connection relationship of this embodiment, you can refer to Figure 6 , Figure 6 The overall circuit connection diagram of the relaxation oscillator is shown in Figure 6 Buffer 600 is shown in FIG. Figure 6 The VRC in ⊂ may refer to the voltage output by the filter 500 .

[0143] Further, in order to better understand this embodiment, the situation that clock disorder does not occur after the comparator is clamped at the second level is described, which can be referred to Figure 7 、 Figure 8 、 Figure 9 and Figure 10 , Figure 7 The internal structure of the control module 400 and the internal structure of the filter 500 are given in FIG. Figure 8 FIG. 1 is a waveform diagram showing the VRC waveform output by the filter 500 under ideal conditions. Figure 9 The VRC waveform diagram of the actual output of the filter 500 is shown. Figure 10 2 shows a waveform diagram of the VRC actually output by the filter 500 when the comparator has a secondary clamp and when the comparator does not have a secondary clamp.

[0144] Reference first Figure 7 ,right Figure 7 The connection relationship between the control module 400 and the filter 500 shown in FIG is briefly described. The control module 400 includes an RS latch 410, an AND gate, a sixth inverter F6, and a seventh inverter F7. The RS latch 410 includes a first NOR gate H1 and a second NOR gate H2. The first input terminal of the AND gate YM can serve as the second output terminal of the control module, the second input terminal PBD of the AND gate can serve as the preset input control terminal in the reference voltage module 100, and the output terminal of the sixth inverter F6 can serve as the first output terminal of the control module 400. The high-side output terminal GT of the high-side comparator 200 can be connected to the R terminal of the RS latch 410, and the low-side output terminal DT of the low-side comparator 300 can be connected to the S terminal of the RS latch 410. The R terminal of the RS latch 410 can serve as the first input terminal of the control module 400, and the S terminal of the RS latch 410 can serve as the second input terminal of the control module 400. The filter 500 includes a filter switch tube 510 and a first resistor R1. The source, drain, and body of the filter switch tube 510 are connected to the ground. The first resistor R1 can be a P-Poly resistor. The connection relationship between the components in the control module 400 and the filter 500 can be specifically referred to. Figure 7 , this embodiment will not go into details about this.

[0145] Reference Figure 8 , the reference voltage of the high-side comparator 200 is , the reference voltage of the low-side comparator 300 , Figure 8 VRC refers to the voltage waveform output from the voltage output terminal of the filter 500. The RC response increases to , the time consumed is the first ideal time tr, through the relaxation loop of the comparator, and then from The RC response is reduced to , the time taken is the second ideal time tf. Ideal oscillation period = tr and tf. It can be seen that ideally, the oscillation period is independent of the power supply voltage VDD and is only related to the resistor R and capacitor C in the filter 500. For example, the following formulas are given for deriving the first ideal duration and the second ideal duration, which can be referred to in Formulas 1 to 5:

[0146]

[0147]

[0148]

[0149]

[0150]

[0151] It should be noted that the ideal oscillation period is the sum of tr and tf, and e is the natural logarithm.

[0152] Refer again Figure 9 , Figure 9 The actual VRC waveform of the filter 500 is shown. In the relaxation oscillator of this embodiment, there is a comparator delay , there is a latch delay of RS latch 410 in control module 400 , inverter delay AND gate delay , when VRC is greater than When the voltage is 0, it first experiences the delay of the high-side comparator 200, and then the delay from the control module 400 back to the high-side comparator 200 is set as the first delay td1. At this time, VRC reaches the maximum value VH, and then drops to , this delay is set as the second delay td2. Similarly, when VRC is less than When the voltage is 0, it first experiences the delay of the low-side comparator 300, plus the delay of the control module 400, which is also td1. At this time, VRC reaches the minimum value VL, and then rises to , this delay is also td2. The RC response increases to , when RCln2, from The RC response is reduced to , using time RCln2. Therefore, the actual period of the oscillator =2 times the sum of RCln2, td1, and td2. For example, refer to Formulas 6 to 10, which provide the derivation process for the actual period.

[0153]

[0154]

[0155]

[0156] Formula 9:

[0157]

[0158]

[0159] It should be noted that, referring to Figure 7 , we can see that there are two inverters in the control module 400, so the first delay is twice . Figure 9 The output waveform of the clock signal is also given. It can be seen that the output period of the clock signal is also , and the high and low levels of the clock signal output will change with the jump of VRC.

[0160] Refer again Figure 10 ,exist Figure 10 Area a shows the waveforms when both the high-side comparator 200 and the low-side comparator 300 are not clamped, and area b shows the waveforms after both the high-side comparator 200 and the low-side comparator 300 are clamped at the second level, where GR can represent the level change of the high-side output terminal GT. Since the high-side output terminal GT is connected to the R end of the RS latch 410, GR can also reflect the level change of the R end of the RS latch 410; DS can represent the level change of the low-side output terminal DT. Since the low-side output terminal DT is connected to the S end of the RS latch 410, DS can also reflect the level change of the S end of the RS latch 410; QBD can refer to the level change of the first output terminal of the control module 400. The level change of the clock signal is also shown. It can be seen that the level change of the QBD output is the same as the level change of the clock signal.

[0161] Reference Figure 10 As can be seen from the a region, when the second stage of the low-side comparator 300 and the high-side comparator 200 are not dynamically clamped, when the low-side output terminal DT (ie, DS) of the low-side comparator 300 is pulled high, the output of the high-side comparator 200 (ie, GR) responds slowly and is not stable when VRC is less than 0. After that, it is not quickly pulled down, and QBD maintains its original state until GR is pulled low, and then QBD changes its state, which increases the delay, that is, Figure 10 In the figure, tdx1>td1, tdx2>td2. The area indicated by c shows that GR and DS are both high at the same time, which results in the delay becoming tdx1 and tdx2. When dynamic clamping control is added to the second stage of the high-side comparator 200 and the low-side comparator 300, when VRC is greater than After that, a narrow pulse is generated, VRC is less than After that, a narrow pulse is also generated, thereby realizing the secondary clamping of the low-side comparator 300 and the high-side comparator 200, ensuring that the RS latch 410 in each cycle is only sensitive to the rising edge, and then the latch state of the RS latch 410 can be changed by a narrow pulse, thereby making the rising delay td1 and the falling delay td2, and there will be no unstable rising delay and falling delay (for example, in Figure 10 In region a, the rising delay includes both td1 and tdx1, and the falling delay includes both td2 and tdx2, thereby ensuring the stability of the clock frequency, thereby improving the robustness of the relaxation oscillator and avoiding clock confusion.

[0162] In another possible embodiment, please refer to Figure 11 , the reference voltage module 100 further includes a preset inverting unit and a preset voltage dividing unit, the preset inverting unit is connected to the preset voltage dividing unit, and the preset voltage dividing unit is connected to the high-side reference terminal NI1 and the low-side reference terminal PI2;

[0163] The preset inverting unit includes a first preset switch tube My1 and a second preset switch tube My2, the first end of the first preset switch tube My1 and the first end of the second preset switch tube My2 are both connected to the preset input control end, the second end of the first preset switch tube My1 is connected to the preset power supply end VDD, and the third end of the first preset switch tube My1 and the second end and third end of the second preset switch tube My2 are all connected to the preset voltage dividing unit.

[0164] It should be noted that the preset inverting unit can be used to implement a soft-start process. By gradually stabilizing the high-threshold reference voltage from VDD to 2 / 3 VDD and the low-threshold reference voltage from VSS to 1 / 3 VDD, the clock signal's frequency is gradually established from low to high, reaching a target frequency to prevent digital circuit runaway. The target frequency is the desired frequency of the clock signal. The high-threshold reference voltage can be the voltage provided by the reference voltage module 100 to the high-side reference terminal NI1, and the low-threshold voltage can be the voltage provided by the reference voltage module 100 to the low-side reference terminal PI2.

[0165] The first preset switch tube My1 can be a PMOS, and the second preset switch tube My2 can be an NMOS. Since the body of the second switch tube M2 is connected to the preset low voltage terminal VSS, when PDB switches from a low level to a high level, the voltage of the second preset switch tube My2 can gradually increase without sudden changes. For example, you can refer to Figure 12 When PDB switches from a low level to a high level, the high threshold reference voltage gradually stabilizes from VDD to 2 / 3VDD, and the low threshold reference voltage gradually stabilizes from VSS to 1 / 3VDD. Then, VRC can jump back and forth between 2 / 3VDD and 1 / 3VDD, and the frequency of the clock signal can also gradually stabilize from low to high to the target frequency, thereby preventing the clock frequency of the digital circuit from being too fast when it is just connected, so as to prevent the digital circuit from running away, thereby improving the stability of the circuit.

[0166] In a possible embodiment, please refer to Figure 11 , the preset voltage dividing unit includes a first voltage dividing switch tube Mf1, a second voltage dividing switch tube Mf2 and a third voltage dividing switch tube Mf3;

[0167] A first end of the first voltage-dividing switch tube Mf1 is connected to the high-side reference terminal NI1, a second end of the first voltage-dividing switch tube Mf1 is connected to a preset power supply terminal VDD, and a third end of the first voltage-dividing switch tube Mf1 is connected to a second end of the second voltage-dividing switch tube Mf2;

[0168] The first end of the second voltage-dividing switch tube Mf2 is connected to the third end of the first preset switch tube My1 and the third end of the second preset switch tube My2, and the third end of the second voltage-dividing switch tube Mf2 is connected to the second end of the third voltage-dividing switch tube Mf3 and the low-side reference terminal PI2;

[0169] The first terminal and the third terminal of the third voltage-dividing switch tube Mf3 are both connected to the preset low voltage terminal VSS.

[0170] It should be noted that the preset voltage divider unit can provide a high-threshold reference voltage for the high-side comparator 200 and a low-threshold reference voltage for the low-side comparator 300. A first preset grounding switch transistor Md1 can be further provided between the first voltage divider switch transistor Mf1 and the high-side comparison terminal PI1, and a second preset grounding switch transistor Md2 can be further provided between the second terminal of the third voltage divider switch transistor Mf3 and the low-side reference terminal PI2. Both the first preset grounding switch transistor Md1 and the second preset grounding switch transistor Md2 can be NMOS transistors, which perform filtering and voltage stabilization functions.

[0171] The first voltage-dividing switch tube Mf1, the second voltage-dividing switch tube Mf2, and the third voltage-dividing switch tube Mf3 are of the same model and can all be PMOS transistors. The first voltage-dividing switch tube Mf1, the second voltage-dividing switch tube Mf2, and the third voltage-dividing switch tube Mf3 are connected in series to divide the voltage to obtain a high threshold reference voltage and a low threshold reference voltage.

[0172] In other embodiments, you can also refer to Figure 13 , Figure 13 FIG shows a circuit connection diagram of the reference voltage module 100 when the first voltage-dividing switch tube Mf1, the second voltage-dividing switch tube Mf2, and the third voltage-dividing switch tube Mf3 are all NMOS. When the first voltage-dividing switch tube Mf1, the second voltage-dividing switch tube Mf2, and the third voltage-dividing switch tube Mf3 are all NMOS, an inverter may be further provided between the input end of the preset inverting unit and PDB. For example, Figure 13The eighth inverter F8 in the reference voltage module 100 is configured to enable the reference voltage module 100 to input the high threshold voltage to the high-side comparison terminal PI1 and the low threshold voltage to the low-side comparison terminal NI2. When PDB is at a low level, the first preset switch tube My1 is turned off, the second preset switch tube My2 is turned on, the second voltage-dividing switch tube Mf2 is turned off, the high threshold reference voltage is VDD, and the low threshold reference voltage is VSS; when PDB is at a high level, the first preset switch tube My1 is turned on, the second preset switch tube My2 is turned off, and the gate of the second voltage-dividing switch tube Mf2 is connected to the drain. At this time, the high threshold reference becomes 2 / 3VDD, and the low threshold reference voltage becomes 1 / 3VDD. When the first voltage-dividing switch tube Mf1, the second voltage-dividing switch tube Mf2, and the third voltage-dividing switch tube Mf3 are all NMOS, the connection relationship between the voltage-dividing diodes can be referred to. Figure 13 , this embodiment does not make any specific limitation on this.

[0173] In this embodiment, a switch tube is used in the reference voltage module 100 to generate a high threshold reference voltage and a low threshold reference voltage, thereby reducing the area of ​​the reference voltage module 100 and the area of ​​the relaxation oscillator.

[0174] The motor provided in the embodiments of the present application utilizes the relaxation oscillator described in the above embodiments, aiming to address the technical issue of poor accuracy of the clock signal output by the relaxation oscillator. Compared to the prior art, the motor provided in the embodiments of the present application has the same beneficial effects as the relaxation oscillator provided in the above embodiments, and will not be further elaborated here.

[0175] The above are only preferred embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the embodiments of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent processing scope of the embodiments of the present application.

Claims

1. A relaxation oscillator, characterized in that: The relaxation oscillator includes: a reference voltage module, a high-side comparator, a low-side comparator, a control module and a filter, wherein the reference voltage module is connected to the high-side reference terminal of the high-side comparator and the low-side reference terminal of the low-side comparator, and the high-side comparison terminal of the high-side comparator and the low-side comparison terminal of the low-side comparator are connected to the voltage output terminal of the filter; The high-side output terminal of the high-side comparator and the low-side output terminal of the low-side comparator are both connected to the input terminal of the control module, and the high-side reset terminal of the high-side comparator and the low-side reset terminal of the low-side comparator are both connected to the first output terminal of the control module; The control module is used to set the high-side reset terminal to a high level when the high-side comparator outputs a high level, so as to clamp the output of the high-side comparator to a low level, so as to form a preset narrow pulse at the high-side output terminal, wherein the preset narrow pulse is composed of a low level, a high level and a low level in sequence; The control module is further configured to set the low-side reset terminal to a low level when the low-side comparator outputs a high level, so as to clamp the output of the low-side comparator to a low level, thereby forming a preset narrow pulse at the low-side output terminal; The control module is further configured to change the level of the clock signal outputted by the first output terminal when the high-side comparator outputs a high level or the low-side comparator outputs a high level.

2. The relaxation oscillator according to claim 1, wherein The high-side comparator comprises a first current source unit, a high-side comparison unit and a high-side secondary clamping unit connected in sequence; The high-side comparison unit is connected to the high-side reference terminal, the high-side comparison terminal and the high-side output terminal, the high-side secondary clamping unit is connected to the high-side reset terminal and the high-side output terminal, the first current source unit is connected to the high-side enable terminal of the high-side comparator, and the high-side enable terminal is connected to the second output terminal of the control module; The high-side comparator is configured to output a high level when the high-side enable terminal is at a high level and the voltage of the high-side comparison terminal is greater than the voltage of the high-side reference terminal; The high-side secondary clamping unit is used for clamping the high-side output terminal to a low level when the high-side reset terminal is set to a high level, so as to form a preset narrow pulse at the high-side output terminal; The first current source unit is configured to output a first preset maximum current when the high-side enable terminal is at a high level, and is also configured to output a first preset low-power consumption current when the high-side enable terminal is at a low level.

3. The relaxation oscillator according to claim 2, wherein: The first current source unit includes a first switch tube and a second switch tube; the high-side comparison unit includes a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube and a ninth switch tube; The first end of the first switch tube is connected to the high-side enable terminal, the first end of the second switch tube is connected to a first preset bias voltage, the second end of the second switch tube is connected to a preset low voltage terminal, and the third end of the second switch tube is connected to the second end of the first switch tube; The third end of the first switch tube is connected to the second end of the third switch tube and the second end of the fourth switch tube, the first end of the third switch tube is connected to the high-side reference end, and the first end of the fourth switch tube is connected to the high-side comparison end; The third end of the fourth switch tube is connected to the third end of the fifth switch tube, the second end of the fifth switch tube is connected to the second end of the sixth switch tube, the first end of the sixth switch tube is connected to the first end of the fifth switch tube, and the third end of the sixth switch tube is connected to the third end of the third switch tube; The second end of the fourth switch tube is connected to the third end of the ninth switch tube, the first end of the ninth switch tube and the first end of the seventh switch tube are both connected to a first preset bias voltage, the second end of the seventh switch tube is connected to the second end of the ninth switch tube, and the third end of the seventh switch tube is connected to the high-side output terminal and the high-side secondary clamping unit; The high-side output end is also connected to the third end of the eighth switch tube, and the first end and the second end of the eighth switch tube are both connected to the high-side secondary clamping unit.

4. The relaxation oscillator according to claim 3, wherein: The high-side secondary clamping unit includes a first clamping switch tube, a second clamping switch tube, a first inverter and a second inverter; The first end of the first clamping switch tube is connected to the output end of the first inverter, the output end of the first inverter is also connected to the input end of the second inverter, the input end of the first inverter is connected to the high-side reset end, the second end of the first clamping switch tube is connected to the second end of the eighth switch tube, and the third end of the first clamping switch tube is connected to the first end of the eighth switch tube; The output end of the second inverter is connected to the first end of the second clamping switch tube, the second end of the second clamping switch tube is connected to the preset low voltage end, and the third end of the second clamping switch tube is connected to the high-side output end.

5. The relaxation oscillator according to claim 1, wherein The low-side comparator comprises a second current source unit, a low-side comparison unit and a low-side secondary clamping unit connected in sequence; The low-side comparison unit is connected to the low-side reference terminal, the low-side comparison terminal and the low-side output terminal, the low-side secondary clamping unit is connected to the low-side reset terminal and the low-side output terminal, the second current source unit is connected to the low-side enable terminal of the low-side comparator, and the low-side enable terminal is connected to the second output terminal of the control module; The low-side comparator is configured to output a high level when the low-side enable terminal is at a low level and the voltage of the low-side comparison terminal is less than the voltage of the low-side reference terminal; The low-side secondary clamping unit is used for clamping the low-side output terminal to a low level when the low-side reset terminal is set to a low level, so as to form a preset narrow pulse at the low-side output terminal; The second current source unit is configured to output a second preset maximum current when the low-side enable terminal is at a low level, and is also configured to output a second preset low-power consumption current when the low-side enable terminal is at a high level.

6. The relaxation oscillator according to claim 5, wherein: The second current source unit includes a tenth switching tube and an eleventh switching tube; The low-side comparison unit includes: a twelfth switch tube, a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube, a sixteenth switch tube, a seventeenth switch tube, an eighteenth switch tube and a third inverter; The first end of the tenth switch tube is connected to the low-side enable terminal, the first end of the eleventh switch tube is connected to the second preset bias voltage, the second end of the eleventh switch tube is connected to the preset power supply terminal, and the third end of the eleventh switch tube is connected to the second end of the tenth switch tube; The third end of the tenth switch tube is connected to the second end of the twelfth switch tube and the second end of the thirteenth switch tube, the first end of the twelfth switch tube is connected to the low-side reference end, and the first end of the thirteenth switch tube is connected to the low-side comparison end; The third end of the thirteenth switch tube is connected to the third end of the fourteenth switch tube, the second end of the fourteenth switch tube is connected to the second end of the fifteenth switch tube, the first end of the fifteenth switch tube is connected to the first end of the fourteenth switch tube, and the third end of the fifteenth switch tube is connected to the third end of the twelfth switch tube; The second end of the twelfth switch tube is connected to the third end of the eighteenth switch tube, the first end of the eighteenth switch tube and the first end of the seventeenth switch tube are connected to a second preset bias voltage, and the second end and the third end of the seventeenth switch tube are connected to the low-side secondary clamping unit; The third end of the seventeenth switch tube is connected to the input end of the third inverter and the third end of the sixteenth switch tube, the first end and the second end of the sixteenth switch tube are connected to the low-side secondary clamping unit, and the output end of the third inverter is connected to the low-side output end.

7. The relaxation oscillator according to claim 6, wherein: The low-side secondary clamping unit includes: a third clamping switch tube, a fourth clamping switch tube, a fourth inverter and a fifth inverter; The low-side reset terminal is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is connected to the input terminal of the fifth inverter and the first terminal of the third clamping switch tube, the second terminal of the third clamping switch tube is connected to the second terminal of the sixteenth switch tube, and the third terminal of the third clamping switch tube is connected to the first terminal of the sixteenth switch tube; The output end of the fifth inverter is connected to the first end of the fourth clamping switch tube, the second end of the fourth clamping switch tube is connected to the preset power supply end, and the third end of the fourth clamping switch tube is connected to the input end of the third inverter.

8. The relaxation oscillator according to claim 1, wherein: The reference voltage module further includes a preset inverting unit and a preset voltage dividing unit, wherein the preset inverting unit is connected to the preset voltage dividing unit, and the preset voltage dividing unit is connected to the high-side reference terminal and the low-side reference terminal; The preset inverting unit includes a first preset switching tube and a second preset switching tube, the first end of the first preset switching tube and the first end of the second preset switching tube are both connected to the preset input control end, the second end of the first preset switching tube is connected to the preset power supply end, and the third end of the first preset switching tube and the second end and third end of the second preset switching tube are all connected to the preset voltage dividing unit.

9. The relaxation oscillator according to claim 8, wherein The preset voltage dividing unit includes a first voltage dividing switch tube, a second voltage dividing switch tube and a third voltage dividing switch tube; The first end of the first voltage-dividing switch tube is connected to the high-side reference end, the second end of the first voltage-dividing switch tube is connected to the preset power supply end, and the third end of the first voltage-dividing switch tube is connected to the second end of the second voltage-dividing switch tube; The first end of the second voltage-dividing switch tube is connected to the third end of the first preset switch tube and the third end of the second preset switch tube, and the third end of the second voltage-dividing switch tube is connected to the second end of the third voltage-dividing switch tube and the low-side reference end; The first end and the third end of the third voltage-dividing switch tube are both connected to a preset low voltage end.

10. A motor, characterized in that: The motor comprises the relaxation oscillator according to any one of claims 1 to 9.

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