Method and system for enhancing 5G-TSN terminal time service precision

Abstract

The invention relates to the technical field of time synchronization, in particular to a method and system for enhancing the time service precision of a 5G-TSN terminal. According to the method for enhancing the 5G-TSN terminal time service precision, a 5G system built-in mechanism is used for sending the internal time of a 5G system to a 5G double module through a base station SIB9 message, two paths of IRIG-B codes are output after errors are verified and compensated, an FPGA analysis module selects the optimal path IRIG-B code to complete analysis, and a 1PPS pulse signal and a TOD message are output through a hardware interface; and the DS-TT synchronizes UTC time packaged by an SIB9 message to a receiving port PHC in real time through internal dynamic time delay compensation and a servo adjustment algorithm, so that time synchronization from a 5G system clock to a DS-TT network bridge is realized, and the premise that 5G transmission residence time needs to be calculated in a TSN domain time synchronization process is met. According to the method and the system for enhancing the 5G-TSN terminal time service precision, high-precision time synchronization from a 5G system clock to a DS-TT network bridge is realized, and the method and the system have high controllability of resisting single-point failure and are suitable for high-precision time synchronization scenes such as 5G TSN fusion and industrial automation.

Description

Technical Field

[0001] The present invention relates to the technical field of time synchronization, and particularly relates to a method and system for enhancing the timing accuracy of 5G-TSN terminals. Background Art

[0002] Time-Sensitive Networking (TSN) is a set of IEEE802.1 standards that uses Ethernet cables to achieve deterministic network transmission. The fifth-generation mobile communication (5G) technology can effectively solve problems such as the lack of mobility and poor scalability in wired networks, which is consistent with the goals of Industry 4.0 and will become an indispensable part of future large-scale industrial communication. The 3rd Generation Partnership Project (3GPP) group is committed to making 5G real-time functions applicable to industrial applications, and a key aspect is seamless integration with TSN to establish a converged 5G-TSN network.

[0003] Time synchronization refers to the process of limiting the deviation between the clocks of devices in a system and a specific time information source within a certain range. It is a particularly important technology in distributed systems, and its purpose is to establish a global time concept with predefined accuracy by ensuring a limited maximum offset between any two nodes. In the TSN industrial network, deterministic scheduling and resource management rely on clock synchronization, requiring all nodes in the network to have a unified time scale.

[0004] The 3GPP standard and the IEEE standard have respectively conducted in-depth analyses on the integration of 5G and TSN. It is feasible to integrate 5G as a TSN logical bridge with TSN. The TSN logical bridge hides the 5G complexity by using dedicated TSN converters (TTs), achieving seamless integration of 5G and TSN. These converters provide TSN-compliant interfaces for the TSN network, and a key feature is support for the General Precision Time Protocol (gPTP) synchronization of IEEE802.1AS. The network-side TSN converter (NW-TT) and device-side TSN converter (DS-TT) introduced by 5GS as a TSN logical bridge add more uncertainties to time synchronization.

[0005] Since it is difficult to achieve high-precision time synchronization between DS-TT and NW-TT, it is difficult to accurately calculate the transmission delay between DS-TT and NW-TT.

[0006] In the existing 5G and TSN integrated networking architecture, the converter NW-TT (Network-side Time Transformer) and DS-TT (Device-side Time Transformer) accurately calculate the residence time after transmission through the 5G system by recording the ingress hardware timestamp TSi and egress hardware timestamp TSe of the gPTP event (Sync) message sent by the upstream TSN device respectively. Therefore, the internal time synchronization accuracy of the 5G system between NW-TT and DS-TT directly affects the end-to-end TSN domain time synchronization accuracy. To enhance the TSN domain time synchronization accuracy after the integration of 5G and TSN networks, it is necessary to ensure that the hardware timestamp clock sources recorded on the network side and the terminal side are consistent. Usually, the network 1588 protocol can be used for time synchronization to achieve ns-level synchronization, but it is difficult to implement due to deployment restrictions in the 5G TSN integrated network model. At present, the 3GPP standard has not proposed an effective solution to the above problems.

[0007] Based on this, the present invention proposes a method and system for enhancing the timing accuracy of 5G-TSN terminals. Summary of the Invention

[0008] In order to make up for the deficiencies of the prior art, the present invention provides a simple and efficient method and system for enhancing the timing accuracy of 5G-TSN terminals.

[0009] The present invention is implemented through the following technical solutions:

[0010] A method for enhancing the timing accuracy of 5G-TSN terminals, comprising the following steps:

[0011] Step S1: The 5G base station uses the built-in mechanism of the 5G system to encapsulate the SIB9 message containing the UTC (Coordinated Universal Time) time and perform periodic broadcasting, and sends the internal time of the 5G system to the 5G dual-mode module through the base station SIB9 message;

[0012] Step S2: After parsing the SIB9 message, the 5G dual-mode module performs verification, compensates for errors, and outputs two channels of IRIG-B codes, which are provided to the FPGA parsing module;

[0013] Step S3: After internal logic processing, the FPGA parsing module selects the optimal path IRIG-B code for parsing and outputs a 1PPS pulse signal and a TOD message through the hardware interface;

[0014] Step S4: The DS-TT time synchronization module obtains the 1PPS pulse signal and the TOD message, and through the internal dynamic delay compensation and servo adjustment algorithm, synchronizes the UTC time encapsulated in the SIB9 message to the receiving port PHC in real time to ensure that the time sources of the NW-TT sending port and the DS-TT time synchronization module receiving port are consistent;

[0015] Step S5: The DS-TT time synchronization module receives the gPTP packets in the TSN domain sent from the network side, obtains the hardware entry timestamp TSi, and at the same time obtains the hardware exit timestamp TSe from the SYNC event, calculates the 5G transmission residence time, and updates the correction field of the gPTP packet to achieve time synchronization from the TSN domain time to the DS-TT bridge or downstream nodes of the DS-TT bridge;

[0016] The calculation formula of the 5G transmission residence time is as follows:

[0017] Δt = TSe - TSi.

[0018] In step S2, there is an error in the 5G dual-mode module's and 5G base station's recognition of the reference frame boundary. The downlink transmission delay is 1 / 2 of the time advance TA. That is, the clock that the 5G dual-mode module thinks is the reference frame boundary is actually the UTC time To encapsulated in the SIB9 message plus TA / 2. Based on this, the clock of the 5G dual-mode module is adjusted to ensure alignment with the 5G dual-mode base station time.

[0019] In step S3, the FPGA parsing module uses two-channel parallel parsing of the two-channel IRIG-B codes output by the 5G module 1 and the 5G module 2, monitors the accuracy of the IRIG-B codes within a custom period, calculates the average error by statistically obtaining the time intervals generated by the edges of the IRIG-B codes in N consecutive frames, and selects the optimal path with the smallest error to parse and convert the output of the 1PPS pulse signal and TOD message.

[0020] In step S3, if the IRIG-B code output of the 5G module corresponding to the current optimal path fails, it immediately switches to the parsing and processing of the other 5G module;

[0021] If the outputs of both 5G modules fail, the local high-precision clock conversion output is enabled.

[0022] The output of the TOD message is encoded in binary. The custom data frame structure includes a frame header, message class, length, status, UTC time, date, and checksum;

[0023] Among them, the status field is used to indicate whether the current output status of the FPGA parsing module is normal and the path to which the parsed IRIG-B code belongs.

[0024] In step S4, the specific implementation process is as follows:

[0025] Step S4.1: When the 1PPS pulse signal arrives at the DS-TT time synchronization module, it triggers a hardware-level interrupt. The current PHC timestamp Tn is recorded by the underlying hardware register, and the timestamp Tn information is notified to the upper-layer program through an event.

[0026] Step S4.2: When the TOD message reaches the DS-TT time synchronization module, the upper serial port parsing thread records the current system time local_t1, starts to receive the TOD data information, and obtains the time stamp Tm associated with the 1PPS pulse signal in Step S4.1 after successful reception and verification.

[0027] Step S4.3: The upper servo adjustment thread obtains the time stamp Tn recorded in Step S4.1. After obtaining the time stamp Tm and the system time local_t1 from the serial port parsing thread, it reads the current system time local_t2 again, calculates the difference between the current system time local_t2 and the system time local_t1 to obtain the time to be compensated (internal processing time consumption) correction. The difference between the time stamps Tm and Tn is aggregated to obtain the deviation offset from the externally provided clock. The formula is as follows:

[0028] offset = Tm + correction - Tn

[0029] Step S4.4: Calculate the servo adjustment state state and the frequency compensation value ppb based on the current PHC clock Tn of the port and offset.

[0030] The specific calculation method is that the servo compares the absolute value of offset with a custom determination threshold. If it exceeds the threshold, it is determined to be in an unlocked state; otherwise, it is in a locked state.

[0031] If the state is not locked, the frequency deviation is roughly estimated through two samplings, and the time and frequency of the port are directly adjusted. The calculation formula is:

[0032] ppb = offset2 - offset1

[0033] where offset1 and offset2 are the deviations from the externally provided clock for two samplings.

[0034] If the state is locked, PI adjustment is used to finely adjust the error introduced by the frequency compensation clock drift. The calculation formula is:

[0035] ppb = Kp * offset + Ki * ∑offset

[0036] where Kp and Ki are the proportional coefficient and the integral coefficient respectively.

[0037] Step S4.5: Repeat Steps S4.1 to S4.4 to achieve real-time adjustment, lock and stably converge following the external 1PPS pulse signal and the TOD message clock source.

[0038] A system for enhancing the timing accuracy of 5G-TSN terminals, used to implement the above method, includes a 5G dual-module, an FPGA parsing module, and a DS-TT time synchronization module;

[0039] The 5G dual-module includes a 5G module 1 and a 5G module 2.

[0040] A computing device for enhancing the timing accuracy of 5G-TSN terminals, includes:

[0041] One or more processors, one or more memories, and one or more programs, where the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing any of the above methods.

[0042] A computer-readable storage medium storing one or more programs, the one or more programs include instructions, when the instructions are executed by a computing device for enhancing the timing accuracy of 5G-TSN terminals, the computing device for enhancing the timing accuracy of 5G-TSN terminals executes any of the above methods.

[0043] The beneficial effects of the present invention are: The method and system for enhancing the timing accuracy of 5G-TSN terminals not only achieve the bridge synchronization of the 5G system clock to the DS-TT time synchronization module, but also have the ability to resist single-point failure, improve reliability, reduce latency, and are applicable to high-precision time synchronization scenarios such as 5G TSN fusion and industrial automation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0045] Attached Figure 1 It is a schematic diagram of the system architecture for enhancing the timing accuracy of 5G-TSN terminals of the present invention.

[0046] Attached Figure 2 It is a schematic diagram of the FPGA parsing execution process of the present invention.

[0047] Attached Figure 3 It is a schematic diagram of the TOD data frame structure output by the FPGA parsing module of the present invention.

[0048] Attached Figure 4 It is a schematic diagram of the DS-TT time synchronization compensation adjustment process of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative work shall fall within the scope of protection of the present invention.

[0050] The method for enhancing the timing accuracy of 5G-TSN terminals includes the following steps:

[0051] Step S1: The 5G base station uses the built-in mechanism of the 5G system to encapsulate the SIB9 message containing UTC (Coordinated Universal Time) time and perform periodic broadcasting, and sends the internal time of the 5G system to the 5G dual-mode module through the base station SIB9 message;

[0052] Step S2: After parsing the SIB9 message, the 5G dual-mode module performs verification, compensates for errors, and outputs two-channel IRIG-B codes, which are provided to the FPGA parsing module;

[0053] Step S3: After internal logic processing, the FPGA parsing module selects the optimal path IRIG-B code for parsing and outputs a 1PPS pulse signal and a TOD message through the hardware interface;

[0054] Step S4: The DS-TT time synchronization module obtains the 1PPS pulse signal and the TOD message, and through the internal dynamic delay compensation and servo adjustment algorithm, synchronizes the UTC time encapsulated in the SIB9 message to the receiving port PHC in real time to ensure that the time sources of the NW-TT sending port and the DS-TT time synchronization module receiving port are the same;

[0055] Step S5: The DS-TT time synchronization module receives the gPTP message in the TSN domain sent from the network side, obtains the hardware entry timestamp TSi, and at the same time obtains the hardware exit timestamp TSe from the SYNC event, calculates the 5G transmission residence time, and updates the correction field field of the gPTP message to achieve the time synchronization from the TSN domain time to the DS-TT bridge or the downstream node of the DS-TT bridge;

[0056] The calculation formula for the 5G transmission residence time is as follows:

[0057] Δt = TSe - TSi.

[0058] In step S2, there is an error in the 5G dual-module's and 5G base station's perception of the reference frame boundary. The downlink transmission delay is 1 / 2 of the time advance TA. That is, the clock that the 5G dual-module thinks is the reference frame boundary is actually the UTC time To encapsulated in the SIB9 message plus TA / 2. Based on this, the clock of the 5G dual-module is adjusted to ensure alignment with the 5G base station time.

[0059] In step S3, the FPGA parsing module uses dual-channel parallel parsing of the two-channel IRIG-B codes output by 5G module 1 and 5G module 2, and monitors the accuracy of the IRIG-B codes within a custom period. The average error is calculated by statistically obtaining the time intervals generated by the edges of the IRIG-B codes in consecutive N frames, and the optimal path with the smallest error is selected to parse and convert the output of the 1PPS pulse signal and TOD message.

[0060] In step S3, if the IRIG-B code output of the 5G module corresponding to the current optimal path fails, it is immediately switched to the parsing and processing of the other 5G module.

[0061] If the outputs of both 5G modules fail, the local high-precision clock conversion output is enabled.

[0062] The output of the TOD message is encoded in binary, and the custom data frame structure is as shown in the appendix Figure 3 and includes a frame header, message type, length, status, UTC time, date, and checksum.

[0063] Among them, the status field is used to indicate whether the current output status of the FPGA parsing module is normal and the path to which the parsed IRIG-B code belongs.

[0064] In step S4, the specific implementation process is as follows:

[0065] Step S4.1: When the 1PPS pulse signal arrives at the DS-TT time synchronization module, a hardware-level interrupt is triggered. The current PHC timestamp Tn is recorded by the underlying hardware register, and the timestamp Tn information is notified to the upper-layer program through an event.

[0066] Step S4.2: When the TOD message arrives at the DS-TT time synchronization module, the upper-layer serial port parsing thread records the current system time local_t1, starts receiving TOD data information, and after receiving and passing the verification, obtains the timestamp Tm associated with the 1PPS pulse signal in step S4.1.

[0067] Step S4.3: The upper-layer servo adjustment thread obtains the timestamp Tn recorded in step S4.1. After obtaining the timestamp Tm and the system time local_t1 from the serial port parsing thread, it reads the current system time local_t2 again, calculates the difference between the current system time local_t2 and the system time local_t1 to obtain the time to be compensated (internal processing time) correction. Combine the difference between the timestamps Tm and Tn to obtain the deviation offset from the externally provided clock. The formula is as follows:

[0068] offset = Tm + correction - Tn

[0069] Step S4.4: Calculate the servo adjustment state state and the frequency compensation value ppb according to the current PHC clock Tn of the port and offset;

[0070] The specific calculation method is that the servo compares the absolute value of offset with a custom determination threshold. If it exceeds the threshold, it is determined to be in an unlocked state; otherwise, it is in a locked state;

[0071] If the state is not locked, roughly estimate the frequency deviation through two samplings and directly adjust the time and frequency of the port. The calculation formula is:

[0072] ppb = offset2 - offset1

[0073] where offset1 and offset2 are the deviations from the externally provided clock for two samplings;

[0074] If the state is locked, PI adjustment is used to fine-tune the error introduced by clock drift through frequency compensation. The calculation formula is:

[0075] ppb = Kp * offset + Ki * ∑offset

[0076] where Kp and Ki are the proportionality coefficient and the integral coefficient respectively;

[0077] Step S4.5: Repeat steps S4.1 to S4.4 to achieve real-time adjustment, follow the external 1PPS pulse signal and lock and stably converge with the TOD message clock source.

[0078] The system for enhancing the timing accuracy of 5G-TSN terminals to implement the above method includes a 5G dual-module, an FPGA parsing module, and a DS-TT time synchronization module;

[0079] The 5G dual-module includes a 5G module 1 and a 5G module 2.

[0080] The computing device for enhancing the timing accuracy of 5G-TSN terminals includes:

[0081] One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for performing any of the above methods.

[0082] A computer-readable storage medium storing the one or more programs, the one or more programs including instructions that, when executed by a computing device for enhancing the time synchronization accuracy of a 5G-TSN terminal, cause the computing device for enhancing the time synchronization accuracy of the 5G-TSN terminal to perform any of the above methods.

[0083] The above-described embodiments are merely one of the specific implementation manners of the present invention, and ordinary changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for enhancing the timing accuracy of 5G-TSN terminals, characterized in that: It includes the following steps: Step S1: The 5G base station uses the built-in mechanism in the 5G system to encapsulate the SIB9 message containing the UTC time and perform periodic broadcasting, and sends the internal time of the 5G system to the 5G dual-mode module through the base station SIB9 message; Step S2: After parsing the SIB9 message, the 5G dual-mode module performs verification, compensates for errors, and outputs two-channel IRIG-B codes, which are provided to the FPGA parsing module; Step S3: After internal logic processing, the FPGA parsing module selects the optimal path IRIG-B code for parsing and outputs a 1PPS pulse signal and a TOD message through the hardware interface; Step S4: The DS-TT time synchronization module obtains the 1PPS pulse signal and the TOD message, and through the internal dynamic delay compensation and servo adjustment algorithm, synchronizes the UTC time encapsulated in the SIB9 message to the receiving port PHC in real time to ensure that the time sources of the NW-TT sending port and the DS-TT time synchronization module receiving port are the same; Step S5: The DS-TT time synchronization module receives the gPTP message in the TSN domain sent from the network side, obtains the hardware entry timestamp TSi, and at the same time obtains the hardware exit timestamp TSe from the SYNC event, calculates the 5G transmission residence time, and updates the correction field field of the gPTP message to achieve time synchronization from the TSN domain time to the DS-TT bridge or the downstream node of the DS-TT bridge; The calculation formula of the 5G transmission residence time is as follows: Δt = TSe - TSi.

2. The method for enhancing the timing accuracy of a 5G-TSN terminal according to claim 1, wherein: In the step S2, there is an error in the understanding of the reference frame boundary between the 5G dual-mode module and the 5G base station. The downlink transmission delay is 1 / 2 of the time advance TA, that is, the clock of the reference frame boundary considered by the 5G dual-mode module is actually the UTC time To encapsulated in the SIB9 message plus TA / 2. Accordingly, the clock of the 5G dual-mode module is adjusted to ensure alignment with the time of the 5G dual-mode base station.

3. The method for enhancing the timing accuracy of a 5G-TSN terminal according to claim 1, characterized in that: In the step S3, the FPGA parsing module uses two-channel parallel parsing of the two-channel IRIG-B codes output by the 5G module 1 and the 5G module 2, monitors the accuracy of the IRIG-B codes within a custom period, calculates the average error by statistically obtaining the time intervals generated by the edges of the IRIG-B codes in consecutive N frames, and selects the optimal path with the smallest error for parsing and converting to output a 1PPS pulse signal and a TOD message.

4. The method for enhancing the timing accuracy of a 5G-TSN terminal according to claim 3, wherein: In the step S3, if the IRIG-B code output of the 5G module corresponding to the current optimal path fails, it immediately switches to the parsing and processing of the other 5G module; If the outputs of both 5G modules fail, the local high-precision clock is enabled for conversion and output.

5. The method for enhancing the timing accuracy of a 5G-TSN terminal according to claim 3, wherein: The output of the TOD message is encoded in binary, and the custom data frame structure includes a frame header, a message class, a length, a status, a UTC time, a date, and a checksum; Among them, the status field is used to characterize whether the current output status of the FPGA parsing module is normal and the path to which the parsed IRIG-B code belongs.

6. The method for enhancing the timing accuracy of a 5G-TSN terminal according to claim 5, wherein: In the step S4, the specific implementation process is as follows: Step S4.1: When the 1PPS pulse signal arrives at the DS-TT time synchronization module, a hardware-level interrupt is triggered. The underlying hardware register records the current PHC timestamp Tn, and the timestamp Tn information is notified to the upper-layer program through an event. Step S4.2: When the TOD message arrives at the DS-TT time synchronization module, the upper-layer serial port parsing thread records the current system time local_t1, starts to receive TOD data information, and obtains the timestamp Tm associated with the 1PPS pulse signal in Step S4.1 after receiving and passing the verification. Step S4.3: The upper-layer servo adjustment thread obtains the timestamp Tn recorded in Step S4.

1. When the timestamp Tm and the system time local_t1 are obtained from the serial port parsing thread, the current system time local_t2 is read again, and the difference between the current system time local_t2 and the system time local_t1 is calculated to obtain the time to be compensated correction. The difference between the timestamp Tm and Tn is aggregated to obtain the deviation offset from the externally provided clock. The formula is as follows: offset = Tm + correction - Tn Step S4.4: Calculate the servo adjustment state state and the frequency compensation value ppb according to the current PHC clock Tn of the port and offset. The specific calculation method is that the servo compares the absolute value of offset with a custom determination threshold. If it exceeds the threshold, it is determined to be in an unlocked state, otherwise it is in a locked state. If the state is not locked, the frequency deviation is roughly estimated by two samplings, and the time and frequency of the port are directly adjusted. The calculation formula is: ppb = offset2 - offset1 where offset1 and offset2 are the deviations from the externally provided clock for the two samplings. If the state is locked, PI adjustment is used to fine-tune the error introduced by the frequency compensation clock drift. The calculation formula is: ppb = Kp * offset + Ki * ∑offset where Kp and Ki are the proportional coefficient and the integral coefficient respectively. Step S4.5: Repeat Steps S4.1 to S4.4 to achieve real-time adjustment, and lock and stably converge following the external 1PPS pulse signal and TOD message clock source.

7. A system for enhancing the timing accuracy of 5G-TSN terminals, characterized in that: A device for implementing the method according to any one of claims 1 to 6, comprising a 5G dual-module, an FPGA parsing module, and a DS-TT time synchronization module. The 5G dual-module includes a 5G module 1 and a 5G module 2.

8. A computing device for enhancing the timing accuracy of 5G-TSN terminals, characterized in that: Comprising: One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors. The one or more programs include instructions for executing the method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing one or more programs, characterized in that: The one or more programs include instructions that, when executed by a computing device for enhancing the time synchronization accuracy of a 5G-TSN terminal, cause the computing device for enhancing the time synchronization accuracy of a 5G-TSN terminal to execute the method according to any one of claims 1 to 6.

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