An intelligent control multi-layer circuit board

Abstract

The present invention belongs to the field of electronic circuit integration technology, and in particular relates to an intelligent control multi-layer circuit board. It includes a multi-layer composite structure, which includes, stacked from top to bottom: a first signal layer, which is a copper layer with a thickness of 2μm; a first dielectric layer, which is arranged below the first signal layer; a second signal layer, which is a copper layer with a thickness of 2μm, which is arranged below the first dielectric layer and is used for medium-frequency signal transmission; an intelligent dielectric layer, which is arranged below the second signal layer; a third signal layer, which is arranged below the intelligent dielectric layer; a second dielectric layer; a fourth signal layer, which is arranged below the second dielectric layer; a substrate layer, which is arranged below the fourth signal layer and has a bionic spider web support structure on its surface; and the dielectric constant of the multi-layer circuit board is distributed in a gradient along the thickness direction. It realizes real-time dynamic adjustment of the dielectric properties of the circuit board, can optimize electromagnetic performance according to different operating frequencies or signal requirements, and significantly improves the signal transmission quality in high-frequency / high-speed scenarios.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit integration, and in particular relates to an intelligent control multi-layer circuit board. Background Art

[0002] Currently, multi-layer PCB technology faces the following three major technical bottlenecks.

[0003] 1. Static dielectric distribution: Existing regionalized dielectric designs can only achieve planar material distribution and cannot adapt to electromagnetic requirements under dynamic working conditions.

[0004] 2. Thermal-electrical coupling imbalance: The thermal expansion coefficients of high-dielectric materials (such as BaTiO3) and low-dielectric materials (such as PTFE) differ significantly, leading to interlayer cracking. For example, when thermal stress exceeds 200 MPa, the failure rate can reach as high as 15%.

[0005] 3. Nanoscale loss of control: Traditional manufacturing processes have difficulty achieving precision control of dielectric layers less than 100nm, resulting in severe high-frequency signal loss. For example, the insertion loss exceeds 3dB / cm at 10GHz.

[0006] The above problems limit the performance of PCBs in high-frequency / high-speed scenarios and urgently need innovative technologies to solve them. Summary of the Invention

[0007] The present invention aims to address the defects of the prior art and provides an intelligent control multi-layer circuit board.

[0008] To achieve the above-mentioned object, the present invention adopts the following technical solution: an intelligent control multi-layer circuit board, comprising a multi-layer composite structure, wherein the multi-layer composite structure comprises:

[0009] The first signal layer is a copper layer with a thickness of 2 μm and a line width of 20 μm, and is used for high-frequency signal transmission.

[0010] The first dielectric layer is arranged below the first signal layer and is a fixed dielectric layer made of PTFE with a dielectric constant ε_r=3 and a thickness of 0.5 mm.

[0011] The second signal layer is arranged below the first dielectric layer and is a copper layer with a thickness of 2 μm, and is used for medium frequency signal transmission.

[0012] The smart dielectric layer is arranged below the second signal layer and has a thickness of 0.8 mm. The dielectric constant of the smart dielectric layer is adjusted in real time by an external control signal, and the adjustable range of the dielectric constant of the smart dielectric layer is ε_r=12 to 20.

[0013] The third signal layer is provided below the smart dielectric layer and is a copper layer with a thickness of 2 μm, and is used for low-frequency signal transmission.

[0014] The second dielectric layer is arranged below the third signal layer and is a fixed dielectric layer with a dielectric constant ε_r=25 and a thickness of 0.5 mm.

[0015] The fourth signal layer is disposed below the second dielectric layer and is a copper layer with a thickness of 2 μm, and is used for grounding and shielding.

[0016] The substrate layer is arranged below the fourth signal layer and is an aluminum substrate with a thickness of 1.6 mm and a bionic spider web support structure on the surface.

[0017] Furthermore, the dielectric constant of the multilayer circuit board is distributed in a gradient along the thickness direction.

[0018] Furthermore, the smart dielectric layer adopts a nanocomposite material, which includes a matrix material and nanoadditives dispersed therein.

[0019] Furthermore, it also includes a control system, which includes a CMOS control chip and a microelectrode, wherein the CMOS control chip is used to output a DC voltage of 0-10V; the microelectrode is connected to the CMOS control chip to apply the DC voltage to the smart dielectric layer; wherein the smart dielectric layer realizes real-time adjustment of the dielectric constant by applying a 5V bias voltage.

[0020] Furthermore, the nano-additive is PVDF-wrapped BaTiO3 nanowires with a diameter of 50nm and an aspect ratio of 20:1; the matrix material is strontium niobate-doped titanate (Nb-SrTiO3) with a basic dielectric constant ε_r=15.

[0021] Furthermore, the first signal layer, the second signal layer, the third signal layer and the fourth signal layer are electrically connected to adjacent dielectric layers or smart dielectric layers through micropores, and the diameter of the micropores is 10 μm.

[0022] Furthermore, the bionic spider web support structure of the substrate layer is a micropore array formed by an ultraviolet laser etching process. The parameters of the ultraviolet laser etching process include: laser wavelength of 355nm, power of 50W, pulse frequency of 50kHz, scanning speed of 500mm / s, single etching depth of 50μm, total etching depth of 200μm, nitrogen protection is used during the etching process, and the air flow rate is 2L / min.

[0023] Compared with the prior art, the present invention has beneficial effects.

[0024] The present invention has dynamic dielectric control capabilities. By combining an intelligent dielectric layer (dielectric constant adjustable range ε_r = 12~20) with a CMOS control system, it achieves real-time dynamic adjustment of the circuit board's dielectric properties. It can optimize electromagnetic performance according to different operating frequencies or signal requirements, significantly improving signal transmission quality in high-frequency / high-speed scenarios.

[0025] The bionic spiderweb-like support structure of the substrate layer significantly reduces thermal stress concentration, minimizing localized thermal stress and reducing the risk of interlayer cracking. The nanocomposite material of the smart dielectric layer (PVDF-encapsulated BaTiO3 nanowires and a strontium niobate-doped titanate matrix) exhibits capacitance fluctuations of less than 2% within the -55°C to 200°C temperature range, ensuring reliability and stability in high-temperature environments.

[0026] The dielectric constant of the multilayer circuit board of the present invention is distributed in a gradient along the thickness direction (ε_r=3 in the surface layer to ε_r=25 in the bottom layer), which effectively reduces the impedance mismatch and reflection loss between signal layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention is further described below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following description.

[0028] Figure 1 It is a schematic diagram of the dielectric structure of the intelligently controlled multi-layer circuit board.

[0029] Figure 2 is a schematic diagram of the smart dielectric layer.

[0030] Figure 3 It is a schematic diagram of the bionic spider web support structure of the substrate layer.

[0031] Figure 4a This is a comparison chart of insertion loss in performance testing.

[0032] Figure 4b This is a graph showing the change of dielectric constant with voltage during performance testing.

[0033] Figure 4c This is a graph showing capacitance fluctuations versus temperature during performance testing. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and beneficial effects of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0035] Core layer structure: Intelligent control multi-layer circuit board, including a multi-layer composite structure, which is stacked from top to bottom: the first signal layer, which is a copper layer with a thickness of 2μm, a line width of 20μm and a spacing of 25μm, used for high-frequency signal transmission; the first dielectric layer, arranged below the first signal layer, is a fixed dielectric layer of PTFE material with a dielectric constant ε_r=3 and a thickness of 0.5mm; the second signal layer, arranged below the first dielectric layer, is a copper layer with a thickness of 2μm, used for medium-frequency signal transmission; the intelligent dielectric layer, arranged below the second signal layer, is 0.8mm thick, and the dielectric constant of the intelligent dielectric layer is externally controlled The signal is adjusted in real time, and the dielectric constant of the smart dielectric layer is adjustable in the range of ε_r=12 to 20; the third signal layer is arranged below the smart dielectric layer, which is a copper layer with a thickness of 2μm and is used for low-frequency signal transmission; the second dielectric layer is arranged below the third signal layer, which is a fixed dielectric layer with a dielectric constant ε_r=25 and a thickness of 0.5mm; the fourth signal layer is arranged below the second dielectric layer, which is a copper layer with a thickness of 2μm and is used for grounding and shielding; the substrate layer is arranged below the fourth signal layer, which is an aluminum substrate with a thickness of 1.6mm and a bionic spider web support structure on the surface; and the dielectric constant of the multi-layer circuit board is distributed in a gradient along the thickness direction. Figure 1 As shown in the figure, the multilayer composite structure realizes adaptive optimization of the electromagnetic field by distributing the dielectric constant gradient along the Z-axis (ε_r gradually changes from 3 to 25).

[0036] like Figure 2 As shown, the smart dielectric layer is introduced as follows: 1. The smart dielectric layer adopts nanocomposite material, the matrix of which is strontium niobate titanate (Nb-SrTiO3, ε_r=15), and PVDF-wrapped BaTiO3 nanowires (diameter 50nm, aspect ratio 20:1) are dispersed.

[0037] 2. The smart dielectric layer control mechanism is as follows: a 0-10V DC voltage (0.1V step, response time <1ms) is output through a CMOS control chip and applied to the microelectrodes (copper, 50μm×50μm) on both sides of the smart dielectric layer, driving the BaTiO3 nanowires to align along the electric field, thereby achieving dynamic regulation of the dielectric constant (ε_r=12~20).

[0038] 3. Manufacturing process: BaTiO3 nanowires are synthesized by a solvothermal method (reaction conditions: 180°C, 12 hours). PVDF (concentration 10wt%) is then uniformly coated on the surface of the nanowires by solution coating. The coating thickness is approximately 5nm. The drying temperature is 80°C and the drying time is 2 hours to ensure the uniformity of the dispersion of the nanowires in the matrix (standard deviation <10%).

[0039] like Figure 3The structure and principle of the bionic spiderweb support layer are as follows: the substrate layer is etched using UV laser to form a bionic spiderweb micropore array. The micropore parameters are: 50μm diameter, 200μm spacing, 60° staggered arrangement, and 200μm etching depth. The micropore array covers the entire substrate surface, forming a spiderweb structure. Simulation results show that thermal stress is reduced from a localized concentrated value of 200MPa to an average of 45MPa, and the stress gradient at the micropore edges is reduced by 50%, effectively preventing interlayer cracking.

[0040] The bionic spiderweb support layer structure is created using a 355nm UV laser to etch micropores into the aluminum substrate. Specifically, a 355nm UV laser with 50W power, 50kHz pulse frequency, and a scanning speed of 500mm / s was used. A single etching depth of 50μm was achieved through four cycles, with a total depth of 200μm. Nitrogen protection was used during the etching process at a flow rate of 2L / min to prevent oxidation and thermal damage.

[0041] Example 1, millimeter wave radar PCB: adopts an 8-layer composite structure with a total thickness of 3.2 mm; dielectric gradient: the surface layer is made of PTFE (ε_r=3), and the bottom layer is a BaTiO3 composite material (ε_r=25).

[0042] The manufacturing process is as follows: Step 1: Substrate pretreatment: A bionic spider web support structure is formed on an aluminum substrate using laser etching with an etching depth of 200 μm.

[0043] Step 2: ALD deposition: A composite dielectric layer of Ta2O5 (50nm thickness) and Al2O3 (20nm thickness) was sequentially deposited to form a base interface. Using a thermal ALD tool (such as the Oxford FlexAL), Ta2O5 was deposited using a precursor of tantalum pentaethoxide (Ta(OC2H5)5) and water vapor at 250°C. 0.3nm was deposited per cycle for 167 cycles, resulting in a total thickness of 50nm. Al2O3 was deposited using a precursor of trimethylaluminum (TMA) and water vapor at 200°C. 0.3nm was deposited per cycle for 67 cycles, resulting in a total thickness of 20nm. Vacuum was maintained at 10⁻² Torr to ensure layer thickness uniformity (±1nm).

[0044] Step 3: Nanocompositing: Spray-coat a PVDF solution containing 5 vol% BaTiO3 nanowires (particle size distribution D50 = 80 nm). Use an ultrasonic sprayer (such as the Sono-Tek ExactaCoat) to apply a 10 wt% PVDF solution containing 5 vol% BaTiO3 nanowires in DMF at a pressure of 0.1 MPa, a nozzle diameter of 0.5 mm, and a spray speed of 10 cm / s. Each spray should be 10 μm thick, and eight sprays should be applied to achieve a total thickness of 80 μm. Curing should be performed in a vacuum oven at 120°C for 30 minutes at a pressure of 10⁻¹ Torr to ensure complete evaporation of the solution.

[0045] Step 4: Intelligent integration: Embed a CMOS control chip (size 1mm×1mm, power consumption less than 10mW) and communicate with the main control system through the I2C interface.

[0046] The function of the CMOS control chip is to receive instructions from the main control system, output a 0-10V DC voltage, and apply it to the microelectrodes on both sides of the fourth dielectric layer to achieve dynamic adjustment of the dielectric constant.

[0047] Implementation: A. A CMOS chip is soldered to a reserved pad on the first signal layer. A CMOS chip (e.g., TI DRV8833, 1mm x 1mm, power consumption <10mW) is soldered to the reserved pad on the first signal layer using reflow soldering at 260°C for 10 seconds using lead-free solder (Sn96.5Ag3Cu0.5). The chip pins are connected to the microelectrodes on the third and fifth layers via 0.1mm diameter copper wires using ultrasonic welding with a strength of >5N.

[0048] B. Connect the chip output to the microelectrodes of the 3rd and 5th signal layers through copper wires.

[0049] C. The main control system sends an I2C signal to the CMOS chip, specifying a voltage value of 0-10V.

[0050] D. The CMOS chip applies a voltage signal to the dielectric layer to control the arrangement of the nanowires.

[0051] The performance tests are:

[0052] High frequency performance: such as Figure 4a As shown in the figure, high-frequency performance was tested using a vector network analyzer (Keysight N5247B) in the 1-40 GHz frequency range. The test sample was a 50 mm long straight transmission line, operating at an ambient temperature of 25°C ± 2°C and a humidity of 50% ± 5%. The results showed an insertion loss of 0.8 dB / cm, compared to 3 dB / cm for traditional PCBs, a performance improvement of approximately 62%.

[0053] Dynamic adjustment: such as Figure 4b As shown, use an LCR meter (such as Keysight E4980A) to measure the dielectric constant. Apply a 0-10V bias with a 0.5V step and a frequency of 1kHz. Measure the capacitance change to calculate ε_r. The response time is <0.5s, and the stable adjustment range is ε_r = 15±0.2 at a 5V bias.

[0054] Thermal stability: Figure 4c As shown, the capacitance fluctuation in the -55°C to 200°C range is less than 2%, significantly superior to conventional materials. Thermal stability was tested in an environmental chamber with a temperature range of -55°C to 200°C, a heating rate of 2°C / min, a holding time of 1 hour per temperature point, 5 cycles, and 10 test samples. The average capacitance fluctuation was 1.8%, with a standard deviation of <0.3%.

[0055] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "preferred embodiments," "specific implementations," or "preferred implementations" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, illustrative uses of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solutions described in the above embodiments may still be modified, or some or all of the technical features thereof may be replaced by equivalents. Therefore, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope defined by the claims of the present invention.

Claims

1. An intelligent control multi-layer circuit board, comprising a multi-layer composite structure, characterized in that: The multi-layer composite structure includes the following layers stacked from top to bottom: The first signal layer is a 2μm thick copper layer with a 20μm line width, used for high-frequency signal transmission; The first dielectric layer is provided below the first signal layer and is a fixed dielectric layer made of PTFE with a dielectric constant ε_r=3 and a thickness of 0.5 mm; The second signal layer is provided below the first dielectric layer and is a copper layer with a thickness of 2 μm, and is used for medium frequency signal transmission; A smart dielectric layer is provided below the second signal layer and has a thickness of 0.8 mm. The dielectric constant of the smart dielectric layer is adjusted in real time by the control signal, and the dielectric constant of the smart dielectric layer is adjustable in the range of ε_r = 12 to 20. The third signal layer is provided below the smart dielectric layer and is a 2μm thick copper layer used for low-frequency signal transmission; The second dielectric layer is provided below the third signal layer and is a fixed dielectric layer with a dielectric constant ε_r = 25 and a thickness of 0.5 mm; The fourth signal layer is provided below the second dielectric layer and is a 2 μm thick copper layer used for grounding and shielding. The substrate layer is arranged below the fourth signal layer. It is an aluminum substrate with a thickness of 1.6 mm and a bionic spider web support structure on the surface. The bionic spider web support structure of the substrate layer is a micropore array formed by an ultraviolet laser etching process; and the dielectric constant of the multilayer circuit board is gradiently distributed along the thickness direction.

2. The intelligent control multi-layer circuit board according to claim 1, characterized in that: The smart dielectric layer adopts a nanocomposite material, which includes a matrix material and nano additives dispersed therein.

3. The intelligent control multi-layer circuit board according to claim 1, characterized in that: It also includes a control system, which includes a CMOS control chip and a microelectrode, wherein the CMOS control chip is used to output a DC voltage of 0-10V; the microelectrode is connected to the CMOS control chip and is used to apply the DC voltage to the smart dielectric layer; wherein the smart dielectric layer realizes real-time adjustment of the dielectric constant by applying a 5V bias voltage.

4. The intelligent control multi-layer circuit board according to claim 2, characterized in that: The nano-additive is PVDF-wrapped BaTiO3 nanowires with a diameter of 50nm and an aspect ratio of 20:1; the matrix material is niobium-doped strontium titanate with a basic dielectric constant ε_r=15.

5. The intelligent control multi-layer circuit board according to claim 1, characterized in that: The first signal layer, the second signal layer, the third signal layer and the fourth signal layer are electrically connected to adjacent dielectric layers or smart dielectric layers through micropores, and the diameter of the micropores is 10 μm.

6. The intelligent control multi-layer circuit board according to claim 1, characterized in that: The parameters of the UV laser etching process include: laser wavelength of 355 nm, power of 50 W, pulse frequency of 50 kHz, scanning speed of 500 mm / s, single etching depth of 50 μm, total etching depth of 200 μm, nitrogen protection is used during the etching process, and the air flow rate is 2 L / min.

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