Back contact battery and its preparation method

Abstract

This application belongs to the field of solar cells and relates to a back contact cell and its fabrication method, which can improve conversion efficiency. The back contact cell includes: a semiconductor substrate, including a front side and a back side; a first semiconductor layer and a second semiconductor layer, which are alternately arranged on the back side along the X-axis direction, the edges of the first semiconductor layer and the edges of the second semiconductor layer form an overlapping area in the Z-axis direction, a first groove is formed between adjacent second semiconductor layers, the outer surface of the second semiconductor layer has a second groove, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; a conductive film layer is disposed on the outer surface of the first groove, the second groove and the overlapping area, wherein, corresponding to the bottom of the second groove, two first isolation areas are spaced apart on the conductive film layer, and each first isolation area includes at least one first isolation groove spaced apart along the X-axis direction.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a back contact cell and its preparation method. Background Technology

[0002] Conventional hybrid back-contact batteries have alternating first-region semiconductor layers, mainly consisting of tunneling oxide / doped polycrystalline silicon layers, and second-region semiconductor layers, mainly consisting of intrinsic amorphous silicon / doped amorphous silicon layers, on the back of the battery. Each region of the semiconductor layer is connected to a transparent electrode.

[0003] The related technology mentioned in Chinese patent CN117577709B is a back contact battery, whose transparent conductive layer has an isolation area as shown in the figure. Figure 8 As shown in Wa, the isolation region spans part of the p region ( Figure 8 The edge of W2 region and the edge of n region (in the middle) Figure 8 The W1 region and the overlapping region are included. However, this method results in a significant loss of transparent conductive layer area. In addition, the removal of the transparent conductive layer can easily cause etching of the underlying film, reducing battery efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a back-contact battery that can improve the conversion efficiency of the battery. Furthermore, a method for preparing a back-contact battery is also proposed.

[0005] In a first aspect, a back-contact battery is provided, comprising: a semiconductor substrate including a front side and a back side; a first semiconductor layer and a second semiconductor layer, alternately arranged on the back side along the X-axis direction, wherein the edges of the first semiconductor layer and the edges of the second semiconductor layer form an overlapping area in the Z-axis direction, a first groove is formed between adjacent second semiconductor layers, the outer surface of the second semiconductor layer has a second groove, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; and a conductive film layer disposed on the outer surface of the first groove, the second groove and the overlapping area, wherein, corresponding to the bottom of the second groove, two first isolation areas are spaced apart on the conductive film layer, each first isolation area including at least one first isolation groove spaced apart along the X-axis direction.

[0006] In some embodiments, along the X-axis direction, the distance between two adjacent first isolation slots in the same first isolation region is 5-15 μm.

[0007] In some embodiments, in the same second groove, the second semiconductor layer between the two first isolation regions includes a crystallized microcrystalline silicon region, and the distance between the crystallized microcrystalline silicon region and any of the first isolation regions along the X-axis direction is less than 5 μm.

[0008] In some embodiments, the opposite side walls of the second groove are slopes biased towards the top of the overlapping area. Along the X-axis, the width of the overlapping area is 10-160 μm, the width of the slope is 5-20 μm, the width of the first isolation groove is 35-80 μm, and the width of the crystallized microcrystalline silicon region is 300-600 μm.

[0009] In some embodiments, the second semiconductor layer between the two first isolation regions in the same second groove is an amorphous silicon region.

[0010] In some embodiments, the opposite side walls of the second groove are slopes biased towards the top of the overlapping area. In the X-axis direction, in the same second groove, the two first isolation areas are close to one of the slopes, the starting points of the two first isolation areas are relatively far apart, the ending points of the two first isolation areas are relatively close, and the distance between the starting point of any first isolation area and the bottom of the adjacent slope is 0-3 μm.

[0011] In some embodiments, the conductive film layer has a second isolation region at the top position of the overlapping region, and the second isolation region includes at least one second isolation groove spaced apart along the X-axis direction.

[0012] In some embodiments, the width of the second isolation groove along the X-axis direction is 0-80 μm.

[0013] In some embodiments, the distance between two adjacent second isolation slots within the same second isolation zone is 10-30 μm.

[0014] In some embodiments, the conductive film layer has a third isolation area at the position corresponding to the sidewall of the second groove.

[0015] In a second aspect, this application provides a method for fabricating a back-contact battery, comprising the following steps: Step S10, forming a first semiconductor layer and a mask layer sequentially on the back side of a semiconductor substrate; Step S20, removing the first semiconductor layer and its corresponding mask layer within a first predetermined region on the back side obtained in Step S10 to form a recessed region; Step S30, forming a textured surface at the bottom of the recessed region; Step S40, forming a second semiconductor layer on the back side obtained in Step S30, wherein a second groove is formed on the outer surface of the second semiconductor layer corresponding to the recessed region; Step S50, removing the second semiconductor layer and its corresponding mask layer within the second predetermined region on the back side obtained in Step S40 to form a first groove spaced apart from the second groove, wherein the edges of the first semiconductor layer and the edges of the second semiconductor layer form an overlapping region; Step S60, forming a conductive film layer on the back side obtained in Step S50; Step S70, etching an opening in a third predetermined region on the back side obtained in Step S60, forming two first isolation regions spaced apart on the conductive film layer at the bottom of the second groove, each first isolation region including at least one first isolation groove spaced apart along the X-axis direction.

[0016] In some embodiments, step S40 includes: forming a passivation layer on the back side obtained in step S30; and forming an amorphous silicon layer on the passivation layer.

[0017] In some embodiments, step S50 includes: removing the passivation layer and amorphous silicon layer at the first groove; and performing laser scanning on a predetermined area of ​​the amorphous silicon layer at the second groove to form a crystalline microcrystalline silicon region.

[0018] In some embodiments, the method further includes etching an opening in the fourth preset region on the back side obtained in step S60 to form a second isolation region on the conductive film layer at the top of the overlapping region.

[0019] In some embodiments, the method further includes etching an opening in the fifth preset region on the back side obtained in step S60 to form a third isolation region at the position of the conductive film layer corresponding to the sidewall of the second groove.

[0020] In this application, the first isolation region is located in the second groove on the outer surface of the second semiconductor layer, which avoids excessive etching of the conductive film layer and thus prevents a decrease in the bifaciality of the battery, thereby improving the conversion efficiency. The first isolation region causes the conductive film layer to form one or more conductive film layer islands, resulting in local leakage current in the conductive film layer at the first isolation region, which helps to reduce the hot spot effect of the back contact battery. Therefore, the back contact battery of this application can improve the conversion efficiency and reduce the hot spot effect. Attached Figure Description

[0021] Figure 1 This is a partial cross-sectional structural diagram of a back contact battery according to an embodiment of this application.

[0022] Figure 2 for Figure 1 Enlarged view of point A in the middle.

[0023] Figure 3 for Figure 1 Enlarged view of point B in the middle.

[0024] Figure 4 This is a schematic flowchart of a method for preparing a back contact battery according to an embodiment of this application.

[0025] Figure 5 This is a schematic diagram of the structure after step S10 of the preparation method of this application.

[0026] Figure 6 This is a schematic diagram of the structure after step S20 of the preparation method of this application.

[0027] Figure 7 This is a schematic diagram of the structure after step S30 of the preparation method of this application.

[0028] Figure 8 This is a schematic diagram of the structure after step S40 of the preparation method of this application.

[0029] Figure 9 This is a schematic diagram of the structure after step S50 of the preparation method of this application.

[0030] Figure 10 This is a schematic diagram of the structure after step S60 of the preparation method of this application.

[0031] Figure 11 This is a schematic diagram of the structure after step S70 of the preparation method of this application.

[0032] Figure 12 for Figure 11 A magnified view of point C in the middle.

[0033] Figure 13 This is a flowchart illustrating the implementation of step S40 in an embodiment of this application.

[0034] Figure 14 This is a flowchart illustrating the implementation of step S50 in an embodiment of this application.

[0035] Figure 15 This is a flowchart illustrating the implementation of steps S80 and S90 in the embodiments of this application.

[0036] Figure label:

[0037] 100. Back contact battery; 10. Semiconductor substrate; 101. Front side; 102. Back side; 110. Recessed area; 111. Textured surface; 20. First semiconductor layer; 210. Tunneling oxide layer; 220. Intrinsic polycrystalline silicon layer; 30. Second semiconductor layer; 301. Crystallized microcrystalline silicon region; 310. Passivation layer; 320. Amorphous silicon layer; 40. Overlapping area; 401. Top; 50. First groove; 60. Second groove; 601. Sidewall; 70. Conductive film layer; 701. Slope bottom; 710. First isolation region; 711. First isolation trench; 720. Second isolation region; 721. Second isolation trench; 730. Third isolation region; 80. Mask layer; 910. First electrode; 920. Second electrode. Detailed Implementation

[0038] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by one of ordinary skill in the art.

[0039] Additionally, unless the context otherwise indicates, the material removal described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, abrasive planarization (e.g., chemical mechanical planarization (CMP)) or other known methods.

[0040] As used herein, the term "semiconductor" can refer to, for example, a material layer, substrate, wafer, or substructure, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon sapphire (SOS) technology, silicon-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art.

[0041] The first aspect of this application, with reference to Figures 1 to 3 This application provides a back contact battery 100, which includes a semiconductor substrate 10, a first semiconductor layer 20, a second semiconductor layer 30, and a conductive film layer 70.

[0042] The semiconductor substrate 10 includes a front side 101 and a back side 102. Here, the back side 102 is the side facing away from the sun when the back contact battery 100 is in operation. The front side 101 is the side of the back contact battery 100 facing the sun when in operation. The semiconductor substrate 10 is used to receive incident light and generate photogenerated carriers. The semiconductor substrate 10 can be, for example, silicon, germanium, germanium-silicon, or silicon on an insulator, and various doped silicon materials, including, but not limited to, boron-doped, phosphorus-doped, gallium-doped, antimony-doped, or mixed-doped silicon.

[0043] A first semiconductor layer 20 and a second semiconductor layer 30 are alternately arranged on the back surface 102 along the X-axis direction. The edges of the first semiconductor layer 20 and the edges of the second semiconductor layer 30 form an overlapping area 40 in the Z-axis direction. A first groove 50 is formed between adjacent second semiconductor layers 30, and the outer surface of the second semiconductor layer 30 has a second groove 60.

[0044] The X-axis direction is parallel to the back surface 102. The Z-axis direction is perpendicular to the back surface 102. In this application, the two end edges of the second semiconductor layer 30 extend outward to cover the edge of the adjacent first semiconductor layer 20, thereby forming an overlapping region 40. The first groove 50 exposes the first semiconductor layer 20, thereby enabling it to make ohmic contact with the first electrode 910 ohms.

[0045] The conductivity type of the second semiconductor layer 30 is opposite to that of the first semiconductor layer 20. Specifically, the second semiconductor layer 30 is a P-type doped semiconductor layer, and the doping element is a P-type dopant such as boron. The first semiconductor layer 20 is an N-type doped semiconductor layer, and the doping element is an N-type dopant such as antimony.

[0046] The material of the conductive film layer 70 can refer to the corresponding types in the prior art. For example, the material of the conductive film layer 70 can be an indium oxide-based thin film doped with at least one of tin, zinc, tungsten, or titanium. The conductive film layer 70 is disposed on the outer surface of the first groove 50, the second groove 60, and the overlapping area 40. Corresponding to the bottom of the second groove 60, two first isolation areas 710 are provided on the conductive film layer 70 at intervals. Each first isolation area 710 includes at least one first isolation groove 711 spaced apart along the X-axis direction.

[0047] Specifically, the outer surface of the first groove 50 (including the bottom wall and sidewalls of the first groove 50), the surface of the second groove 60 (including the bottom and sidewall 601 of the second groove 60), and the outer surface of the overlapping region 40 are all covered with a conductive film layer 70. When the two ends of the second semiconductor layer 30 extend outward to cover the ends of the adjacent first semiconductor layer 20 to form the overlapping region 40, the second sidewall 601 of the second groove 60 is also the sidewall 601 of the overlapping region 40.

[0048] refer to Figure 1and Figure 2 In this application, two first isolation regions 710 are provided at intervals on the conductive film layer 70 at the bottom of the second groove 60. Each first isolation region 710 includes at least one first isolation groove 711. The first isolation groove 711 breaks the conductive film layer 70, forming a barrier. When multiple first isolation grooves 711 are provided in the first isolation region 710, the range of the first isolation region 710 refers to the range between the edges of the first and last first isolation grooves 711 in the same first isolation region 710 that are far apart from each other in the X-axis direction.

[0049] Compared to related technologies where the isolation region spans both the P-region and the N-region, in this application, the first isolation region 710 on the conductive film layer 70 is located in the second groove 60 on the outer surface of the second semiconductor layer 30, thus avoiding excessive etching of the conductive film layer 70 and resulting in a decrease in the bifaciality of the battery. Specifically, the second semiconductor layer 30 is a P-type semiconductor layer, the area corresponding to the second groove 60 is the P-region, and the area corresponding to the first groove 50 is the N-region. The first isolation region 710 is located in the P-region, which has poor lateral transmission, thus preventing the conductive film layer 70 in the N-region from being etched away.

[0050] Furthermore, in the X-axis direction, the first isolation groove 711 causes the conductive film layer 70 to form one or more conductive film layer islands, resulting in local leakage current in the conductive film layer 70 at the first isolation region 710, which helps to reduce the hot spot effect of the back contact battery 100. Thus, the back contact battery 100 of this application can improve conversion efficiency and reduce the hot spot effect.

[0051] In some embodiments, reference is made to Figure 1 and Figure 2 In the X-axis direction, within the same first isolation region 710, the distance d1 between two adjacent first isolation trenches 711 is 5-15 μm. The distance d1 between two adjacent first isolation trenches 711 refers to the distance between the edges of two adjacent first isolation trenches 711 that are close to each other. For example, the distance d1 between two adjacent first isolation trenches 711 is 5 μm, 10 μm, or 15 μm. This distance avoids etching away too much of the conductive film layer 70, thus preventing the formation of conductive film layer islands and localized leakage, which helps reduce the hot spot effect of the back contact battery 100.

[0052] In some embodiments, reference is made to Figure 1 and Figure 2In the same first groove 50, the second semiconductor layer 30 between the two first isolation regions 710 includes a crystallized microcrystalline silicon region 301. Along the X-axis, the distance d2 between the crystallized microcrystalline silicon region 301 and any of the first isolation regions 710 is less than 5 μm. The distance d2 between the crystallized microcrystalline silicon region 301 and the first isolation region 710 refers to the distance between the two edges of the crystallized microcrystalline silicon region 301 and the first isolation region 710 that are close to each other. This distance can specifically be 0 μm, 1 μm, 3 μm, or 5 μm, ensuring that the crystallized microcrystalline silicon region 301 has a large area.

[0053] The second semiconductor layer 30 between the two first isolation regions 710 is crystallized into a crystallized microcrystalline silicon region 301. The crystallized microcrystalline silicon region 301 can improve the contact with the conductive film layer 70, reduce the contact resistance, and thus improve the battery efficiency.

[0054] Further, refer to Figure 1 and Figure 2 The conductive film layer 70 on the opposite side walls 601 of the second groove 60 is a slope biased towards the top 401 of the overlapping region 40. Along the X-axis, the width D1 of the overlapping region 40 is 10-160μm, the width W1 of the slope is 5-20μm, the width Wa of the first isolation groove 711 is 35-80μm, and the width W2 of the crystallized microcrystalline silicon region 301 is 300-600μm.

[0055] In actual fabrication, the opposing sidewalls 601 of the second groove 60 and the conductive film layer 70 thereon form a slope. The width D1 of the overlapping region 40 is 10-160 μm, such as 10 μm, 40 μm, 60 μm, 90 μm, 130 μm, or 160 μm. The width W1 of the slope is, for example, 5 μm, 8 μm, 0 μm, 12 μm, 14 μm, 16 μm, 18 μm, or 20 μm. The width Wa of the first isolation groove 711 is, for example, 35 μm, 40 μm, 45 μm, 50 μm, 60 μm, 70 μm, or 80 μm. The width W2 of the crystallized microcrystalline silicon region 301 is, for example, 300 μm, 350 μm, 380 μm, 400 μm, 450 μm, 500 μm, 580 μm, or 600 μm. Within the aforementioned size range, it has been verified that high battery efficiency can be guaranteed, while also being patternable using etching processes.

[0056] In other embodiments, the second semiconductor layer 30 between the two first isolation regions 710 in the same first groove 50 can also be an amorphous silicon region. Since the second semiconductor layer 30 between the two first isolation regions 710 is an amorphous silicon region, it can be formed during the fabrication process, for example, through a conventional deposition process, without requiring additional processing steps, making the manufacturing process relatively simple.

[0057] In some embodiments, reference is made to Figure 1 and Figure 2The conductive film layer 70 on the opposite side walls 601 of the second groove 60 is a slope biased towards the top 401 of the overlapping region 40; in the X-axis direction, in the same second groove 60, the two first isolation regions 710 are respectively close to a slope. The starting points of the two first isolation regions 710 are relatively far apart, and the ending points of the two first isolation regions 710 are relatively close. The distance between the starting point of any first isolation region 710 and the bottom 701 of the adjacent slope is 0-3 μm.

[0058] For both first isolation zones 710, the endpoint is closer to the other first isolation zone 710 than the starting point. (Reference) Figure 1 and Figure 2 ,in Figure 2 Only enlarged illustration Figure 1 The structure of the first isolation region 710 located to the left of the second groove 60. The structure of the first isolation region 710 on the right side is symmetrical to the structure of the first isolation region 710 on the left side.

[0059] The distance between the starting point of the first isolation zone 710 on the left and the bottom of the slope 701 on the left is D2. The starting point of the first isolation zone 710 on the left is the edge of the first isolation groove 711 within the first isolation zone 710 that is closest to the bottom of the slope 701 on the left. The distance between the first isolation zone 710 on the right and the bottom of the slope 701 on the right is similar. Taking the first isolation zone 710 on the left as an example, the above distances are, for example, 0 μm, 1 μm, and 3 μm. When the distance is 0 μm, it means that the starting point of the first isolation zone 710 on the left coincides with the first end point of the second groove 60.

[0060] Through the above design, the distance between the starting point of each first isolation zone 710 and the bottom of the adjacent slope 701 is 0-3μm, which reduces the risk of leakage and keeps the local leakage within the expected range.

[0061] refer to Figures 1 to 3 As shown, the conductive film layer 70 has a second isolation region 720 at the position corresponding to the top 401 of the overlapping region 40. The second isolation region 720 includes at least one second isolation groove 721 spaced apart along the X-axis direction.

[0062] At least one second isolation region 720 is provided on the conductive film layer 70 at the top 401 of the overlapping region 40. Each second isolation region 720 includes one or more second isolation trenches 721. Along the X-axis direction, the width Wb of the second isolation trench 721 is 0-50 μm. For example, the width Wb of the second isolation trench 721 is 0 μm; 35 μm, 40 μm, 45 μm, 50 μm, 60 μm, 70 μm, 80 μm. When the width of the second isolation trench 721 is 0 μm, it means that no second isolation trench 721 is provided.

[0063] The second isolation region 720 forms a conductive film island on the top 401 of the overlapping region 40, achieving local leakage and thus helping to reduce the hot spot effect of the back contact battery 100. The width Wb of the second isolation trench 721 is 0-80μm, which can reduce the degree of etching of the conductive film layer 70 and avoid the reduction of the battery bifaciality caused by excessive etching of the transparent conductive film.

[0064] Specifically, the distance d3 between two adjacent second isolation trenches 721 is 10-30 μm. The distance d3 between two adjacent second isolation trenches 721 refers to the distance between the edges of two adjacent second isolation trenches 721 that are close to each other. For example, the distance d3 between two adjacent second isolation trenches 721 is 10 μm, 15 μm, 20 μm, 25 μm, or 30 μm. This distance avoids etching away too much of the conductive film layer 70, thus preventing the formation of multiple conductive film layer islands and localized leakage, which helps reduce the hot spot effect of the back contact battery 100.

[0065] In some embodiments, reference is made to Figure 2 A third isolation region 730 is provided at the position of the conductive film layer 70 corresponding to the side wall 601 of the first groove 50. The formation method of the third isolation region 730 can be completely similar to the formation method of the first isolation region 710 and the second isolation region 720. The third isolation region 730 forms multiple conductive film layer islands at the side wall 601 of the first groove 50, forming local leakage current, which helps to reduce the hot spot effect of the back contact battery 100 and improve the conversion efficiency of the back contact battery 100.

[0066] Secondly, this application proposes a method for preparing a back contact battery 100, which is used to prepare the aforementioned back contact battery 100.

[0067] refer to Figure 4 The method for preparing the back contact battery 100 of this application includes the following steps.

[0068] Step S10, as follows Figure 5 As shown, a first semiconductor layer 20 and a mask layer 80 are sequentially formed on the back side 102 of the semiconductor substrate 10.

[0069] Step S20, as follows Figure 6 As shown, the first semiconductor layer 20 and its corresponding mask layer 80 in the first preset area on the back side obtained in step S10 are removed to form a recessed area 110.

[0070] After removing the first semiconductor layer 20 and its corresponding mask layer 80, a recessed region 110 is formed that exposes the semiconductor substrate 10.

[0071] Step S30, Reference Figure 7A textured surface 111 is formed at the bottom of the recessed region 110. Texturing and cleaning are performed to form the textured surface 111 on the semiconductor substrate 10 in the recessed region 110.

[0072] Step S40, Reference Figure 8 A second semiconductor layer 30 is formed on the back side obtained in step S30, and a second groove 60 is formed on the outer surface of the second semiconductor layer 30 at the recessed area 110.

[0073] In this step, the second semiconductor layer 30 is formed to cover the back side 102 of the intermediate obtained in step S30. The second semiconductor layer 30 covers the sidewall 601 and bottom wall of the recessed region 110, such that the outer surface of the second semiconductor layer 30 forms a second groove 60 corresponding to the recessed region 110.

[0074] Step S50, Reference Figure 9 Remove the second semiconductor layer 30 and the mask layer corresponding to the second semiconductor layer 30 in the second preset area on the back side obtained in step S40 to form a first groove 50 that is spaced apart from the second groove 60, and the edge of the first semiconductor layer 20 and the edge of the second semiconductor layer 30 form an overlapping area 40.

[0075] In this step, a portion of the second semiconductor layer 30 is etched away, thereby exposing the underlying first semiconductor layer 20. The two end edges of the second semiconductor layer 30 respectively cover the edges of the adjacent first semiconductor layer 20, forming an overlapping region 40.

[0076] In steps S40 and S50, the formation of the first semiconductor layer 20, the second semiconductor layer 30, and the mask layer 80 can be achieved by any method corresponding to the prior art. For example, the first semiconductor layer 20 can be formed using a chemical vapor deposition process.

[0077] In steps S40 and S50, the removal of the corresponding semiconductor layer and its corresponding mask layer 80 to form the corresponding recessed area 110 and the first groove 50 can be achieved by laser etching, chemical etching, or any other required techniques.

[0078] Step S60, Reference Figure 10 A conductive film layer 70 is formed on the back side obtained in step S50.

[0079] The conductive film layer 70 covers the sidewalls and bottom wall of the first groove 50, the overlapping area 40, and the sidewalls 601 and bottom wall of the second groove 60.

[0080] The conductive film layer 70 can be formed by referring to the corresponding methods in the prior art. For example, the conductive film layer 70 can be formed by magnetron sputtering, vapor deposition, ion beam evaporation, activated plasma vapor deposition, and any other desired techniques.

[0081] Step S70, Reference Figure 11 and Figure 12 In step S60, an opening is etched in the third preset area on the back side, and two first isolation areas 710 are formed on the conductive film layer 70 at the bottom of the second groove 60. Each first isolation area 710 includes at least one first isolation groove 711 spaced apart along the X-axis direction.

[0082] The first isolation groove 711 can be formed, for example, by laser, ink etching, mask etching, and any other desired technique.

[0083] refer to Figure 8 and Figure 13 In some implementations, step S40 includes:

[0084] Step S410: A passivation layer 310 is formed on the back side obtained in step S30.

[0085] Step S420: An amorphous silicon layer 320 is formed on the passivation layer 310.

[0086] The passivation layer 310 can reduce carrier recombination and optimize carrier transport paths. The material of the passivation layer 310 is, for example, a-Si:H(i) or silicon oxide.

[0087] refer to Figure 9 and Figure 14 In some implementations, step S50 includes:

[0088] Step S510: Remove the passivation layer 310 and amorphous silicon layer 320 at the first groove 50.

[0089] Step S520: Perform laser scanning on a predetermined area of ​​the amorphous silicon layer 320 at the second groove 60 to form a crystallized microcrystalline silicon region 301.

[0090] The passivation layer 310 and amorphous silicon layer 320 in the second preset area are removed by etching to form the first groove 50. At the same time, a portion of the amorphous silicon layer 320 in the second groove 60 is laser-scanned to form a crystallized microcrystalline silicon region 301.

[0091] refer to Figures 1 to 3 , Figure 15 The method for preparing the back contact battery 100 of this application further includes the following steps:

[0092] In step S80, an opening is etched in the fourth preset area on the back side obtained in step S60 to form a second isolation area 720 on the conductive film layer 70 on the top 401 of the overlapping area 40.

[0093] A second isolation region 720 is formed by etching a groove on the conductive film layer 70 at the top 401 of the overlapping region 40.

[0094] refer to Figures 1 to 3 , Figure 15 The method for preparing the back contact battery 100 of this application further includes the following steps:

[0095] Step S90 further includes: etching an opening in the fifth preset area on the back side obtained in step S60 to form a third isolation area 730 at the position of the conductive film layer 70 corresponding to the sidewall 601 of the second groove 60.

[0096] A third isolation region 730 is formed by etching a groove on the conductive film layer 70 at the sidewall 601 of the second groove 60.

[0097] In some implementations, reference Figure 1 The method for preparing the back contact battery 100 further includes: forming a first electrode 910 and a second electrode 920 respectively located in the first groove 50 and the second groove 60 on the back side obtained in step S70, step S80 or step S90. The first electrode 910 and the second electrode 920 can be formed by printing, transfer printing, electroplating or other methods.

[0098] The back contact battery 100 in the embodiments of this application will be described below with reference to some of the above embodiments and related comparative examples.

[0099] Example 1

[0100] refer to Figure 5 As shown, a semiconductor substrate 10, specifically an N-type silicon wafer, is provided, and the N-type silicon wafer is cleaned and polished. A first semiconductor layer 20 is formed on the back side 102 of the N-type silicon wafer. The first semiconductor layer 20 includes a tunneling oxide layer 210 and an intrinsic polysilicon layer 220 sequentially located away from the back side 102 of the N-type silicon wafer. The intrinsic polysilicon layer 220 is subjected to phosphorus diffusion doping to form a phosphorus-doped polysilicon layer. A mask layer 80, specifically a silicon oxide layer, is then provided.

[0101] like Figure 6 As shown, in Figure 5 The resulting backside patterning process removes the first semiconductor layer 20 and the mask layer 80 of the recessed region 110, forming the recessed region 110.

[0102] like Figure 7 As shown, texturing is performed on the N-type silicon wafer in the recessed region 110 to form a textured surface 111.

[0103] like Figure 8 As shown, in Figure 7A second semiconductor layer 30 is formed on the resulting back side. The second semiconductor layer 30 includes a passivation layer 310 and an amorphous silicon layer 320 sequentially disposed away from the semiconductor substrate 10. The passivation layer 310 is specifically an a-Si:H(i) layer, and the amorphous silicon layer 320 is specifically a p-type doped amorphous silicon thin film layer. The a-Si:H(i) passivation layer 310 can be deposited at a low temperature (annealing conditions). The p-type doped amorphous silicon thin film layer can be formed by using AlOx or evaporated Al as the dopant source under low-temperature annealing conditions. The low temperature range is less than 250°C, specifically, for example, 200°C.

[0104] like Figure 9 , Figure 12 As shown, in Figure 8 The second semiconductor layer 30 is removed from the position corresponding to the first groove 50 on the back side; simultaneously, a laser with a wavelength of 355nm is used for scanning to crystallize part of the P-type doped amorphous silicon thin film layer, forming a crystallized microcrystalline silicon region 301. Alternatively, a laser with a wavelength of 532nm can be used for scanning.

[0105] like Figure 10 As shown, in Figure 9 The resulting back side has a conductive film layer 70, specifically a tin-doped indium oxide thin film.

[0106] like Figure 11 and Figure 12 As shown, ink etching or laser patterning is applied to the conductive film layer 70 to form a first isolation region 710. The first isolation region 710 includes at least one first isolation trench 711.

[0107] In this embodiment, the width D1 of the overlapping region 40 is 10 μm, the width W1 of the slope is 5 μm, the width Wa of the first isolation region 710 is 35 μm, and the width W2 of the crystallized microcrystalline silicon region 301 is 300 μm. Furthermore, Embodiments 2-6 are performed with reference to Embodiment 1, differing only in the relevant dimensional parameters, as detailed in Table 1.

[0108] The back contact batteries obtained in Examples 1-6 were tested using an IV tester, and their performance was compared with that of related technologies. The results are shown in Table 1.

[0109] Table 1

[0110]

[0111] According to Table 1, in Examples 1 and 3, the number of the first isolation groove 711 and the second isolation groove 721 is one each; in Examples 2 and 4, the number of the first isolation groove 711 and the second isolation groove 721 is two each; and in Examples 5 and 6, the number of the first isolation groove 711 and the second isolation groove 721 is three each. In Table 1, Comparative Examples 1, 2, and 3 are Examples 1, 2, and 7 in the related art, respectively.

[0112] The results above show that, compared with the comparative example, the back contact battery 100 of the present invention has a higher conversion efficiency.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A back-contact battery, characterized in that, include: Semiconductor substrate, including front and back sides; A first semiconductor layer and a second semiconductor layer are alternately arranged on the back surface along the X-axis direction. The edges of the first semiconductor layer and the edges of the second semiconductor layer overlap in the Z-axis direction. A first groove is formed between adjacent second semiconductor layers. The outer surface of the second semiconductor layer has a second groove. The conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer. A conductive film layer is disposed on the outer surface of the first groove, the second groove and the overlapping area. The outer surface of the second groove includes the bottom and sidewall of the second groove. The bottom and sidewall of the second groove are covered with the conductive film layer. Corresponding to the bottom of the second groove, two first isolation areas are spaced apart on the conductive film layer. Each first isolation area includes at least one first isolation groove spaced apart along the X-axis direction. In the same second groove, the second semiconductor layer between the two first isolation regions includes a crystallized microcrystalline silicon region, and the distance between the crystallized microcrystalline silicon region and any of the first isolation regions along the X-axis direction is less than 5 μm.

2. The back contact battery according to claim 1, characterized in that, Along the X-axis, the distance between two adjacent first isolation slots in the same first isolation zone is 5-15 μm.

3. The back contact battery according to claim 1, characterized in that, The conductive film layer on the opposite side walls of the second groove is a slope biased towards the top of the overlapping area. Along the X-axis, the width of the overlapping area is 10-160μm, the width of the slope is 5-20μm, the width of the first isolation groove is 35-80μm, and the width of the crystallized microcrystalline silicon area is 300-600μm.

4. The back contact battery according to claim 1, characterized in that, The conductive film layer on the opposite side walls of the second groove is a slope biased towards the top of the overlapping area. In the X-axis direction, in the same second groove, the two first isolation areas are close to one of the slopes, the starting points of the two first isolation areas are relatively far apart, and the ending points of the two first isolation areas are relatively close. The distance between the starting point of any first isolation area and the bottom of the adjacent slope is 0-3μm.

5. The back contact battery according to claim 1, characterized in that, The conductive film layer has a second isolation region at the top position of the overlapping region, and the second isolation region includes at least one second isolation groove spaced apart along the X-axis direction.

6. The back contact battery according to claim 5, characterized in that, Along the X-axis, the width of the second isolation groove is 0-80 μm.

7. The back contact battery according to claim 5, characterized in that, Within the same second isolation zone, the distance between two adjacent second isolation slots is 10-30 μm.

8. The back contact battery according to claim 1, characterized in that, The conductive film layer has a third isolation zone at the position corresponding to the side wall of the second groove.

9. A method for preparing a back contact battery, characterized in that, The method for preparing the back contact battery includes: Step S10: Sequentially form a first semiconductor layer and a mask layer on the back side of the semiconductor substrate; Step S20: Remove the first semiconductor layer and its corresponding mask layer in the first preset area on the back side obtained in step S10 to form a recessed area; Step S30: Form a velvety surface at the bottom of the recessed area; Step S40: A second semiconductor layer is formed on the back side obtained in step S30, and a second groove is formed on the outer surface of the second semiconductor layer corresponding to the recessed area, wherein step S40 includes: A passivation layer is formed on the back side obtained in step S30; An amorphous silicon layer is formed on the passivation layer; Step S50: Remove the second semiconductor layer and the corresponding mask layer in the second preset area on the back side obtained in step S40 to form a first groove spaced apart from the second groove, and the edges of the first semiconductor layer and the edges of the second semiconductor layer form an overlapping area, wherein step S50 includes: Remove the passivation layer and amorphous silicon layer at the first groove; A predetermined area of ​​the amorphous silicon layer at the second groove is laser-scanned to form a crystalline microcrystalline silicon region; Step S60: A conductive film layer is formed on the back side obtained in step S50. The conductive film layer is disposed on the outer surface of the first groove, the second groove and the overlapping area. The outer surface of the second groove includes the bottom and sidewall of the second groove. The bottom and sidewall of the second groove are both covered with the conductive film layer. Step S70: Etch an opening in the third preset area on the back side obtained in step S60, and form two spaced first isolation areas on the conductive film layer at the bottom of the second groove. Each first isolation area includes at least one spaced first isolation groove along the X-axis direction, wherein the distance between the crystallized microcrystalline silicon area and any of the first isolation areas along the X-axis direction is less than 5 μm.

10. The method for preparing a back contact battery according to claim 9, characterized in that, Also includes: An etched opening is made in the fourth preset region on the back side obtained in step S60 to form a second isolation region on the conductive film layer at the top of the overlapping region.

11. The method for preparing a back contact battery according to claim 9, characterized in that, Also includes: An etched opening is made in the fifth preset area on the back side obtained in step S60 to form a third isolation area at the position of the sidewall of the conductive film layer corresponding to the second groove.

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