Sampling method, sampling device, computer storage medium and laser ranging device

Abstract

The invention discloses a sampling method, a sampling device, a computer storage medium and a laser ranging device.The sampling method comprises the steps that an electric signal output by a detection unit is sampled with N * f0 as the sampling rate, and an initial sampling signal is generated; wherein f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1; sampling K * N sampling data of adjacent K clock periods of the initial sampling signal by taking f0 / K as a sampling rate, and generating a first sampling signal to a (K * N)-th sampling signal; wherein K is a positive integer greater than 1; according to the invention, the sampling rate of the sampling circuit can be improved, so that the time-of-flight distance measurement precision is improved, and meanwhile, the clock speed requirement during the processing operation of the subsequent sampling signal is reduced.

Description

Sampling method, sampling device, computer storage medium and laser ranging device Technical Field

[0001] The present application relates to the field of laser ranging, and in particular to a sampling method, a sampling device, a computer storage medium and a laser ranging device. Background Art

[0002] Laser ranging technology has important applications in areas such as autonomous driving, facial recognition, and 3D gesture recognition. Laser ranging systems typically use time-of-flight measurement technology to measure flight time, and then use flight time to determine the distance to obstacles. Time-of-flight measurement technology typically uses a laser to emit a pulsed light signal to the detection area, and uses a detector to detect the return light signal after the pulsed light signal emitted by the laser is reflected by obstacles in the detection area. When the detector receives the light signal, the electrical signal output by the detector is a pulsed high level; when the detector does not receive the light signal, the electrical signal output by the detector is a low level, that is, the electrical signal output by the detector is a digital signal. The electrical signal output by the detector is then sampled by a sampling circuit to generate a sampling signal. The sampling signal is used to determine the flight time, and the distance between the laser and the object can be calculated based on the flight time.

[0003] At present, the measurement accuracy of flight time usually depends on the sampling rate of the sampling circuit; the higher the sampling rate of the sampling circuit, the shorter the time interval between two adjacent sampling moments in the sampled signal, that is, the shorter the duration of each flight moment in the flight time statistical period, and the higher the measurement accuracy of the flight time.

[0004] To improve time-of-flight measurement accuracy, related technologies typically increase the sampling rate of the sampling circuit. However, increasing the sampling rate of the sampling circuit increases the clock speed requirements for subsequent processing of the sampled signals, which can easily consume a large amount of computing resources. Therefore, how to increase the sampling rate of the sampling circuit, thereby improving the accuracy of time-of-flight ranging, while reducing the clock speed requirements for subsequent processing of the sampled signals has become a technical problem that needs to be solved by those skilled in the art.

[0005] Summary of the Invention

[0006] To solve the above problems, the present application provides a sampling method, a sampling device, a computer storage medium and a laser ranging device, which samples the electrical signal output by the detection unit at a sampling rate of N*f0, thereby improving the sampling rate and thereby improving the measurement accuracy of the time of flight; at the same time, the initial sampling signal is sampled at a sampling rate of f0 / K to generate a first sampling signal to a K*Nth sampling signal, thereby realizing the conversion of the initial sampling signal in a fast clock domain to a first sampling signal to a K*Nth sampling signal in a slow clock domain, thereby reducing the clock speed requirements for subsequent sampling signal processing operations and reducing the computing resources required for subsequent sampling signal processing operations, thereby improving the sampling rate of the sampling circuit, thereby improving the ranging accuracy of the time of flight while reducing the clock speed requirements for subsequent sampling signal processing operations.

[0007] In a first aspect, the present application provides a sampling method, comprising:

[0008] Sampling the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal; wherein f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1;

[0009] K*N sampling data of K adjacent clock cycles of the initial sampling signal are sampled at a sampling rate of f0 / K to generate a first sampling signal to a K*Nth sampling signal; wherein K is a positive integer greater than 1.

[0010] In a second aspect, the present application further provides a sampling device, comprising:

[0011] A first sampling unit is configured to sample the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal; wherein f0 is a clock frequency of the first clock signal, and N is a positive integer greater than 1;

[0012] The second sampling unit is used to sample K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal; wherein K is a positive integer greater than 1.

[0013] In a third aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores at least one executable instruction, and when the executable instruction is executed by a processor, any of the above-mentioned methods is implemented.

[0014] In a fourth aspect, the present application further provides a laser ranging device, characterized in that it includes: a transmitter, a detector, a processor, a communication interface, a memory, and a communication bus; the processor communicates with the transmitter and the detector via the communication interface; the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0015] The transmitter includes one or more light-emitting units for transmitting pulsed light signals;

[0016] The detector includes one or more detection units for receiving optical signals;

[0017] The memory is used to store computer programs or instructions;

[0018] The processor is configured to execute the computer program or instructions in the memory to implement any of the above methods.

[0019] The present application also provides another laser ranging device, comprising a transmitter, a detector and a sampling module;

[0020] The transmitter includes one or more light-emitting units for transmitting pulsed light signals;

[0021] The detector includes one or more detection units for receiving optical signals;

[0022] The sampling module includes one or more sampling units, and the sampling unit adopts any of the sampling devices described above.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The electrical signal output by the detection unit is sampled at a sampling rate of N*f0, thereby improving the sampling rate and thus improving the measurement accuracy of the flight time; at the same time, the initial sampling signal is sampled at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal, thereby realizing the conversion of the initial sampling signal in the fast clock domain into the first sampling signal to the K*Nth sampling signal in the slow clock domain, thereby reducing the clock speed requirement for subsequent sampling signal processing operations and reducing the computing resources required for subsequent sampling signal processing operations, so as to achieve the improvement of the sampling rate of the sampling circuit, thereby improving the distance measurement accuracy of the flight time and reducing the clock speed requirement for subsequent sampling signal processing operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a flow chart of a sampling method provided in an embodiment of the present application;

[0026] FIG2 is a flow chart of step S110 in the sampling method provided in FIG1 ;

[0027] FIG3 is a flow chart of step S110 in the sampling method provided in FIG2 ;

[0028] FIG4 is a timing diagram of waveform changes of various signals in the sampling method provided in an embodiment of the present application;

[0029] FIG5 is another flow chart of the sampling method provided in an embodiment of the present application;

[0030] FIG6 is a schematic structural diagram of a sampling device provided in an embodiment of the present application;

[0031] FIG7 is a schematic diagram of a specific structure of the sampling device provided in FIG6;

[0032] FIG8 is a schematic diagram of a specific structure of the sampling device provided in FIG7 ;

[0033] FIG9 is another schematic structural diagram of a sampling device provided in an embodiment of the present application;

[0034] FIG10 is a schematic diagram of a specific structure of the determination unit and the output unit in the sampling device provided in FIG9;

[0035] FIG11 is a schematic diagram of a specific structure of the determination unit and the output unit in the sampling provided in FIG10;

[0036] FIG12 is a schematic structural diagram of a laser ranging device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the multiple drawings provided in the embodiments of the present application.

[0038] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0039] It should be noted that when a unit is referred to as being "connected to" another unit, it may be directly connected to the other unit or indirectly connected to the other unit. It should be understood that the term "and / or" used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. In addition, in the description of this specification and the appended claims, the terms "first", "second", "third", "fourth", etc. are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance. Unless otherwise specified, " / " means "division" and "*" means "multiplication".

[0040] It should also be understood that references to "one embodiment" or "some embodiments" in the present specification mean that one or more embodiments of the present application include a particular feature, structure, or characteristic described in conjunction with the embodiment. Thus, phrases such as "in one embodiment," "in some embodiment embodiments," "in other embodiments," and "in other embodiments" appearing in different places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0041] As shown in Figure 1, on the first aspect, an embodiment of the present application provides a sampling method for sampling the electrical signal output by the detection unit at a sampling rate of N*f0, thereby improving the sampling rate and thereby improving the measurement accuracy of the flight time; at the same time, the sampling method provided by the embodiment of the present application samples the initial sampling signal at a sampling rate of f0 / K, generates the first sampling signal to the K*Nth sampling signal, and realizes the conversion of the initial sampling signal in the fast clock domain into the first sampling signal to the K*Nth sampling signal in the slow clock domain, so as to reduce the clock speed requirements for subsequent sampling signals (i.e., flight time data) when performing processing operations, and reduce the computing resources required for subsequent sampling signals when performing processing operations.

[0042] Referring to FIG1 , a sampling method provided in an embodiment of the present application includes but is not limited to the following steps:

[0043] S110 , sampling the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal; wherein f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1.

[0044] In some specific embodiments, the detection unit uses a silicon photomultiplier (SIPM). A silicon photomultiplier is a new type of photodetector device that consists of an avalanche diode array operating in Geiger mode. It has the characteristics of high gain, high sensitivity, low bias voltage, insensitivity to magnetic fields, and compact structure. In other optional embodiments, the detection unit 101 can also use a single photon avalanche diode (SPAD). This application does not limit the specific type of the detection unit 101.

[0045] As shown in Figure 4, the electrical signal output by the detection unit is an electrical signal, and the electrical signal output by the detection unit is a digital signal; when the electrical signal output by the detection unit 101 is at a high level, it means that the detection unit 101 has received an optical signal (including an echo optical signal); when the electrical signal output by the detection unit 101 is at a low level, it means that the detection unit 101 has not received an optical signal.

[0046] The sampling method provided in the embodiment of the present application samples the electrical signal output by the detection unit at a sampling rate of N*f0, that is, N samplings are performed in each clock cycle of the first clock signal, and the initial sampling signal includes N sampling data (that is, N flight time data) in each clock cycle of the first clock signal; wherein, the N sampling data include N sampling moments (that is, N flight moments) in each clock cycle of the first clock signal and the sampling values ​​corresponding to each of the N sampling moments (the number of photons corresponding to each of the N flight time moments). Compared with the related art, the sampling rate of the electrical signal output by the detection unit is increased by sampling at a sampling rate of f0. When the related art samples the electrical signal output by the detection unit at a sampling rate of f0, the phase difference between two adjacent sampling data is The time interval between two adjacent sampling data is Δt0=T0, and the measurement accuracy of the flight time is equal to Δt0=T0; wherein T0 is the clock period of the first clock signal, T0=1 / f0, and the sampling method provided in the embodiment of the present application samples the electrical signal output by the detection unit at a sampling rate of N*f0, and the phase difference between two adjacent sampling data in the initial sampling signal is The time interval between two adjacent sampling data is Δt1=T0 / N; the measurement accuracy of the flight time is equal to Δt1=T0 / N, which improves the measurement accuracy of the flight time.

[0047] S120 , sampling K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate a first sampling signal to a K*Nth sampling signal; wherein K is a positive integer greater than 1.

[0048] Among them, the (k-1)*N+1th sampling signal to the k*Nth sampling signal are the N sampling data corresponding to the initial sampling signal in the kth clock cycle, k is a positive integer, and 1≤k≤K; when k=1, the (k-1)*N+1th sampling signal to the k*Nth sampling signal are the first sampling signal to the Nth sampling signal, and the first sampling signal to the Nth sampling signal are the N sampling data corresponding to the initial sampling signal in the 1st clock cycle...When k=K, the (k-1)*N+1th sampling signal to the k*Nth sampling signal are the (K-1)*N+1th sampling signal to the K*Nth sampling signal, and the (K-1)*N+1th sampling signal to the K*Nth sampling signal are the N sampling data corresponding to the initial sampling signal in the Kth clock cycle.

[0049] The sampling method provided in the present application samples the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal, wherein the initial clock signal is a signal in the clock domain with a frequency of f0, and the first sampling signal to the K*Nth sampling signal are signals in the clock domain with a frequency of f0 / K, thereby realizing the conversion of the initial sampling signal in the fast clock domain into the first sampling signal to the K*Nth sampling signal in the slow clock domain, thereby reducing the clock speed requirements for subsequent sampling signals (i.e., time-of-flight data) when performing processing operations, and reducing the computing resources required for subsequent sampling signals when performing processing operations.

[0050] In some specific embodiments, N=2, that is, sampling is performed twice in each clock cycle of the first clock signal, and the initial sampling signal includes two sampled data in each clock cycle of the first clock signal. As shown in FIG2 , step S110 samples the electrical signal output by the detection unit at a sampling rate of N*f0, and generating the initial sampling signal includes:

[0051] S111, sampling the electrical signal output by the detection unit using the rising edge of the first clock signal to generate a first initial sampling signal;

[0052] S112, use the falling edge of the first clock signal to sample the electrical signal output by the detection unit to generate a second initial sampling signal; wherein, the first initial sampling signal and the second initial sampling clock signal constitute the initial clock signal; the first initial sampling signal is the first sampling data of the initial clock signal in each clock cycle of the first clock signal, and the second initial sampling signal is the second sampling data of the initial clock signal in each clock cycle of the first clock signal.

[0053] As shown in FIG4 , the first clock signal is CLK1 ; it can be understood that by sampling the electrical signal output by the detection unit at the rising and falling edges of the first clock signal CLK1 , the sampling rate is doubled, and the measurement accuracy of the time of flight is doubled.

[0054] As shown in FIG4 , the first initial sampling signal is sample1; the second initial sampling signal is sample2. When the electrical signal output by the detection unit 101 is sampled using the rising edge of the first clock signal CLK1, if a pulse high level is sampled at a certain rising edge of the first clock signal CLK1, the first initial sampling signal sample1 is high at the sampling instant corresponding to the rising edge. Accordingly, the flight instant corresponding to the sampling instant is the time when the pulse high level of the detection unit is generated, that is, the time when the optical signal arrives at the detection unit. The level value of the first initial sampling signal sample1 at the sampling instant corresponding to the rising edge is used to indicate the number of photons received by the detection unit 101 at the corresponding flight instant. If a pulse high level is not sampled at a certain rising edge of the first clock signal CLK1, the first initial sampling signal sample1 is low at the sampling instant corresponding to the rising edge. Accordingly, the detection unit does not generate a pulse high level at the flight instant corresponding to the sampling instant, that is, the detection unit does not receive an optical signal at the flight instant.

[0055] Similarly, when the electrical signal output by the detection unit is sampled using the falling edge of the first clock signal CLK1, if a pulse high level is sampled at a certain falling edge of the first clock signal CLK1, the first initial sampling signal sample1 is at a high level at the sampling moment corresponding to the falling edge. Accordingly, the flight time corresponding to the sampling moment is the time when the pulse high level of the detection unit is generated, that is, the time when the optical signal arrives at the detection unit; the level value of the first initial sampling signal sample1 at the sampling moment corresponding to the falling edge is used to indicate the number of photons received by the detection unit at the corresponding flight time; if a pulse high level is not sampled at a certain falling edge of the first clock signal CLK1, the first initial sampling signal sample1 is at a low level at the sampling moment corresponding to the falling edge. Accordingly, the detection unit does not generate a pulse high level at the flight time corresponding to the sampling moment, that is, the detection unit does not receive the optical signal at the flight time.

[0056] In a specific embodiment, the frequency of the first clock signal CLK1 is 1 GHz, and the clock period of the first clock signal CLK1 is 10 -9s; When the sampling method provided in the embodiment of the present application simultaneously uses the rising edge and falling edge of the first clock signal CLK1 to sample the electrical signal output by the detection unit, the sampling rate is 2 GHz; at the same time, the time interval between the first initial sampling signal sample1 and the second initial sampling signal sample2 is equal to (1 / 2 GHz) = 5*10 -10 s, that is, the time interval between two adjacent sampling data in the initial sampling signal is equal to (1 / 2Ghz) = 5*10 -10 s, and accordingly, the measurement accuracy of the flight time is 5*10 -10 s.

[0057] Further, K=2; N=2, sampling K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K is sampling 2*2, that is, 4 sampling data of two adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / 2; the first sampling signal to the K*Nth sampling signal include a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; the first sampling signal is the first sampling data of the initial sampling signal in the first clock cycle of two adjacent clock cycles of the first clock signal CLK1, the second sampling signal is the second sampling data of the initial sampling signal in the first clock cycle of two adjacent clock cycles of the first clock signal CLK1, the third sampling signal is the first sampling data of the initial sampling signal in the second clock cycle of two adjacent clock cycles of the first clock signal CLK1, and the fourth sampling signal is the second sampling data of the initial sampling signal in the second clock cycle of two adjacent clock cycles of the second clock signal CLK1.

[0058] As shown in FIG3 , in some specific implementations, step S120 of sampling K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal includes:

[0059] S121, synchronizing the first initial sampling signal with the first clock signal to generate a first synchronization signal; synchronizing the second initial sampling signal with the first clock signal to generate a second synchronization signal;

[0060] As shown in FIG4 , the first synchronization signal is sync1, and the second synchronization signal is sync2. Since the first initial sampling signal sample1 is obtained by sampling at the rising edge of the first clock signal CLK1, and the second initial sampling signal sample2 is obtained by sampling at the falling edge of the first clock signal CLK1, the first initial sampling signal sample1 and the second initial sampling signal sample2 are asynchronous signals. Step S12 is used to synchronize the first synchronization signal sync1 and the second synchronization signal sync2 with the first clock signal CLK1.

[0061] Furthermore, synchronizing the first initial sampling signal with the first clock signal to generate the first synchronization signal includes: synchronizing the first initial sampling signal with a rising edge of the first clock signal to generate the first synchronization signal.

[0062] Specifically, the first synchronization signal sync1 is synchronized with a rising edge of the first clock signal CLK1 .

[0063] Furthermore, synchronizing the second initial sampling signal with the first clock signal to generate the second synchronization signal includes: synchronizing the second initial sampling signal with a rising edge of the first clock signal to generate the second synchronization signal.

[0064] Specifically, the second synchronization signal sync2 is synchronized with the rising edge of the first clock signal CLK1 .

[0065] S122, delaying the first synchronization signal by T0 to generate a third synchronization signal; delaying the second synchronization signal by T0 to generate a fourth synchronization signal;

[0066] As shown in Figure 4, the third synchronization signal is sync3; the second synchronization signal is sync4; since the third synchronization signal sync3 is delayed by one clock cycle T0 of the first clock signal CLK1 compared to the first synchronization signal sync1, the third synchronization signal is sync3 and is used to represent the data of the next clock cycle of the first synchronization signal sync1; since the fourth synchronization signal sync4 is delayed by one clock cycle T0 of the first clock signal CLK1 compared to the second synchronization signal sync2, the fourth synchronization signal is sync4 and is used to represent the data of the next clock cycle of the second synchronization signal sync2.

[0067] As shown in FIG4 , when the electrical signal output by the detection unit is sampled by the rising edge and the falling edge of the first clock signal CLK1, the sampling rate is 2*f1, that is, the electrical signal output by the detection unit is sampled four times in every two adjacent clock cycles T0 of the first clock signal CLK1, and is sampled twice in each clock cycle T0; wherein, the sampling data of the electrical signal output by the detection unit being sampled twice in the first clock cycle of the two adjacent clock cycles of the first clock signal CLK1 are the first synchronization signal sync1 and the second synchronization signal sync1 respectively; the sampling data of the electrical signal output by the detection unit being sampled twice in the second clock cycle of the two adjacent clock cycles of the first clock signal CLK1 are the first synchronization signal sync1 and the second synchronization signal sync1 respectively; The sampled data sampled twice are the third synchronization signal sync3 and the fourth synchronization signal sync4. The sampling time corresponding to the first synchronization signal sync1 is the sampling time corresponding to the rising edge of the clock cycle before two adjacent clock cycles, and the sampling time corresponding to the second synchronization signal sync2 is the sampling time corresponding to the falling edge of the clock cycle before two adjacent clock cycles. The sampling time corresponding to the third synchronization signal sync3 is the sampling time corresponding to the rising edge of the clock cycle after two adjacent clock cycles, and the sampling time corresponding to the fourth synchronization signal sync4 is the sampling time corresponding to the falling edge of the clock cycle after two adjacent clock cycles. In other words, the first synchronization signal sync1, the second synchronization signal sync2, the third synchronization signal sync3, and the fourth synchronization signal sync4 are equivalent to the sampled data corresponding to each of the four time units when the clock cycle of the second clock signal CLK2 with a frequency of f0 / 2 is equally divided into four time units.

[0068] S123, use the rising edge of the second clock signal to sample the first synchronization signal and delay it by T2 to generate a first sampling signal; use the rising edge of the second clock signal to sample the second synchronization signal and delay it by T2 to generate a second sampling signal; use the rising edge of the second clock signal to sample the third synchronization signal to generate a third sampling signal; use the rising edge of the second clock signal to sample the fourth synchronization signal to generate a fourth sampling signal; wherein, the clock frequency of the second clock signal is f0 / 2, T2 is the period of the second clock signal, and T2=2 / f0.

[0069] In a specific embodiment, the clock frequency f0 of the first clock signal CLK1 is 1 GHz, the frequency of the second clock signal CLK2 is 500 MHz; the clock period of the first clock signal CLK1 is 10 -9s; When the sampling method provided in the embodiment of the present application simultaneously uses the rising edge and falling edge of the first clock signal CLK1 to sample the electrical signal output by the detection unit, the sampling rate is 2 GHz; at the same time, the time interval between the first initial sampling signal sample1 and the second initial sampling signal sample2 is equal to (1 / 2 GHz) = 5*10 -10 s, that is, the time interval between two adjacent sampling data in the initial sampling signal is equal to (1 / 2Ghz) = 5*10 -10 s, and accordingly, the measurement accuracy of the flight time is 5*10 -10 The sampling rates of the first sampling signal res1, the second sampling signal res2, the third sampling signal res3, and the fourth sampling signal res4 are all 500 MHz. Compared with the initial sampling signal with a sampling rate of 3 GHz, the clock speed requirement for subsequent processing operations on the first sampling signal res1, the second sampling signal res2, the third sampling signal res3, and the fourth sampling signal res4 is reduced, thereby reducing the computing resources required for subsequent processing operations on the sampling signals.

[0070] The sampling method provided in the embodiment of the present application converts the initial clock signal in the clock domain of the first clock signal CLK1 with a frequency f0 into the first sampling clock signal, the second sampling clock signal, the third sampling clock signal, and the fourth sampling clock signal in the clock domain of the second clock signal CLK2 with a frequency f0 / 2 through steps S121 to S123, thereby converting the initial sampling signal in the fast clock domain into the first sampling signal to the fourth sampling signal in the slow clock domain. This can reduce the clock speed requirements for subsequent sampling signal (i.e., time-of-flight data) when performing processing operations, thereby reducing the computing resources required for subsequent sampling signal processing operations.

[0071] As shown in Figure 4, the signal after the first synchronization signal sync1 is sampled by the second clock signal CLK2 is res01, and the first sampling signal res1 is obtained after res01 is delayed by T2; the signal after the second synchronization signal sync2 is sampled by the second clock signal CLK2 is res02, and the second sampling signal res1 is obtained after res02 is delayed by T2; the third sampling signal is res3; and the fourth sampling signal is res4. The four sampling data corresponding to each rising edge of the second clock signal CLK2, namely, the four sampling data of the first sampling signal res1, the second sampling signal res2, the third sampling signal res3 and the fourth sampling signal res4, are the four sampling data of the initial sampling signal composed of the first initial sampling signal sample1 and the second initial sampling signal sample2 in two adjacent clock cycles of the first clock signal CLK1. That is, the four sampling data corresponding to each rising edge of the second clock signal CLK2, namely, the four sampling data of the first sampling signal res1, the second sampling signal res2, the third sampling signal res3 and the fourth sampling signal res4, are the four sampling data of the initial sampling signal composed of the first initial sampling signal sample1 and the second initial sampling signal sample2 in each clock cycle of the second clock signal CLK2, that is, the first sampling signal res1 is the first flight time data P0 in each clock cycle of the second clock signal CLK2, the second sampling signal res2 is the second flight time data P1 in each clock cycle of the second clock signal CLK2, the third sampling signal res3 is the third flight time data P2 in each clock cycle of the second clock signal CLK2, and the fourth sampling signal res4 is the fourth flight time data P3 in each clock cycle of the second clock signal CLK2.

[0072] As shown in FIG5 , in some other embodiments, the sampling method further includes:

[0073] S130, determining whether a transition from 0 to 1 occurs between every two adjacent sampling signals from the first sampling signal to the K*Nth sampling signal, and generating first to K*Nth determination results;

[0074] Among them, the first judgment result is the judgment result generated by judging whether a jump from 0 to 1 occurs between the K*Nth sampling signal and the first sampling signal; the second judgment result is the judgment result generated by judging whether a jump from 0 to 1 occurs between the first sampling signal and the second sampling signal; the xth judgment result is the judgment result generated by judging whether a jump from 0 to 1 occurs between the xth sampling signal and the x+1th sampling signal, where x is a positive integer and 2≤x≤K*N-1;

[0075] S140, outputting the first judgment result to the K*Nth judgment result;

[0076] S150, obtaining the first to K*Nth judgment results, and determining whether the first to K*Nth sampling signals are normal sampling signals based on the first to K*Nth judgment results; if so, proceeding to step S160;

[0077] S160: Output the first sampling signal to the K*Nth sampling signal. That is, when the first sampling signal to the K*Nth sampling signal are normal sampling signals, output the first sampling signal to the K*Nth sampling signal.

[0078] Specifically, when the first sampling signal to the K*Nth sampling signal are normal sampling signals, there is no jump from 0 to 1 between the first sampling signal to the K*Nth sampling signal, or there is only a jump from 0 to 1 between two sampling signals; if it is determined according to the first judgment result to the K*Nth judgment result that there are two or more jumps from 0 to 1 between the first sampling signal to the K*Nth sampling signal, then it means that sampling abnormality occurs in the first sampling signal to the K*Nth sampling signal.

[0079] The sampling method provided in the embodiment of the present application determines whether the first sampling signal to the K*Nth sampling signal are normal sampling signals by judging the number of jumps from 0 to 1 between each two adjacent sampling signals from the first sampling signal to the K*Nth sampling signal, thereby avoiding outputting abnormal first sampling signals to the K*Nth sampling signal, which affects the flight time measurement result.

[0080] In a specific embodiment, K=2, N=2.

[0081] Step S130, determining whether a transition from 0 to 1 occurs between every two adjacent sampling signals from the first sampling signal to the K*Nth sampling signal, and generating the first determination result to the K*Nth determination result includes:

[0082] It is determined whether a transition from 0 to 1 occurs between each two adjacent sampling signals from the first sampling signal to the fourth sampling signal, and first to fourth determination results are generated; wherein the first determination result is a determination result generated by determining whether a transition from 0 to 1 occurs between the fourth sampling signal and the first sampling signal; the second determination result is a determination result generated by determining whether a transition from 0 to 1 occurs between the first sampling signal and the second sampling signal; the third determination result is a determination result generated by determining whether a transition from 0 to 1 occurs between the second sampling signal and the third sampling signal; and the fourth determination result is a determination result generated by determining whether a transition from 0 to 1 occurs between the third sampling signal and the fourth sampling signal.

[0083] Step S140, outputting the first judgment result to the K*Nth judgment result includes:

[0084] Outputting the first to fourth judgment results.

[0085] Step S150, obtaining the first to K*Nth judgment results, and determining whether the first to K*Nth sampling signals are normal sampling signals based on the first to K*Nth judgment results. If so, proceeding to step S160 includes:

[0086] According to the first to fourth judgment results, it is determined whether the first to fourth sampling signals are normal sampling signals. If so, the process proceeds to step S160.

[0087] Step S160, outputting the first sampling signal to the K*Nth sampling signal includes:

[0088] Outputting the first sampling signal to the fourth sampling signal.

[0089] The above details a sampling method according to an embodiment of the present application. A sampling device according to an embodiment of the present application is provided below. Regarding the second aspect, referring to FIG. 6 , the sampling device shown in FIG. 6 can implement the sampling method shown in FIG. 1 . The sampling device includes a first sampling unit 210 and a second sampling unit 220 .

[0090] The first sampling unit 210 is configured to sample the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal; wherein f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1;

[0091] The second sampling unit 220 is used to sample K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal; wherein K is a positive integer greater than 1.

[0092] The sampling device shown in FIG6 and the method embodiment shown in FIG1 are based on the same concept and bring the same technical effects. For the specific process, reference may be made to the description of the method embodiment shown in FIG1 and will not be repeated here.

[0093] In some specific implementations, N=2. As shown in FIG7 , the first sampling unit 210 includes a first sub-sampling unit 211 and a second sub-sampling unit 212 .

[0094] The first sub-sampling unit 211 samples the electrical signal output by the detection unit using the rising edge of the first clock signal to generate a first initial sampling signal;

[0095] The second sub-sampling unit 212 samples the electrical signal output by the detection unit using the falling edge of the first clock signal to generate a second initial sampling signal.

[0096] Further, K=2; as shown in Figure 7, in some specific embodiments, the second sampling unit 220 includes a first synchronization unit 221, a second synchronization unit 222, a first delay unit 223, a second delay unit 224, a first sampling and delay unit 2251, a second sampling and delay unit 2252, a fifth sub-sampling unit 2253, a sixth sub-sampling unit 2254, a third delay unit 226 and a fourth delay unit 227.

[0097] A first synchronization unit 221 is configured to synchronize the first initial sampling signal with the first clock signal to generate a first synchronization signal;

[0098] A second synchronization unit 222 is configured to synchronize the second initial sampling signal with the first clock signal to generate a second synchronization signal;

[0099] The first delay unit 223 is used to delay the first synchronization signal by T0 to generate a third synchronization signal;

[0100] The second delay unit 224 is used to delay the second synchronization signal by T0 to generate a fourth synchronization signal;

[0101] The first sampling and delay unit 2251 is configured to sample the first synchronization signal using the rising edge of the second clock signal and delay it by T2 to generate a first sampling signal;

[0102] The second sampling and delay unit 2252 is used to sample the second synchronization signal using the rising edge of the second clock signal and generate a second sampling signal after a delay of T2;

[0103] A third sub-sampling unit 2253 is configured to sample the third synchronization signal using the rising edge of the second clock signal to generate a third sampling signal;

[0104] The fourth sub-sampling unit 2254 is configured to sample the fourth synchronization signal using the rising edge of the second clock signal to generate a fourth sampling signal.

[0105] The first sampling unit 210 shown in FIG7 is based on the same concept as the method embodiment of FIG2 and produces the same technical effects. For details, please refer to the description of the method embodiment of FIG2 and will not be repeated here. The second sampling unit 220 shown in FIG7 is based on the same concept as the method embodiment of FIG3 and produces the same technical effects. For details, please refer to the description of the method embodiment of FIG3 and will not be repeated here.

[0106] Please refer to FIG. 8 , which is a schematic structural diagram of a first sampling unit 210 and a second sampling unit 220 provided in an embodiment of the present application. As shown in FIG8 , the first sub-sampling unit 211 includes a first flip-flop D1, which is a rising-edge-triggered D flip-flop. The first flip-flop D1 includes a data input terminal (also referred to as the D terminal), a data output terminal (also referred to as the Q terminal), and a clock input terminal (also referred to as the C terminal). The data input terminal of the first flip-flop D1 is used to receive the electrical signal electrical signal output by the detection unit, the clock input terminal of the first flip-flop D1 is used to receive the first clock signal CLK1, and the data output terminal of the first flip-flop D1 is used to output the first initial sampling signal sample1. The second sub-sampling unit 212 includes a second flip-flop D2, which is a falling-edge-triggered D flip-flop. The second flip-flop D2 includes a data input terminal (the D terminal), a data output terminal (the Q terminal), and a clock input terminal (the C terminal). The data input terminal of the second flip-flop D2 is used to receive the electrical signal electrical signal output by the detection unit, the clock input terminal of the second flip-flop D2 is used to receive the first clock signal CLK1, and the data output terminal of the second flip-flop D2 is used to output the second initial sampling signal sample2. The first trigger D1 samples the electrical signal output by the detection unit at the rising edge of the first clock signal CLK1 to generate a first initial sampling signal sample1; the second trigger D2 samples the electrical signal output by the detection unit at the falling edge of the first clock signal CLK1 to generate a second initial sampling signal sample2.

[0107] As shown in FIG8 , the first synchronization unit 221 includes a third trigger D3, which is a rising edge triggered D trigger; the first trigger D1 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal), the data input terminal of the third trigger D3 is used to receive the first preliminary sampling signal sample1, the clock input terminal of the third trigger D3 is used to receive the first clock signal CLK1, and the data output terminal of the third trigger D3 is used to output the first synchronization signal sync1; the second synchronization unit 222 includes a fourth trigger D4, which is a rising edge triggered D trigger; the fourth trigger D4 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal). An input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal), the data input terminal of the fourth trigger D4 is used to receive the second preliminary sampling signal sample2, the clock input terminal of the fourth trigger D4 is used to receive the first clock signal CLK1, and the data output terminal of the fourth trigger D4 is used to output the second synchronization signal sync2; the third trigger D3 is used to synchronize the first initial sampling signal sample1 with the first clock signal CLK1 to generate the first synchronization signal sync1; the fourth trigger D4 is used to synchronize the second initial sampling signal sample2 with the first clock signal CLK1 to generate the second synchronization signal sync2.

[0108] As shown in FIG8 , the first delay unit 223 includes a fifth trigger D5, which is a rising-edge triggered D trigger; the fifth trigger D5 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal); the data input terminal of the fifth trigger D5 is used to receive the first synchronization signal sync1, the clock input terminal of the fifth trigger D5 is used to receive the first clock signal CLK1, and the data output terminal of the fifth trigger D5 is used to output the third synchronization signal sync3; the second delay unit 224 includes a sixth trigger D6, which is a rising-edge triggered D trigger; the sixth trigger D6 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal); the data input terminal of the fifth trigger D5 is used to receive the first synchronization signal sync1, the clock input terminal of the fifth trigger D5 is used to receive the first clock signal CLK1, and the data output terminal of the fifth trigger D5 is used to output the third synchronization signal sync3. D6 includes a data input terminal (also called D terminal), a data output terminal (also called Q terminal) and a clock input terminal (also called C terminal). The data input terminal of the sixth trigger D6 is used to receive the second synchronization signal sync2, the clock input terminal of the sixth trigger D6 is used to receive the first clock signal CLK1, and the data output terminal of the sixth trigger D6 is used to output the fourth synchronization signal sync4; the fifth trigger D5 is used to delay the first synchronization signal sync1 by T0 to generate the third synchronization signal sync3; the sixth trigger D6 is used to delay the second synchronization signal sync2 by T0 to generate the fourth synchronization signal sync4.

[0109] As shown in Figure 8, the first sampling and delay unit 2251 includes a seventh flip-flop D7 and an eighth flip-flop D8. Both the seventh flip-flop D7 and the eighth flip-flop D8 are rising-edge triggered D flip-flops. Each of the seventh flip-flop D7 and the eighth flip-flop D8 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal). The data input terminal of the seventh flip-flop D7 is used to receive the first synchronization signal sync1, the clock input terminal of the seventh flip-flop D7 is used to receive the second clock signal CLK2, and the data output terminal of the seventh flip-flop D7 is connected to the data input terminal of the eighth flip-flop D8. The clock input terminal of the eighth flip-flop D8 is used to receive the second clock signal CLK2, and the data output terminal of the eighth flip-flop D8 is used to output the first sampling signal res1. The seventh flip-flop D7 is used to sample the first synchronization signal sync1 using the rising edge of the second clock signal CLK2, and the eighth flip-flop D8 is used to delay the data output by the seventh flip-flop D7 by T2 to generate the first sampling signal res1.

[0110] As shown in FIG8 , the second sampling and delay unit 2252 includes a ninth flip-flop D9 and a tenth flip-flop D10. Both the ninth flip-flop D9 and the tenth flip-flop D10 are rising-edge triggered D flip-flops. Each of the ninth flip-flop D9 and the tenth flip-flop D10 includes a data input terminal (terminal D), a data output terminal (terminal Q), and a clock input terminal (terminal C). The data input terminal of the ninth flip-flop D9 is used to receive the second synchronization signal sync2, the clock input terminal of the ninth flip-flop D9 is used to receive the second clock signal CLK2, and the data output terminal of the ninth flip-flop D9 is connected to the data input terminal of the tenth flip-flop D10. The clock input terminal of the tenth flip-flop D10 is used to receive the second clock signal CLK2, and the data output terminal of the tenth flip-flop D10 is used to output the second sampling signal res2. The ninth flip-flop D9 is used to sample the second synchronization signal sync2 using the rising edge of the second clock signal CLK2, and the tenth flip-flop D10 is used to delay the data output by the ninth flip-flop D9 by T2 to generate the second sampling signal res2.

[0111] As shown in FIG8 , the third sub-sampling unit 2253 includes an eleventh flip-flop D11, which is a rising-edge triggered D flip-flop; the eleventh flip-flop D11 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal); the data input terminal of the eleventh flip-flop D11 is used to receive the third synchronization signal sync3, the clock input terminal of the eleventh flip-flop D11 is used to receive the second clock signal CLK2, and the data output terminal of the eleventh flip-flop D11 is used to output the third sampling signal res3; the fourth sub-sampling unit 2254 includes a twelfth flip-flop D12, which is a rising-edge triggered D flip-flop; the twelfth flip-flop D12 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal); the data input terminal of the twelfth flip-flop D12 is used to receive the fourth synchronization signal sync4, the clock input terminal of the twelfth flip-flop D12 is used to receive the second clock signal CLK2, and the data output terminal of the twelfth flip-flop D12 is used to output the fourth sampling signal res4; the eleventh flip-flop D11 is used to use the rising edge of the second clock signal CLK2 to sample the third synchronization signal sync3 to generate the third sampling signal res3; the twelfth flip-flop D12 is used to use the rising edge of the second clock signal CLK2 to sample the fourth synchronization signal sync4 to generate the fourth sampling signal res4.

[0112] The embodiment of the present application provides a sampling device that can sample the electrical signal output by the detection unit at a sampling rate of 2*f0 through the first sampling unit 210 to generate an initial sampling signal, thereby improving the sampling rate and thereby improving the measurement accuracy of the time of flight. The embodiment of the present application provides a sampling device that samples the initial sampling signal at a sampling rate of f0 / 2 through the second sampling unit 220 to generate first to fourth sampling signals, wherein the initial clock signal is a signal in the clock domain of the first clock signal (with a frequency of f0), and the first to fourth sampling signals are signals in the clock domain of the second clock signal (with a frequency of f0 / 2), thereby converting the initial sampling signal in the fast clock domain into the first to fourth sampling signals in the slow clock domain, thereby reducing the clock speed requirements for subsequent sampling signals (i.e., time of flight data) when processing operations, and reducing the computing resources required for subsequent sampling signal processing operations.

[0113] Furthermore, as shown in FIG9 , the sampling device provided by the present application further includes a judgment unit 230 , an output unit 240 and a determination unit (not shown);

[0114] The judging unit 230 is configured to judge whether a transition from 0 to 1 occurs between every two adjacent sampling signals from the first sampling signal to the K*Nth sampling signal, and generate first to K*Nth judgment results;

[0115] An output unit 240 is used to output the first judgment result to the K*Nth judgment result;

[0116] a determination unit, configured to obtain first to K*Nth judgment results, and determine whether the first to K*Nth sampling signals are normal sampling signals according to the first to K*Nth judgment results;

[0117] The output unit 240 is further configured to output the first sampling signal to the K*Nth sampling signal when the first sampling signal to the K*Nth sampling signal are normal sampling signals.

[0118] In a specific embodiment, K=2, N=2. The judgment unit 230 is configured to judge whether a transition from 0 to 1 occurs between each two adjacent sampling signals from the first sampling signal to the fourth sampling signal, and generate first to fourth judgment results. The determination unit is configured to obtain the first to fourth judgment results and determine whether the first to fourth sampling signals are normal sampling signals based on the first to fourth judgment results. The output unit 240 is configured to output the first to fourth judgment results and further configured to output the first to fourth sampling signals when the first to fourth sampling signals are normal sampling signals.

[0119] The sampling device shown in FIG8 and the method embodiment shown in FIG5 are based on the same concept and bring the same technical effects. For the specific process, please refer to the description of the method embodiment shown in FIG5 and will not be repeated here.

[0120] In a specific implementation, referring to FIG. 10 , FIG. 10 is a schematic structural diagram of the judgment unit 230 and the output unit 240 provided in an embodiment of the present application.

[0121] As shown in Figure 10, the judgment unit 230 includes a first sub-judgment unit 231, a second sub-judgment unit 232, a third sub-judgment unit 233 and a fourth sub-judgment unit 234; the first sub-judgment unit 231 is used to judge whether a jump from 0 to 1 occurs between the fourth sampling signal res4 and the first sampling signal res1; the second sub-judgment unit 231 is used to judge whether a jump from 0 to 1 occurs between the first sampling signal res1 and the second sampling signal res2; the third sub-judgment unit 233 is used to judge whether a jump from 0 to 1 occurs between the second sampling signal res2 and the third sampling signal res3; the fourth sub-judgment unit 234 is used to judge whether a jump from 0 to 1 occurs between the third sampling signal res3 and the fourth sampling signal res4.

[0122] As shown in FIG10 , the first sub-judgment unit 231 includes a thirteenth flip-flop D13, a first inverter N, and a first AND gate A1; the thirteenth flip-flop D13 is a rising-edge triggered D flip-flop; the thirteenth flip-flop D13 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal); the data input terminal of the thirteenth flip-flop D13 is used to receive the fourth sampling signal res4, the clock input terminal of the thirteenth flip-flop D13 is used to receive the second clock signal CLK2, and the data output terminal of the thirteenth flip-flop D13 is connected to the input terminal of the first inverter N; one input terminal of the first AND gate A1 is used to receive the first sampling signal res4. s1, the other input end of the first AND gate A1 is connected to the output end of the first inverter N, and the output end of the first AND gate A1 is used to output a fourth judgment result; when a transition from 0 to 1 occurs between the fourth sampling signal res4 and the first sampling signal res1, the fourth judgment result output by the first AND gate A1 is equal to a value of 1; when a transition from 0 to 1 does not occur between the fourth sampling signal res3 and the first sampling signal res1, the fourth judgment result output by the first AND gate A1 is equal to a value of 0; based on the value of the fourth judgment result output by the first AND gate A1, it can be determined whether a transition from 0 to 1 occurs between the fourth sampling signal res4 and the first sampling signal res1.

[0123] As shown in FIG10 , the second sub-determination unit 232 includes a second inverter N2 and a second AND gate A2; an input end of the second inverter N2 is used to receive the second sampling signal res2; one input end of the second AND gate A2 is used to receive the first sampling signal res1, the other input end of the second AND gate A2 is connected to the output end of the second inverter N2, and the output end of the second AND gate A2 is used to output a first determination result; when a transition from 0 to 1 occurs between the first sampling signal res1 and the second sampling signal res2, the first determination result output by the second AND gate A2 is equal to a value of 1; when a transition from 0 to 1 does not occur between the first sampling signal res1 and the second sampling signal res2, the first determination result output by the second AND gate A2 is equal to a value of 0; based on the value of the first determination result output by the second AND gate A2, it can be determined whether a transition from 0 to 1 occurs between the first sampling signal res1 and the second sampling signal res2.

[0124] As shown in FIG10 , the third sub-determination unit 233 includes a third inverter N3 and a third AND gate A3; an input end of the third inverter N3 is used to receive the third sampling signal res3; one input end of the third AND gate A3 is used to receive the second sampling signal res2, the other input end of the third AND gate A3 is connected to the output end of the third inverter N3, and the output end of the third AND gate A3 is used to output a second determination result; when a transition from 0 to 1 occurs between the second sampling signal res2 and the third sampling signal res3, the second determination result output by the third AND gate A3 is equal to a value of 1; when a transition from 0 to 1 does not occur between the second sampling signal res2 and the third sampling signal res3, the second determination result output by the third AND gate A3 is equal to a value of 0; based on the value of the second determination result output by the third AND gate A3, it can be determined whether a transition from 0 to 1 occurs between the second sampling signal res2 and the third sampling signal res3.

[0125] As shown in FIG10 , the fourth sub-determination unit 234 includes a fourth inverter N4 and a fourth AND gate A4; an input terminal of the fourth inverter N4 is used to receive the fourth sampling signal res4; one input terminal of the fourth AND gate A4 is used to receive the third sampling signal res3, the other input terminal of the fourth AND gate A4 is connected to the output terminal of the fourth inverter N4, and the output terminal of the fourth AND gate A4 is used to output a third determination result; when a transition from 0 to 1 occurs between the third sampling signal res3 and the fourth sampling signal res4, the third determination result output by the fourth AND gate A4 is equal to a value of 1; when a transition from 0 to 1 does not occur between the third sampling signal res3 and the fourth sampling signal res4, the third determination result output by the fourth AND gate A4 is equal to a value of 0; based on the value of the third determination result output by the fourth AND gate A4, it can be determined whether a transition from 0 to 1 occurs between the third sampling signal res2 and the fourth sampling signal res3.

[0126] As shown in Figure 10, the output unit 240 includes a first sub-output unit 241, a second sub-output unit 242, a third sub-output unit 243 and a fourth sub-output unit 244; the first sub-output unit 241, the second sub-output unit 242, the third sub-output unit 243 and the fourth sub-output unit 244 are respectively used to output the first judgment result and the second judgment result when it is necessary to output the first judgment result, the second judgment result, the third judgment result and the fourth judgment result; the first sub-output unit 241, the second sub-output unit 242, the third sub-output unit 243 and the fourth sub-output unit 244 are also used to output the first sampling signal res1, the second sampling signal res2, the third sampling signal res3 and the fourth sampling signal res4 when it is necessary to output the first sampling signal res1, the second sampling signal res2, the third sampling signal res3 and the fourth sampling signal res4.

[0127] As shown in FIG11 , the first sub-output unit 241 includes a first data selector M1 and a fourteenth flip-flop D14; the first data selector M1 includes two data input terminals, a data output terminal, and a control signal input terminal; one data input terminal of the first data selector M1 is connected to the output terminal of the first AND gate A1 for receiving the first judgment result; the other data input terminal of the first data selector M1 is connected to the output terminal of the fourteenth flip-flop D14 for receiving the first sampling signal res1; the control signal input terminal of the first data selector M1 receives a control signal; the first data selector M1 is configured to output the first selection result or the first sampling signal res1 through the output terminal under the control of the control signal; the fourteenth flip-flop D14 is a rising-edge triggered D flip-flop; the fourteenth flip-flop D14 includes a data input terminal (D terminal), a data output terminal (Q terminal), and a clock input terminal (C terminal); The data input end of the fourteenth flip-flop D14 is connected to the output end of the first data selector M1, the clock input end of the fourteenth flip-flop D14 is used to receive the second clock signal CLK2, and the data output end of the fourteenth flip-flop D14 is used to output the first judgment result or the first sampling signal res1 synchronized with the second clock signal CLK2.

[0128] As shown in FIG11 , the second sub-output unit 242 includes a second data selector M2 and a fifteenth flip-flop D15; the second data selector M2 includes two data input terminals, a data output terminal and a control signal input terminal, one data input terminal of the second data selector M2 is connected to the output terminal of the second AND gate A2 for receiving the second judgment result, the other data input terminal of the second data selector M2 is connected to the output terminal of the fifteenth flip-flop D15 for receiving the second sampling signal res2, the control signal input terminal of the second data selector M1 receives the control signal, and the second data selector M2 is used to generate a control signal when the control signal is Under control, the second selection result or the second sampling signal res2 is output through the output end; the fifteenth trigger D15 is a rising edge triggered D trigger; the fifteenth trigger D15 includes a data input end (D end), a data output end (Q end) and a clock input end (C end), the data input end of the fifteenth trigger D15 is connected to the output end of the second data selector M2, the clock input end of the fifteenth trigger D15 is used to receive the second clock signal CLK2, and the data output end of the fifteenth trigger D15 is used to output the second judgment result or the second sampling signal res2 synchronized with the second clock signal CLK2.

[0129] As shown in FIG11 , the third sub-output unit 243 includes a third data selector M3 and a sixteenth flip-flop D16; the third data selector M3 includes two data input terminals, a data output terminal, and a control signal input terminal. One data input terminal of the third data selector M3 is connected to the output terminal of the third AND gate A3 for receiving the third judgment result. The other data input terminal of the third data selector M3 is connected to the output terminal of the sixteenth flip-flop D16 for receiving the third sampling signal res3. The control signal input terminal of the third data selector M3 receives the control signal. The third data selector M3 is used to generate a control signal when the control signal is Under control, the third selection result or the third sampling signal res3 is output through the output end; the sixteenth flip-flop D16 is a rising-edge triggered D flip-flop; the sixteenth flip-flop D16 includes a data input end (D end), a data output end (Q end) and a clock input end (C end), the data input end of the sixteenth flip-flop D16 is connected to the output end of the third data selector M3, the clock input end of the sixteenth flip-flop D16 is used to receive the second clock signal CLK2, and the data output end of the sixteenth flip-flop D16 is used to output the third judgment result or the third sampling signal res3 synchronized with the second clock signal CLK2.

[0130] As shown in FIG11 , the fourth sub-output unit 244 includes a third data selector M4 and a seventeenth flip-flop D17; the fourth data selector M4 includes two data input terminals, a data output terminal, and a control signal input terminal. One data input terminal of the fourth data selector M4 is connected to the output terminal of the fourth AND gate A4 for receiving the fourth judgment result, and the other data input terminal of the fourth data selector M4 is connected to the output terminal of the seventeenth flip-flop D17 for receiving the fourth sampling signal res4. The control signal input terminal of the fourth data selector M4 receives the control signal, and the fourth data selector M4 is used to generate a control signal when the control signal is Under control, the fourth selection result or the fourth sampling signal res4 is output through the output terminal; the seventeenth trigger D17 is a rising edge triggered D trigger; the seventeenth trigger D17 includes a data input terminal (D terminal), a data output terminal (Q terminal) and a clock input terminal (C terminal), the data input terminal of the seventeenth trigger D17 is connected to the output terminal of the fourth data selector M4, the clock input terminal of the seventeenth trigger D17 is used to receive the second clock signal CLK2, and the data output terminal of the seventeenth trigger D17 is used to output the fourth judgment result or the fourth sampling signal res4 synchronized with the second clock signal CLK2.

[0131] Specifically, when the confirmation unit 250 needs to determine whether the first sampling signal to the K*Nth sampling signal are normal sampling signals based on the first judgment result to the K*Nth judgment result, the control signal is in the first state (for example, a high level) to control the first data selector M1, the second data selector M2, the third data selector M3 and the fourth data selector M4 to output the first selection result, the second selection result, the third selection result and the fourth selection result respectively, and output the first judgment result, the second judgment result, the third judgment result and the fourth judgment result synchronized with the second clock signal CLK2 to the determination unit through the fourteenth trigger D14, the fifteenth trigger D15, the sixteenth trigger D16 and the seventeenth trigger D17 respectively. When the determination unit determines that the first sampling signal res1, the second sampling signal res2, the third sampling signal res3 and the fourth sampling signal res4 are normal sampling signals based on the first judgment result, the second judgment result, the third judgment result and the fourth judgment result, the control signal is in the second state (for example, a low level) to control the first data selector M1, the second data selector M2, the third data selector M3 and the fourth data selector M4 to output the first sampling signal res1, the second sampling signal res2, the third sampling signal res3 and the fourth sampling signal res4 respectively.

[0132] The above describes in detail a sampling device according to an embodiment of the present application. The following provides a laser ranging device according to an embodiment of the present application. In a third aspect, as shown in FIG12 , the laser ranging device may include: a transmitter 60, a detector 10, a processor 910, a communication interface 920, a memory 930, and a communication bus 940. The transmitter 60 includes one or more light-emitting units 601 for emitting pulsed light signals. The detector 10 includes one or more detection units 101 for receiving light signals. Each light-emitting unit 601 corresponds to one or more detection units 101. The processor 910, the communication interface 920, and the memory 930 communicate with each other via the communication bus 940. The communication interface 920 is used to communicate with network elements of other devices such as clients or other servers. The memory 930 is used to store computer programs or instructions 903 for implementing the above method embodiments (i.e., sampling methods) or the various units of the device embodiments (i.e., sampling devices). The processor 910 is connected to the transmitter 60 and the detector 10 through the communication interface 920, and is used to call the computer program or instruction 903 to execute the operations of the above method embodiments, such as S110 to S120 shown in Figure 2, S111 to S112 shown in Figure 3, and S110 to S150 shown in Figure 5.

[0133] The laser ranging device provided in the present application determines the flight time from the first sampling signal to the K*Nth sampling signal (for example, the first sampling signal to the fourth sampling signal) output by the above-mentioned method embodiment or device embodiment, and then generates a point cloud map based on the flight time. By processing the point cloud map, parameters such as the distance, direction, height, speed, posture and shape of the obstacle are obtained, thereby realizing the laser detection function, and can be applied to navigation avoidance, obstacle identification, ranging, speed measurement, automatic driving and other scenarios of products such as automobiles, robots, logistics vehicles, and inspection vehicles.

[0134] Specifically, in some embodiments, the emitter 60 includes a light-emitting unit 601. In this case, the emitter 60 can be a vertical-cavity surface-emitting laser (VCSEL), an edge-emitting laser (EEL), a light-emitting diode (LED), a micro light-emitting diode (Micro LED), a pulsed laser deposition (PLD), or a laser diode (LD). The present application does not limit the type of the emitter 60.

[0135] In some other embodiments, the emitter 60 includes a plurality of light-emitting units 601; the plurality of light-emitting units 601 may be arranged in an array, that is, the emitter 60 may be a laser array. In this case, the emitter 60 may be a vertical-cavity surface-emitting laser (VCSEL) array, an edge-emitting laser (EEL) array, a light-emitting diode (LED) array, a micro light-emitting diode (Micro LED) array, a pulsed laser deposition (PLD) array, or a laser diode (LD) array, etc. The present application does not limit the type of emitter 60.

[0136] In some embodiments, the detector 10 includes a detection unit 101. In this case, the detector 10 can adopt a single photon avalanche diode (SPAD) or a silicon photomultiplier (SIPM), and the present application does not limit the type of the detector 10. In other embodiments, the detector 10 includes multiple detection units 101, and the multiple detection units 101 are arranged in an array, that is, the detector 10 can be a detector array. In this case, the detector 10 can adopt a single photon avalanche diode (SPAD) array or a silicon photomultiplier (SIPM) array, and the present application does not limit the type of the detector 10.

[0137] Furthermore, when the transmitter 60 includes multiple light-emitting units 601, the multiple light-emitting units 601 can emit light in sequence to scan and transmit the pulsed light signal to the detection area to scan for obstacles within the detection area. Accordingly, the detection unit 101 in the detector 10 is used to detect the echo light signal reflected by the obstacles within the detection area.

[0138] Specifically, the processor 910 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0139] The memory 930 may be an internal storage unit of the laser distance measuring device, such as a hard disk or memory of the laser distance measuring device. The memory 930 may also be an external storage device of the laser distance measuring device, such as a plug-in hard disk equipped on the laser distance measuring device, a smart memory card (SMC), a secure digital (SD) card, a flash card, etc. Furthermore, the memory 930 may include both an internal storage unit of the laser distance measuring device and an external storage device. The memory 930 is used to store the computer program and other programs and data required by the terminal device. The memory 930 may also be used to temporarily store data that has been output or is about to be output.

[0140] The embodiment of the present application further provides a computer-readable storage medium storing at least one executable instruction, which implements the above-mentioned sampling method when executed by a processor.

[0141] An embodiment of the present application provides a computer program product. When the computer program product is run on a laser ranging device, the laser ranging device can implement the above-mentioned sampling method when executing the computer program product.

[0142] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the terminal device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the above-mentioned embodiments, the description of each embodiment has its own focus. For the part that is not described or recorded in detail in a certain embodiment, refer to the relevant description of other embodiments.

[0143] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0144] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A sampling method, characterized in that: include: The electrical signal output by the detection unit is sampled at a sampling rate of N*f0 to generate an initial sampling signal; wherein f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1; The K*N sampling data of the K adjacent clock cycles of the initial sampling signal are sampled at a sampling rate of f0 / K to generate a first sampling signal to a K*Nth sampling signal; wherein K is a positive integer greater than 1.

2. The sampling method according to claim 1, characterized in that: N＝2； The step of sampling the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal comprises: Using the rising edge of the first clock signal to sample the electrical signal output by the detection unit to generate a first initial sampling signal; The electrical signal output by the detection unit is sampled using the falling edge of the first clock signal to generate a second initial sampling signal; wherein the first initial sampling signal and the second initial sampling clock signal constitute the initial clock signal.

3. The sampling method according to claim 2, characterized in that: K=2; sampling K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal includes: Synchronize the first initial sampling signal with the first clock signal to generate a first synchronization signal; synchronize the second initial sampling signal with the first clock signal to generate a second synchronization signal; After delaying the first synchronization signal by T0, a third synchronization signal is generated; after delaying the second synchronization signal by T0, a fourth synchronization signal is generated; wherein T0 is the clock period of the first clock signal, and T0=1 / f0; The first synchronization signal is sampled by the rising edge of the second clock signal and delayed by T2 to generate a first sampling signal; the second synchronization signal is sampled by the rising edge of the second clock signal and delayed by T2 to generate a second sampling signal; the third synchronization signal is sampled by the rising edge of the second clock signal to generate a third sampling signal; the fourth synchronization signal is sampled by the rising edge of the second clock signal to generate a fourth sampling signal; wherein the clock frequency of the second clock signal is f0 / 2, the clock period of the second clock signal is T2, and T2=2 / f0.

4. The method according to claim 1, characterized in that After sampling K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate the first sampling signal to the K*Nth sampling signal, the method further includes: Determine whether a jump from 0 to 1 occurs between every two adjacent sampling signals from the first sampling signal to the K*Nth sampling signal, and generate first to K*Nth determination results; Outputting the first judgment result to the K*Nth judgment result; Obtain the first to K*Nth judgment results to determine whether the first to K*Nth sampling signals are normal sampling signals; when the first to K*Nth sampling signals are normal sampling signals, output the first to K*Nth sampling signals.

5. A sampling device, characterized in that: include: A first sampling unit, used to sample the electrical signal output by the detection unit at a sampling rate of N*f0 to generate an initial sampling signal; wherein f0 is the clock frequency of the first clock signal, and N is a positive integer greater than 1; The second sampling unit is used to sample K*N sampling data of K adjacent clock cycles of the initial sampling signal at a sampling rate of f0 / K to generate a first sampling signal to a K*Nth sampling signal; wherein K is a positive integer greater than 1.

6. The sampling device according to claim 5, characterized in that: N＝2； The first sampling unit comprises: a first sub-sampling unit, sampling the electrical signal output by the detection unit using the rising edge of the first clock signal to generate a first initial sampling signal; The second sub-sampling unit samples the electrical signal output by the detection unit using the falling edge of the first clock signal to generate a second initial sampling signal.

7. The sampling device according to claim 6, characterized in that: K=2; the second sampling unit includes: A first synchronization unit, configured to synchronize the first initial sampling signal with the first clock signal to generate a first synchronization signal; A second synchronization unit, configured to synchronize the second initial sampling signal with the first clock signal to generate a second synchronization signal; A first delay unit, used for delaying the first synchronization signal by T0 to generate a third synchronization signal; A second delay unit, used for delaying the second synchronization signal by T0 to generate a fourth synchronization signal; wherein T0 is a clock period of the first clock signal, and T0=1 / f0; A first sampling and delay unit, configured to sample the first synchronization signal using a rising edge of a second clock signal and delay the sample by T2 to generate a first sampling signal; A second sampling and delay unit, configured to sample the second synchronization signal using the rising edge of the second clock signal and generate a second sampling signal after a delay of T2; wherein the clock frequency of the second clock signal is f0 / 2, the clock period of the second clock signal is T2, and T2=2 / f0; A third sub-sampling unit, configured to sample the third synchronization signal using a rising edge of the second clock signal to generate a third sampling signal; The fourth sub-sampling unit is used to sample the fourth synchronization signal using the rising edge of the second clock signal to generate a fourth sampling signal.

8. The sampling device according to claim 7, characterized in that: Also includes: a judgment unit, used for judging whether a jump from 0 to 1 occurs between every two adjacent sampling signals from the first sampling signal to the K*Nth sampling signal, and generating first judgment results to the K*Nth judgment results; An output unit, used for outputting the first judgment result to the K*Nth judgment result; a determination unit, configured to obtain the first to K*Nth judgment results, and determine whether the first to K*Nth sampling signals are normal sampling signals according to the first to K*Nth judgment results; The output unit is further configured to output the first sampling signal to the K*Nth sampling signal when the first sampling signal to the K*Nth sampling signal are normal sampling signals.

9. A computer-readable storage medium storing at least one executable instruction, wherein the executable instruction, when executed by a processor, implements the method according to any one of claims 1 to 4.

10. A laser distance measuring device, characterized in that: include: Transmitters, detectors, processors, communication interfaces, memories, and communication buses; The processor communicates with the transmitter and the detector via the communication interface; The processor, the communication interface and the memory communicate with each other via the communication bus; The transmitter includes one or more light-emitting units for emitting pulsed light signals; The detector includes one or more detection units for receiving optical signals; The memory is used to store computer programs or instructions; The processor is configured to execute the computer program or instructions in the memory to implement the method according to any one of claims 1 to 4.

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