Data rereading method, memory and storage medium

Abstract

The invention relates to the technical field of EMMC research and development performance, in particular to a data rereading method, a memory and a storage medium, the method comprises the following steps: counting the number of basic storage units respectively corresponding to n data states in a flash memory page to obtain n numbers which are counted as N0, N1,..., Nn-1, and n is greater than or equal to 2; determining the voltage distribution offset state of the flash memory page according to the size relation between N0 and Nn-1; determining the offset direction of the rereading voltage according to the voltage distribution offset state of the flash memory page, and screening out a corresponding offset voltage value from the rereading table according to the offset direction; and according to the offset voltage value, executing a re-reading process to correct back data or ending the re-reading process after a preset re-reading frequency is reached. Therefore, the problems that when the NAND Flash executes the rereading process, the number of times of Retry table traversal is large, and the time consumed by the rereading process is long can be effectively solved.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and in particular, to a data rereading method, a memory, and a storage medium. Background Art

[0002] The Read Retry technology is used when data errors that cannot be corrected occur in a flash memory page. By adjusting the internal read reference voltage, it is hoped that the data states stored in the basic memory cells can be correctly distinguished under the adjusted read reference voltage, and then the rereading process is executed to send a read operation to the NAND Flash and attempt to correctly read the data stored in the basic memory cells. Among them, the Retry table (reread table) will be used in the Read Retry technology. The Retry table is a table that stores the read voltage offset each time. However, there are multiple groups of Read Retry values in the Retry table, corresponding to the voltage amplitudes and adjustment directions to be adjusted in their respective scenarios.

[0003] Generally, manufacturers will provide the Retry table, but the Retry tables provided by manufacturers are all offset voltage values without distinguishing scenarios. As a result, during use, the entire Retry table is often traversed through retry to try all read retry values until the data is correctly read. This method results in a large number of traversals of the Retry table, and the retry flow takes a lot of time, causing a serious decline in read performance. Summary of the Invention

[0004] In view of this, the embodiments of this application provide a data rereading method, a memory, and a storage medium, which can effectively solve the problems such as the large number of traversals of the Retry table when the NAND Flash executes the rereading process and the long time consumed by the rereading process.

[0005] In a first aspect, the embodiments of this application provide a data rereading method, including: Count the number of basic memory cells corresponding to n data states in the flash memory page to obtain n quantities, denoted as N0, N1,..., N n-1 , where n≥2; According to the magnitude relationship between N0 and N n-1 , determine the voltage distribution offset state of the flash memory page; Determine the offset direction of the rereading voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; Execute the rereading process to correct the data according to the offset voltage value or end the rereading process after reaching the preset rereading times.

[0006] In some embodiments, the data states of the basic memory cells include: "0" and "1". Statistical flash memory pages in which the number of basic memory cells corresponding to n data states are obtained, including n quantities: Statistical flash memory pages in which the number of basic memory cells corresponding to the "0" state and the "1" state are obtained, corresponding to N0 and N1 respectively.

[0007] In some embodiments, according to the size relationship between N0 and N n-1 To determine the voltage distribution offset state of the flash memory page, including: Compare the sizes of N0 and N1; If N0 is equal to N1, the voltage distribution offset state of the flash memory page is unbiased; And / or, if N0 is greater than N1, the voltage distribution offset state of the flash memory page is right-biased; And / or, if N0 is less than N1, confirm that the voltage distribution offset state of the flash memory page is left-biased.

[0008] In some embodiments, when the flash memory page is configured in the MLC mode, the data states of the basic memory cells include: "00", "01", "10", and "11"; Statistical flash memory pages in which the number of basic memory cells corresponding to n data states are obtained, including: Statistical flash memory pages in which the number of basic memory cells corresponding to the "11" state, "01" state, "00" state, and "10" state are obtained, corresponding to N0, N1, N2, and N3 in sequence.

[0009] In some embodiments, according to the size relationship between N0 and N n-1 To determine the voltage distribution offset state of the flash memory page, including: Obtain the flash memory page type; Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0, N1, N2, and N3.

[0010] In some embodiments, the flash memory page type includes: low-order pages and high-order pages; Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0, N1, N2, and N3, including: If the flash memory page type is a low-order page, for the threshold voltage R2, compare the sizes of N0 + N1 and N2 + N3: If N0 + N1 > N2 + N3, the voltage distribution offset state of the flash memory page is left-biased; If N0 + N1 < N2 + N3, the voltage distribution offset state of the flash memory page is right - biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; When the flash memory page type is a high - order page, for the threshold voltage R1, compare the magnitudes of 3×N0 and N1 + N2 + N3: If 3×N0 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left - biased; If 3×N0 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right - biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R3, compare the magnitudes of 3×N2 and N1 + N2 + N3: If 3×N2 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left - biased; If 3×N2 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right - biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased.

[0011] In some embodiments, when the flash memory page is configured in the TLC mode, the data states of the basic storage units include: "000", "001", "010", "011", "100", "101", "110", and "111"; Statistically count the number of basic storage units corresponding to n data states in the flash memory page, obtaining n quantities, including: Statistically count the number of basic storage units corresponding to the "111" state, "110" state, "100" state, "000" state, "010" state, "011" state, "001" state, and "101" state in the flash memory page, and correspondingly obtain N0, N1, N2, N3, N4, N5, N6, and N7 in sequence.

[0012] In some embodiments, determine the voltage distribution offset state of the flash memory page according to the size relationship between N0 and N n-1 including: Obtain the flash memory page type; Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0 and N7.

[0013] In some embodiments, the flash memory page types include: low - order pages, high - order pages, and super - pages; Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0 and N7, including: If the flash memory page type is a low-order page, for the threshold voltage R1, compare the magnitudes of 7×N0 and N1+N2+N3+N4+N5+N6+N7: If 7×N0 is greater than N1+N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is left-offset; If 7×N0 is less than N1+N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is right-offset; If they are equal, then the voltage distribution offset state of the flash memory page is non-offset; For the threshold voltage R5, compare the magnitudes of 3×(N1+N2+N3+N4) and 5×(N5+N6+N7): If 3×(N1+N2+N3+N4) is greater than 5×(N5+N6+N7), then the offset state of the voltage distribution of the flash memory page is left-offset; If 3×(N1+N2+N3+N4) is less than 5×(N5+N6+N7), then the voltage distribution offset state of the flash memory page is right-offset; if they are equal, then the voltage distribution offset state of the flash memory page is non-offset; If the flash memory page type is a high-order page, for the threshold voltage R2, compare the magnitudes of 3×(N0+N1) and N2+N3+N4+N5+N6+N7: If 3×(N0+N1) is greater than N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is left-offset; If 3×(N0+N1) is less than N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is right-offset; if they are equal, then the voltage distribution offset state of the flash memory page is non-offset; For the threshold voltage R4, compare the magnitudes of N0+N1+N2+N3 and N4+N5+N6+N7: If N0+N1+N2+N3 is greater than N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is left-offset; if N0+N1+N2+N3 is less than N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is right-offset; if they are equal, then the voltage distribution offset state of the flash memory page is non-offset; For the threshold voltage R6, compare the magnitudes of N0+N1+N2+N3+N4+N5 and 3×(N6+N7): If N0+N1+N2+N3+N4+N5 is greater than 3×(N6+N7), then the voltage distribution offset state of the flash memory page is left-offset; if N0+N1+N2+N3+N4+N5 is less than 3×(N6+N7), then the voltage distribution offset state of the flash memory page is right-offset; if they are equal, then the voltage distribution offset state of the flash memory page is non-offset; If the flash memory page type is an intermediate bit page, for the threshold voltage R3, compare the magnitudes of 5×(N0 + N1 + N2) and 3×(N3 + N4 + N5 + N6 + N7): If 5×(N0 + N1 + N2) is greater than 3×(N3 + N4 + N5 + N6 + N7), then the voltage distribution offset state of the flash memory page is left - biased; If 5×(N0 + N1 + N2) is less than 3×(N3 + N4 + N5 + N6 + N7), then the voltage distribution offset state of the flash memory page is right - biased; If they are equal, then the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R7, compare the magnitudes of N1 + N2 + N3 + N4 + N5 + N6 and 7×N7: If N1 + N2 + N3 + N4 + N5 + N6 is greater than 7×N7, then the voltage distribution offset state of the flash memory page is left - biased; if N1 + N2 + N3 + N4 + N5 + N6 is less than 7×N7, then the voltage distribution offset state of the flash memory page is right - biased; if they are equal, then the voltage distribution offset state of the flash memory page is unbiased.

[0014] In some embodiments, determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; including: If the voltage distribution offset state of the flash memory page is right - biased, then screen out the offset voltage value greater than zero from the reread table; And / or, if the voltage distribution offset state of the flash memory page is left - biased, then screen out the offset voltage value less than zero from the reread table.

[0015] In a second aspect, an embodiment of the present application provides a memory, which is used to store a computer program for implementing a data reread method provided in the first aspect of the present application, and uses the data reread method provided in the first aspect of the present application to correct data when a read data error occurs.

[0016] In a third aspect, an embodiment of the present application provides a readable storage medium, which stores a computer program, and when the computer program is executed on a processor, implements a data reread method provided in the first aspect of the present application.

[0017] The embodiments of the present application have the following beneficial effects: In the present application, the number of basic storage units corresponding to n data states in a flash memory page is statistically obtained to get n numbers, denoted as N0, N1, …, N n-1 , n≥2; according to N0 to N n-1Determine the voltage distribution offset state of the flash memory page according to the magnitude relationship between them; determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; execute the reread process to recover the data according to the offset voltage value or end the reread process after reaching the preset reread times. The present application uses the Read retry technology to execute the reread process according to the accurate voltage threshold determined by the voltage distribution offset state to recover the data, which can effectively solve the problems such as the large number of times of traversing the Retry table and the long time-consuming of the reread process when the NAND Flash executes the reread process, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without creative efforts.

[0019] Figure 1 Shows a flowchart of a data reread method according to an embodiment of the present application; Figure 2 Shows a schematic diagram of the voltage distribution offset state of the MLC standard unbiased in the data reread method according to an embodiment of the present application; Figure 3 Shows a schematic diagram of the voltage distribution offset state of the TLC standard unbiased in the data reread method according to an embodiment of the present application; Figure 4 Shows a flowchart of a data reread method according to an embodiment of the present application when the flash memory page is configured as the SLC type; Figure 5 Shows a flowchart of a data reread method according to an embodiment of the present application when the flash memory page is configured as the MLC type; Figure 6-1 Shows a first part of the flowchart of a data reread method according to an embodiment of the present application when the flash memory page is configured as the TLC type; Figure 6-2 Shows a second part of the flowchart of a data reread method according to an embodiment of the present application when the flash memory page is configured as the TLC type; Figure 6-3 Shows a third part of the flowchart of a data reread method according to an embodiment of the present application when the flash memory page is configured as the TLC type; Figure 7 Shows a schematic diagram of the structure of a reread process execution device according to an embodiment of the present application.

[0020] MAIN ELEMENT SYMBOL DESCRIPTION: 710 - Statistical module; 720 - Offset status determination module; 730 - Offset voltage value determination module; 740 - Re - reading module. Detailed implementation manners

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0022] The components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but only represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0023] In the following, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0024] Unless otherwise defined, all terms (including technical terms and scientific terms) used here have the same meaning as those commonly understood by those of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in a commonly used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or being overly formal, unless clearly defined in the various embodiments of the present application.

[0025] The following will describe some implementation manners of the present application in detail with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0026] Read Retry flow (Read Retry process), the normal read process of EMMC (Embedded Multi Media Card Embedded Non-Volatile Memory System), takes the page (flash memory page) as the smallest operation unit. If the returned read page passes, it means that the read process of this page directly passes (succeeds) and there is no need to perform the Read Retry flow; once the read page returns fail (fails), it will enter the Read Retry flow. This process first starts to set the offset (offset voltage value) according to the Retry table, and then performs the read operation again; if it returns Pass, the data is recovered in this retry; if it fails, continue to reset the next offset (offset voltage value) in the Retry table, adjust the read voltage and then perform the next read operation until the Read operation Passes or reaches the maximum number of retries. In the prior art, when performing the Read Retry flow, the Retry table is usually traversed, and the voltage offset values in it are tried one by one, resulting in a large number of traversals of the Retry table. The Read Retry flow takes a lot of time and causes a serious decline in read performance. Therefore, this application proposes a data reread method, a memory and a storage medium, which can effectively solve the problems such as the large number of traversals of the Retry table when NAND Flash performs the reread process and the long time consumed by the reread process.

[0027] The main idea of this application: propose a method to classify the Retry table according to the scenario, that is, determine whether the voltage distribution offset state of the flash memory page (also known as the Vt distribution) is left-biased or right-biased according to the voltage distribution offset state of the flash memory page, and classify according to left-biased and right-biased. For example, when screening out the left-biased ones, skip the offset voltage values in the Retry table where the retry voltage is right-biased, and about half of the offset voltage values in the Retry table will be screened out, thereby reducing the number of traversals of the Retry table, shortening the retry flow time, and further optimizing the performance of the Read Retry flow. It also provides a starting solution for further subdividing scenarios in the future (data retention, life consumption, read / write interference). In other words, according to the fact that the cells in each state should be 1:1:1:1 under normal circumstances, this application directly compares the quantities of each state to confirm whether the overall offset of this flash memory page is left-biased or right-biased.

[0028] The following will illustrate this data reread method in combination with some specific embodiments.

[0029] Figure 1 FIG. 1 shows a flowchart of a data rereading method according to an embodiment of the present application. Exemplarily, the data rereading method includes the following steps: S10. Count the number of basic storage cells corresponding to n data states in the flash memory page respectively, to obtain n numbers, denoted as N0, N1, …, N n-1 , where n≥2.

[0030] Where the basic storage cell cell is also called the flash memory basic storage cell.

[0031] The flash memory page is a logical concept. The flash memory page page is composed of cells (flash memory basic storage cells) on the same word line. The number of pages on a word line is determined by the ability of the cell to store bits. A single cell in SLC memory can store 1 bit of information, MLC can store 2 bits, TLC is 3 bits, and QLC is 4 bits.

[0032] According to the types of NAND Flash memory chips, it includes SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quad-Level Cell). Each storage cell in the SLC chip stores one binary bit, that is, "1 and 0", and the corresponding cell has two data states; each storage cell in the MLC chip stores two binary bits, that is, there are four states "11, 01, 00, and 10", and the corresponding cell has four data states; each storage cell in the TLC chip stores three binary bits, that is, there are eight states "111, 101, 100, 110, 000, 001, 010, and 011", and the corresponding cell has eight data states; correspondingly, the voltage thresholds used to distinguish different states change from low to high.

[0033] When reading the data in the page, the threshold voltage (abbreviation: R) needs to be used. Different types of NAND Flash use different numbers of threshold voltages, and each threshold voltage is located at the intersection of adjacent Vt distribution curves. During the read operation, the threshold voltage should be known to determine the charge level and thus the data stored in the memory cell. Specifically, SLC has only one threshold voltage; MLC has three threshold voltages R, which are R1, R2, and R3 respectively. TLC has 7 threshold voltages, which are R1, R2, R3, R4, R5, R6, and R7 respectively.

[0034] Under normal circumstances, the number of data states of cells in SLC, MLC, and TLC is equal after randomization. Therefore, according to this characteristic, as long as the quantity relationship of each data state is obtained, it can be determined whether the Vt is left-biased or right-biased; for SLC, it only needs to count the number of 0s and 1s to make a judgment, while for MLC and TLC, it is more troublesome and requires statistics in combination with the number of cells corresponding to each data state.

[0035] After a Read operation Fail, it enters the Read Retry flow. At this time, first count the number of cells corresponding to each data state of the page and record the quantities separately.

[0036] S20, according to the size relationship between N0 and N n-1 Determine the voltage distribution offset state of the flash page.

[0037] S30, determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; In this embodiment, the Vt distribution offset states include unbiased, left-biased, and right-biased. For example, Figure 2 is the voltage distribution offset state diagram of MLC standard unbiased, Figure 3 is the voltage distribution offset state diagram of TLC standard unbiased. If the voltage distribution offset state is left-biased, skip the offset voltage values in the Retry table with right-biased offset voltage values; if the voltage distribution offset state is right-biased, skip the offset voltage values in the Retry table with left-biased offset voltage values.

[0038] S40, execute the reread process according to the offset voltage value to recover the data or end the reread process after reaching the preset reread times.

[0039] In one implementation, when the flash page is configured in SLC mode, the data states of the basic storage units include: "0" and "1".

[0040] In step S10, count the number of basic storage units corresponding to n data states in the flash page to obtain n quantities, including: Count the number of basic storage units corresponding to the "0" state and the "1" state in the flash page, and correspondingly obtain N0 and N1.

[0041] Furthermore, in step S20, according to the size relationship between N0 and N n-1 Determine the voltage distribution offset state of the flash page, including: S211, compare the sizes of N0 and N1.

[0042] S212, if N0 is equal to N1, the voltage distribution offset state of the flash memory page is unbiased.

[0043] S213, if N0 is greater than N1, the voltage distribution offset state of the flash memory page is right-biased.

[0044] S214, if N0 is less than N1, confirm that the voltage distribution offset state of the flash memory page is left-biased.

[0045] Exemplarily, as Figure 4 shown, the data rereading method for this SLC embodiment includes: S110, determine whether read page needs to execute the rereading process.

[0046] After Read operation Fail, enter the Read Retry flow and execute S120 to count the status of each data.

[0047] S120, if the rereading process needs to be executed, count the number of cells corresponding to the "0" state and the "1" state of the flash memory page respectively, and obtain N0 and N1 correspondingly.

[0048] That is to say, in step S10, the number of cells corresponding to n data states in the page is counted, and n numbers are obtained, including: counting the number of cells corresponding to the "0" state and the "1" state in the page respectively, and obtaining N0 and N1 correspondingly.

[0049] S130, judge whether N0 and N1 are equal. That is, compare the magnitudes of N0 and N1; if N0 is equal to N1, execute step S140; if they are not equal, execute step S150.

[0050] S140, confirm that the voltage distribution offset state of the flash memory page is unbiased.

[0051] S150, judge whether N0 is greater than N1. If N0 is greater than N1, execute step S160; if N0 is less than N1, execute step S170.

[0052] S160, confirm that the voltage distribution offset state of the flash memory page is right-biased. Furthermore, it is necessary to screen out the offset voltage values greater than 0 from the rereading table as the accurate offset voltage values.

[0053] S170. Confirm that the voltage distribution offset state of the flash memory page is left - biased. Further, it is necessary to filter out the offset voltage values less than 0 from the retry table as the accurate offset voltage values. That is to say, after determining whether the Vt distribution (also known as the voltage distribution offset state) is left - biased or right - biased, the Retry table can be distinguished into two cases, and the offset voltage values corresponding to the corresponding scenarios can be filtered out; if the Vt distribution is left - biased, it means that the read voltage also needs to move to the left to read correctly, so the offsets greater than 0 in the Retry table can be filtered out, and the offsets greater than 0 can be directly skipped; similarly, when it is right - biased, the offsets less than 0 in the Retry table can be filtered out.

[0054] That is to say, in step S20, determining the voltage distribution offset state of the flash memory page according to the size relationship between N0 and N n-1 includes steps S130, S140, S150, S160, and S170.

[0055] S180. Perform the retry flow according to the obtained accurate offset voltage values.

[0056] In one implementation, when the flash memory page is configured in the MLC mode, the data states of the basic storage units include: "00", "01", "10", and "11". MLC has three threshold voltages R, namely R1, R2, and R3.

[0057] Count the number of basic storage units corresponding to n data states in the flash memory page, including: Count the number of basic storage units corresponding to the "11" state, "01" state, "00" state, and "10" state in the flash memory page, and obtain N0, N1, N2, and N3 in sequence.

[0058] In step S20, determine the voltage distribution offset state of the flash memory page according to the size relationship between N0 and N n-1 includes: S221. Obtain the flash memory page type.

[0059] S222. Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0, N1, N2, and N3.

[0060] Furthermore, the flash memory page types include: lower page and upper page. Different cases are run according to different flash memory page types. For the lower page and the upper page, the retry flow only needs to know the corresponding threshold voltages.

[0061] According to the coding method lower page, only the offset of the threshold voltage R2 needs to be known to confirm the offset state of lowerpage, so as to screen the retry table for the retry flow.

[0062] Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0, N1, N2, and N3, including: S2221. When the flash memory page type is the lower page, for the threshold voltage R2, compare the magnitudes of N0 + N1 and N2 + N3: If N0 + N1 > N2 + N3, the voltage distribution offset state of the flash memory page is left-offset; If N0 + N1 < N2 + N3, the voltage distribution offset state of the flash memory page is right-offset; If they are equal, the voltage distribution offset state of the flash memory page is non-offset, and the retry flow can be directly performed.

[0063] In other words, first determine whether Equation 1 holds, where Equation 1 is: (N0 + N1) = (N2 + N3); if Equation 1 holds, it means that the voltage distribution offset state of the flash memory page is non-offset, and the retry flow is directly performed; otherwise, further determine whether the voltage distribution offset state of the flash memory page is left-offset or right-offset. If (N0 + N1) > (N2 + N3), it means that the voltage distribution offset state of the flash memory page is left-offset, and vice versa for right-offset.

[0064] However, for the upper page, the offset state needs to be confirmed according to the two threshold voltages R1 and R3.

[0065] S2222. When the flash memory page type is the upper page, for the threshold voltage R1, compare the magnitudes of 3×N0 and N1 + N2 + N3: If 3×N0 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-offset; If 3×N0 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right-offset; If they are equal, the voltage distribution offset state of the flash memory page is non-offset, and it is confirmed that the voltage distribution offset states on both sides of the threshold voltage R1 are non-offset.

[0066] Exemplarily, first determine whether Equation 2 holds. Equation 2 is (3×N0) = (N1 + N2 + N3). If they are equal, it means that the voltage distribution offset states on both sides of the threshold voltage R1 are non-offset. If it is greater, left-offset is confirmed, otherwise right-offset is confirmed.

[0067] S2223. For the threshold voltage R3, compare the magnitudes of 3×N2 and N1 + N2 + N3: If 3×N2 is greater than N1+N2+N3, the voltage distribution offset state of the flash memory page is left-biased; If 3×N2 is less than N1+N2+N3, the voltage distribution offset state of the flash memory page is right-biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased.

[0068] Exemplarily, first determine whether the equation three (3×N2) = (N1+N0+N3) holds; if it holds (equal), confirm that the voltage distribution offset state around the threshold voltage R3 is unbiased; if it is greater, confirm that the voltage distribution offset state around the threshold voltage R3 is left-biased, otherwise confirm that the voltage distribution offset state around the threshold voltage R3 is right-biased.

[0069] Exemplarily, as Figure 5 shown, when the flash memory page is configured as the MLC type, the data rereading method of the embodiment of the present application specifically includes: S210, determine whether read page needs to execute the rereading process. If so, execute step S220; if not, directly end.

[0070] S220, count the number of cells corresponding to the "11" state, "01" state, "00" state, and "10" state in the flash memory page, and obtain N0, N1, N2, and N3 in sequence.

[0071] That is to say, in step S10, count the number of cells corresponding to n data states in the flash memory page, and obtain n quantities, including: count the number of cells corresponding to the "11" state, "01" state, "00" state, and "10" state in the flash memory page, and obtain N0, N1, N2, and N3 in sequence.

[0072] Before executing step S220, first clarify the encoding method of the MLC. Different particles may have different encoding methods. Currently, most encoding methods are based on the voltage range, from left to right are "11" - "01" - "00" - "10". According to the read operation result, record the quantities as N0, N1, N2, and N3 respectively. Specifically, after the Read operationFail, enter the retry flow; different from the SLC, an MLC cell has 4 states, "00", "01", "10", "11"; count the quantities of the four cell states respectively and record them in an array with a length of 4.

[0073] S230, confirm that the flash memory page type is low page.

[0074] S231, Determine whether the equation (N0 + N1) = (N2 + N3) holds to confirm whether there is an offset. If they are equal, execute the last step; if not, execute step S232.

[0075] S232, Determine whether (N0 + N1) > (N2 + N3) holds. If not, execute step S233; if so, execute step S234.

[0076] S233, Confirm that the voltage distribution offset state around the threshold voltage R2 is a right offset.

[0077] S234, Confirm that the voltage distribution offset state around the threshold voltage R2 is a left offset.

[0078] S240, Confirm that the flash page type is up page.

[0079] S241, Determine whether the equation (3 × N0) = (N1 + N2 + N3) holds to confirm whether there is an offset. If they are equal, execute the last step; if not, execute step S242.

[0080] S242, Determine whether (3 × N0) > (N1 + N2 + N3) holds. If so, execute step S243; if not, execute step S244.

[0081] S243, Confirm that the voltage distribution offset state around the threshold voltage R1 is a right offset. Screen the offset voltage values greater than 0 from the reread table as the accurate offset voltage values. Rescreen the MLC's retrytable according to the offset situation, and initially screen out the appropriate Retry table according to the left or right offset situation.

[0082] S244, Confirm that the voltage distribution offset state around the threshold voltage R1 is a left offset. Screen the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0083] S245, Determine whether the equation (3 × N2) = (N1 + N0 + N3) holds. If so, execute the last step; if not, execute step S246.

[0084] S246, Determine whether the equation (3 × N2) > (N1 + N0 + N3) holds. If so, execute S247; if not, execute step S248.

[0085] S247, Confirm that the voltage distribution offset state around the threshold voltage R3 is a right offset. Screen the offset voltage values greater than 0 from the reread table as the accurate offset voltage values.

[0086] S248. Confirm that the voltage distribution offset state around the threshold voltage R3 is left-biased. Filter out the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0087] S250. Perform the read retry flow according to the filtered accurate offset voltage values.

[0088] In one implementation, when the flash memory page is configured in the TLC mode, the data states of the basic memory cells include: "000", "001", "010", "011", "100", "101", "110", and "111". TLC has 7 threshold voltages, namely R1, R2, R3, R4, R5, R6, and R7.

[0089] First, it is necessary to clarify the encoding method of TLC. Different NAND flash chips may have different encoding methods. Currently, most encoding methods are 76502314. From left to right according to the voltage range, they are: "111" - "110" - "100" - "000" - "010" - "011" - "001" - "101". The advantage of this encoding method is to balance the read and write times of different page types of the same cell and prevent the read and write times of different page types from differing too much.

[0090] Count the number of basic memory cells corresponding to n data states in the flash memory page to obtain n quantities, including: Count the number of basic memory cells corresponding to the "111" state, "110" state, "100" state, "000" state, "010" state, "011" state, "001" state, and "101" state in the flash memory page, and obtain N0, N1, N2, N3, N4, N5, N6, and N7 in sequence. Specifically, after the Read operation fails, enter the retry flow. A TLC cell has 8 data states. According to the result of the read operation, count the number of cells corresponding to the eight data states respectively and record them in an array with a length of 8.

[0091] Further, according to the size relationship between N0 and N n-1 to determine the voltage distribution offset state of the flash memory page, including: Obtain the flash memory page type.

[0092] One TLC wordline has 3 types of pages, namely the lower page (LSB), the upper page (MSB), and the extra page (CSB). Run different cases according to different page types.

[0093] Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0 and N7.

[0094] Furthermore, the flash memory page types include: lower page, upper page, and extra page.

[0095] Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0 and N7, including: S2321, if the flash memory page type is a lower page, for the threshold voltage R1, compare the magnitudes of 7×N0 and N1 + N2 + N3 + N4 + N5 + N6 + N7: If 7×N0 is greater than N1 + N2 + N3 + N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is left - biased; If 7×N0 is less than N1 + N2 + N3 + N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is right - biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R5, compare the magnitudes of 3×(N1 + N2 + N3 + N4) and 5×(N5 + N6 + N7): If 3×(N1 + N2 + N3 + N4) is greater than 5×(N5 + N6 + N7), the offset state of the voltage distribution of the flash memory page is left - biased; If 3×(N1 + N2 + N3 + N4) < 5×(N5 + N6 + N7), the voltage distribution offset state of the flash memory page is right - biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; S2322, if the flash memory page type is an upper page, for the threshold voltage R2, compare the magnitudes of 3×(N0 + N1) and N2 + N3 + N4 + N5 + N6 + N7: If 3×(N0 + N1) > N2 + N3 + N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is left - biased; If 3×(N0 + N1) < N2 + N3 + N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is right - biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R4, compare the magnitudes of N0 + N1 + N2 + N3 and N4 + N5 + N6 + N7: If N0 + N1 + N2 + N3 is greater than N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is left-biased; if N0 + N1 + N2 + N3 is less than N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R6, compare the magnitudes of N0 + N1 + N2 + N3 + N4 + N5 and 3 × (N6 + N7): If N0 + N1 + N2 + N3 + N4 + N5 is greater than 3 × (N6 + N7), the voltage distribution offset state of the flash memory page is left-biased; if N0 + N1 + N2 + N3 + N4 + N5 is less than 3 × (N6 + N7), the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; S2323. If the flash memory page type is an intermediate bit page, for the threshold voltage R3, compare the magnitudes of 5 × (N0 + N1 + N2) and 3 × (N3 + N4 + N5 + N6 + N7): If 5 × (N0 + N1 + N2) > 3 × (N3 + N4 + N5 + N6 + N7), the voltage distribution offset state of the flash memory page is left-biased; If 5 × (N0 + N1 + N2) < 3 × (N3 + N4 + N5 + N6 + N7), the voltage distribution offset state of the flash memory page is right-biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R7, compare the magnitudes of N1 + N2 + N3 + N4 + N5 + N6 and 7 × N7: If N1 + N2 + N3 + N4 + N5 + N6 is greater than 7 × N7, the voltage distribution offset state of the flash memory page is left-biased; if N1 + N2 + N3 + N4 + N5 + N6 is less than 7 × N7, the voltage distribution offset state of the flash memory page is right-biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased.

[0096] Furthermore, determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; including: If the voltage distribution offset state of the flash memory page is right-biased, screen out the offset voltage value greater than zero from the reread table; If the voltage distribution offset state of the flash memory page is left-biased, screen out the offset voltage value less than zero from the reread table.

[0097] When the NAND Flash memory page is configured in the TLC mode (TLC mode), the data states of the cells include: "000", "001", "010", "011", "100", "101", "110", and "111".

[0098] Step S20 determines the Vt distribution offset state according to the magnitude relationship between the quantity N0 and the quantity N, including: n-1 Between them, determine the Vt distribution offset state, including: Such as Figure 6-1 , Figure 6-2 , Figure 6-3 As shown, when the NAND flash is of the TLC type, the data rereading method of the embodiment of the present application specifically includes: S310, determine whether the read page needs to execute the rereading process. If so, execute step S320; if not, it is the last step.

[0099] S320, count the number of cells corresponding to each data state in the flash memory page, and sequentially obtain N0, N1, N2, N3, N4, N5, N6, and N7.

[0100] S331, the flash memory page type is the lower page. It is necessary to judge the offset situation on the left and right of the threshold voltage R1 and the threshold voltage R5. First, judge the offset state of the threshold voltage R1, and then judge the offset state of the threshold voltage R5.

[0101] S332, for the threshold voltage R1, judge whether the equation (N0×7) = (N1 + N2 + N3 + N4 + N5 + N6 + N7) holds. If so, confirm that the voltage distribution offset state on the left and right of the threshold voltage R1 is unbiased, and then execute step S336 to judge the threshold voltage R5; if not, execute step S333.

[0102] According to the coding method page type, if the flash memory page type is the lower page, for the threshold voltage R1, judge whether equation three holds. Equation three is: (N0×7) = (N1 + N2 + N3 + N4 + N5 + N6 + N7).

[0103] S333, judge whether (N0×7) > (N1 + N2 + N3 + N4 + N5 + N6 + N7) holds. If it is greater, execute step S334; if it is less, execute step S335.

[0104] S334, confirm that the voltage distribution offset state on the left and right of the threshold voltage R1 is left-biased. Screen the offset voltage values less than 0 from the rereading table as the accurate offset voltage values.

[0105] S335, confirm that the voltage distribution offset state on the left and right of the threshold voltage R1 is right-biased. Screen the offset voltages greater than 0 from the rereading table as the accurate offset voltage values.

[0106] S336. For the threshold voltage R5, determine whether the equation (N0 + N1 + N2 + N3 + N4) × 3 = (N5 + N6 + N7) × 5 holds.

[0107] If it holds, perform the last step; otherwise, execute step S337.

[0108] For the threshold voltage R5, determine whether Equation Four holds. Equation Four is: (N0 + N1 + N2 + N3 + N4) × 3 = (N5 + N6 + N7) × 5; if they are equal, confirm that the voltage distribution offset state around the threshold voltage R5 is unbiased.

[0109] S337. Determine whether the equation (N0 + N1 + N2 + N3 + N4) × 3 > (N5 + N6 + N7) × 5 holds. If it is greater, execute step S338; if it is less, execute step S339.

[0110] S338. Confirm that the voltage distribution offset state around the threshold voltage R5 is left-biased. Screen the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0111] S339. Confirm that the voltage distribution offset state around the threshold voltage R5 is right-biased. Screen the offset voltage values greater than 0 from the reread table as the accurate offset voltage values.

[0112] S340. The flash page type is the upper page. It is necessary to judge the offset situations around the threshold voltages R2, R4, and R6. First, judge the offset situation of the threshold voltage R2, then judge the offset situation of the threshold voltage R4, and finally judge the situation of R6.

[0113] S341. For the threshold voltage R2, determine whether the equation (N0 + N1) × 3 = (N2 + N3 + N4 + N5 + N6 + N7) holds. If it holds, if they are equal, the voltage distribution offset state around the threshold voltage R2 is unbiased, and execute step S345 to judge the offset situation of R4; otherwise, execute step S342.

[0114] Determine whether Equation Five holds. Equation Five is: (N0 + N1) × 3 = (N2 + N3 + N4 + N5 + N6 + N7).

[0115] S342. Determine whether the equation (N0 + N1) × 3 > (N2 + N3 + N4 + N5 + N6 + N7) holds. If it is greater, execute step S343; if it is less, execute step S344.

[0116] S343. Confirm that the voltage distribution offset state around the threshold voltage R2 is left-biased. Screen the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0117] S344. Confirm that the voltage distribution offset state around the threshold voltage R2 is right-biased. Screen the offset voltage values greater than 0 from the reread table as the accurate offset voltage values.

[0118] S345. For the threshold voltage R4, determine whether the equation (N0 + N1 + N2 + N3) = (N4 + N5 + N6 + N7) holds. If it is equal, the voltage distribution offset state around the threshold voltage R4 is unbiased, and proceed to step S349 to judge the offset situation regarding R6; if it is not equal, proceed to step S346.

[0119] Determine whether Equation 6 holds. Equation 6 is: (N0 + N1 + N2 + N3) = (N4 + N5 + N6 + N7); S346. Determine whether (N0 + N1 + N2 + N3) > (N4 + N5 + N6 + N7) holds. If it is greater, proceed to step S347; if it is less, proceed to step S348.

[0120] S347. Confirm that the voltage distribution offset state around the threshold voltage R4 is left-biased. Screen the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0121] S348. Confirm that the voltage distribution offset state around the threshold voltage R4 is right-biased. Screen the offset voltage values greater than 0 from the reread table as the accurate offset voltage values.

[0122] S349. For the threshold voltage R6, determine whether the equation (N0 + N1 + N2 + N3 + N4 + N5) = (N6 + N7) × 3 holds. If it is equal, the voltage distribution offset state around the threshold voltage R6 is without offset, and proceed to the last step; if it is not equal, proceed to step S350.

[0123] Determine whether Equation 7 holds. Equation 7 is: (N0 + N1 + N2 + N3 + N4 + N5) = (N6 + N7) × 3; S350. Determine whether the equation (N0 + N1 + N2 + N3 + N4 + N5) > (N6 + N7) × 3 holds. If it is greater, proceed to step S351; if it is less, proceed to step S352.

[0124] S351. Confirm that the voltage distribution offset state around the threshold voltage R6 is left-biased. Screen out the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0125] S352. Confirm that the voltage distribution offset state around the threshold voltage R6 is right-biased. Screen out the offset voltage values greater than 0 from the reread table as the accurate offset voltage values.

[0126] S360. The flash page type is Extra page. It is necessary to judge the offset situations around the threshold voltage R3 and the threshold voltage R7. First, judge the offset situation of the threshold voltage R1, and then judge the offset situation of the threshold voltage R5.

[0127] S371. For the threshold voltage R3, judge whether the equation (N0 + N1 + N2) × 5 = (N3 + N4 + N5 + N6 + N7) × 3 holds. If it holds, that is, if they are equal, then the voltage distribution offset state around the threshold voltage R3 is unbiased, and then execute step 380 to judge the offset situation around R7; if not, then execute step S372.

[0128] Judge whether equation eight holds. Equation eight is: (N0 + N1 + N2) × 5 = (N3 + N4 + N5 + N6 + N7) × 3.

[0129] S372. Judge whether the equation (N0 + N1 + N2) × 5 > (N3 + N4 + N5 + N6 + N7) × 3 holds. If it is greater, then execute step S373; if it is less, then execute step S374.

[0130] S373. Confirm that the voltage distribution offset state around the threshold voltage R3 is left-biased. Screen out the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0131] S374. Confirm that the voltage distribution offset state around the threshold voltage R3 is right-biased. Screen out the offset voltage values greater than 0 from the reread table as the accurate offset voltage values.

[0132] S380. For the threshold voltage R7, judge whether the equation (N0 + N1 + N2 + N3 + N4 + N5 + N6) = N7 × 7 holds. If it holds, that is, if they are equal, then the voltage distribution offset state around the threshold voltage R3 is non-offset, and then execute the last step; if not, then execute step S381.

[0133] Judge whether equation nine holds. Equation nine is: (N0 + N1 + N2 + N3 + N4 + N5 + N6) = N7 × 7.

[0134] S381, determine whether the equation (N0 + N1 + N2 + N3 + N4 + N5 + N6) > N7 × 7 holds. If it is greater, execute step S382; if it is less, execute step S383.

[0135] S382, confirm that the voltage distribution offset state around the threshold voltage R7 is left-biased. Screen the offset voltage values less than 0 from the reread table as the accurate offset voltage values.

[0136] S383, confirm that the voltage distribution offset state around the threshold voltage R7 is right-biased. Screen the offset voltage values greater than 0 from the reread table as the accurate offset voltage values.

[0137] S390, perform the retry flow according to the screened accurate offset voltage values.

[0138] After confirming the offset situation, rescreen the retry table of TCL according to the offset situation, and initially screen out the appropriate retry table according to the left or right bias situation to perform the retry flow.

[0139] In this application, by analyzing the state distribution of the basic storage unit (cell), it is determined whether the threshold voltage (Vt) is left-biased or right-biased, so as to screen out the retry table applicable to the current scenario.

[0140] Figure 7 FIG. shows a schematic structural diagram of a reread process execution device according to an embodiment of the present application. Exemplarily, the reread process execution device includes: a statistics module 710, an offset state determination module 720, an offset voltage value determination module 730, and a reread module 740.

[0141] The statistics module 710 is used to count the number of basic storage units corresponding to n data states in the flash memory page, obtaining n quantities, denoted as N0, N1,..., N n-1 , n ≥ 2; The offset state determination module 720 is used to determine the voltage distribution offset state of the flash memory page according to the size relationship between N0 and N n-1 ; The offset voltage value determination module 730 is used to determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; The reread module 740 is used to execute the reread process to correct the data according to the offset voltage value or end the reread process after reaching the preset reread times.

[0142] It can be understood that the device in this embodiment corresponds to the data rereading method in the above embodiment, and the optional items in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0143] The present application also provides a memory. Exemplarily, the memory is used to store a computer program for implementing the data rereading method of the present application, and the data rereading method of the present application is used to correct the data when a read data error occurs. The storage device consists of a main control chip + nand flash. The data rereading method of the present application is stored in a fixed position of the nand flash and will be loaded into the main control chip for execution when powered on. The main control chip schedules the execution of the program to implement the functions of the data rereading method of the present application.

[0144] It can be understood that the device in this embodiment corresponds to the data rereading method in the above embodiment, and the optional items in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0145] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory. Among them, the memory stores a computer program, and the processor runs the computer program, so that the terminal device executes the above data rereading method or the functions of each module in the above rereading process execution device.

[0146] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application.

[0147] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electric Erasable Programmable Read-Only Memory (EEPROM), etc. Among them, the memory is used to store computer programs, and after receiving the execution instruction, the processor can execute the computer program accordingly.

[0148] This application also provides a readable storage medium for storing the computer program used in the above terminal device.

[0149] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and structure diagrams in the drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the blocks can occur in a different order than marked in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the structure diagram and / or flowchart, as well as the combination of blocks in the structure diagram and / or flowchart, can be implemented by a dedicated hardware-based system that executes the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0150] In addition, each functional module or unit in various embodiments of this application can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.

[0151] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0152] As described above, the above are only specific implementation manners of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, and all of them should be covered within the protection scope of this application.

Claims

1. A data rereading method, characterized in that, Including: Statistically count the number of basic storage units corresponding to n data states in a flash memory page to obtain n quantities, denoted as N0, N1, …, N n-1 , where n ≥ 2; According to the magnitude relationship between N0 and N n-1 determine the voltage distribution offset state of the flash memory page; Determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; Execute the reread process to recover data according to the offset voltage value or end the reread process after reaching the preset reread times.

2. The data rereading method according to claim 1, wherein When the flash memory page is configured in the SLC mode, the data states of the basic storage units include: "0” and "1”; The method of statistically counting the number of basic storage units corresponding to n data states in the flash memory page to obtain n quantities includes: Statistically count the number of basic storage units corresponding to the "0” state and the "1” state in the flash memory page, and correspondingly obtain N0 and N1.

3. The data rereading method according to claim 2, wherein Determining the voltage distribution offset state of the flash memory page according to the magnitude relationship between N0 and N n-1 includes: Compare the magnitudes of N0 and N1; If N0 is equal to N1, the voltage distribution offset state of the flash memory page is unbiased; And / or, if N0 is greater than N1, the voltage distribution offset state of the flash memory page is right-biased; And / or, if N0 is less than N1, confirm that the voltage distribution offset state of the flash memory page is left-biased.

4. The data rereading method according to claim 1, wherein When the flash memory page is configured in the MLC mode, the data states of the basic storage units include: "00”, "01”, "10” and "11”; The method of statistically counting the number of basic storage units corresponding to n data states in the flash memory page includes: Statistically count the number of basic storage units corresponding to the "11” state, "01” state, "00” state and "10” state in the flash memory page, and correspondingly obtain N0, N1, N2 and N3 in sequence.

5. The data rereading method according to claim 4, characterized in that, Determining the voltage distribution offset state of the flash memory page according to the magnitude relationship between N0 and N n-1 includes: Obtain the flash memory page type; Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship among N0, N1, N2 and N3.

6. The data rereading method according to claim 5, characterized in that The flash memory page type includes: low-order page and high-order page; The method of determining the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship among N0, N1, N2 and N3 includes: If the flash memory page type is a low-order page, For the threshold voltage R2, compare the magnitudes of N0 + N1 and N2 + N3: If N0 + N1 > N2 + N3, the voltage distribution offset state of the flash memory page is left-biased; If N0 + N1 < N2 + N3, the voltage distribution offset state of the flash memory page is right-biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; If the flash memory page type is a high-order page, for the threshold voltage R1, compare the magnitudes of 3×N0 and N1 + N2 + N3: If 3×N0 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-biased; If 3×N0 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right-biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R3, compare the magnitudes of 3×N2 and N1 + N2 + N3: If 3×N2 is greater than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is left-biased; If 3×N2 is less than N1 + N2 + N3, the voltage distribution offset state of the flash memory page is right-biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased.

7. The data rereading method according to claim 1, characterized in that When the flash memory page is configured in the TLC mode, the data states of the basic memory cells include: "000", "001", "010", "011", "100", "101", "110", and "111". Statistically count the number of basic memory cells corresponding to n data states in the flash memory page, obtaining n quantities, including: Statistically count the number of basic memory cells corresponding to the "111" state, "110" state, "100" state, "000" state, "010" state, "011" state, "001" state, and "101" state in the flash memory page, and correspondingly obtain N0, N1, N2, N3, N4, N5, N6, and N7 in sequence.

8. The data rereading method according to claim 7, characterized in that Determine the voltage distribution offset state of the flash memory page according to the magnitude relationship between N0 and N n-1 including: Obtain the flash memory page type; Determine the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0 and N7.

9. The data rereading method according to claim 8, wherein The flash memory page types include: low-order page, high-order page, and super page; The determining the voltage distribution offset state of the flash memory page according to the flash memory page type and the relationship between N0 and N7 includes: If the flash memory page type is a low-order page, for the threshold voltage R1, compare the magnitudes of 7×N0 and N1+N2+N3+N4+N5+N6+N7: If 7×N0 is greater than N1+N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is left-biased; If 7×N0 is less than N1+N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is right-biased; If they are equal, then the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R5, compare the magnitudes of 3×(N1+N2+N3+N4) and 5×(N5+N6+N7): If 3×(N1+N2+N3+N4) is greater than 5×(N5+N6+N7), then the offset state of the voltage distribution of the flash memory page is left-biased; If 3×(N1+N2+N3+N4) is less than 5×(N5+N6+N7), then the voltage distribution offset state of the flash memory page is right-biased; if they are equal, then the voltage distribution offset state of the flash memory page is unbiased; If the flash memory page type is a high-order page, for the threshold voltage R2, compare the magnitudes of 3×(N0+N1) and N2+N3+N4+N5+N6+N7: If 3×(N0+N1) is greater than N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is left-biased; If 3×(N0+N1) is less than N2+N3+N4+N5+N6+N7, then the voltage distribution offset state of the flash memory page is right-biased; if they are equal, then the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R4, compare the magnitudes of N0+N1+N2+N3 and N4+N5+N6+N7: If N0 + N1 + N2 + N3 is greater than N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is left - biased; if N0 + N1 + N2 + N3 is less than N4 + N5 + N6 + N7, the voltage distribution offset state of the flash memory page is right - biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R6, compare the magnitudes of N0 + N1 + N2 + N3 + N4 + N5 and 3×(N6 + N7): If N0 + N1 + N2 + N3 + N4 + N5 is greater than 3×(N6 + N7), the voltage distribution offset state of the flash memory page is left - biased; if N0 + N1 + N2 + N3 + N4 + N5 is less than 3×(N6 + N7), the voltage distribution offset state of the flash memory page is right - biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased; If the flash memory page type is an intermediate - bit page, for the threshold voltage R3, compare the magnitudes of 5×(N0 + N1 + N2) and 3×(N3 + N4 + N5 + N6 + N7): If 5×(N0 + N1 + N2) is greater than 3×(N3 + N4 + N5 + N6 + N7), the voltage distribution offset state of the flash memory page is left - biased; If 5×(N0 + N1 + N2) is less than 3×(N3 + N4 + N5 + N6 + N7), the voltage distribution offset state of the flash memory page is right - biased; If they are equal, the voltage distribution offset state of the flash memory page is unbiased; For the threshold voltage R7, compare the magnitudes of N1 + N2 + N3 + N4 + N5 + N6 and 7×N7: If N1 + N2 + N3 + N4 + N5 + N6 is greater than 7×N7, the voltage distribution offset state of the flash memory page is left - biased; if N1 + N2 + N3 + N4 + N5 + N6 is less than 7×N7, the voltage distribution offset state of the flash memory page is right - biased; if they are equal, the voltage distribution offset state of the flash memory page is unbiased.

10. The data rereading method according to any one of claims 1-9, characterized in that, Determine the offset direction of the reread voltage according to the voltage distribution offset state of the flash memory page, and screen out the corresponding offset voltage value from the reread table according to the offset direction; including: If the voltage distribution offset state of the flash memory page is right - biased, screen out the offset voltage value greater than zero from the reread table; And / or, if the voltage distribution offset state of the flash memory page is left - biased, screen out the offset voltage value less than zero from the reread table.

11. A memory, characterized in that, The memory is used to store a computer program for implementing the data reread method described in any one of claims 1 - 10, and uses the data reread method described in any one of claims 1 - 10 to recover data when a read data error occurs.

12. A readable storage medium, characterized in that, It stores a computer program, and when the computer program is executed on a processor, it implements the data reread method described in any one of claims 1 - 10.

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