Semiconductor structure fabrication methods and semiconductor structures

Abstract

This disclosure relates to a semiconductor structure fabrication method and semiconductor structure, belonging to the field of integrated circuit technology, including: providing a substrate; forming a first via sequentially penetrating a supporting stack along a first direction based on a target photomask; forming a target stack on the inner sidewall of the first via, the target stack defining a second via, the target stack including a target carbon layer and an isolation layer alternately stacked from the outside to the inside; forming a dielectric stack filling the second via; forming a third via penetrating the dielectric stack and exposing the target stack based on the target photomask; etching through the third via and removing the remaining dielectric stack in the second via, then etching the first dielectric layer to obtain a groove exposing a portion of the conductive layer; removing the target carbon layer to form a metal barrier layer covering the inner sidewall of the third via and the inner surface of the groove, with air gaps between adjacent remaining isolation layers. This method can at least reduce the number of photomasks used, and reduce the complexity and cost of the fabrication process.

Description

[0001] This application is a divisional application of the invention patent application filed on December 18, 2024, with application number 202411868367.5 and invention title "Semiconductor Structure Preparation Method and Semiconductor Structure". Technical Field

[0002] This disclosure relates to the field of integrated circuit manufacturing technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0003] With the rapid development of semiconductor technology, the market has increasingly higher requirements for the integration, performance and reliability of integrated circuits, resulting in a continuous increase in the number of stacked film layers and the complexity of the structure inside the chip.

[0004] Inside a chip, metal wires are typically used to establish communication connections between transistors, capacitors, resistors, and other components. As the number of stacked film layers and the complexity of the structure inside a chip continue to increase, the process requirements for fabricating high aspect ratio metal interconnect structures are becoming increasingly stringent.

[0005] However, traditional fabrication processes for high aspect ratio metal interconnect structures require redefining additional photomasks for etching the interconnect structures and place high demands on the etching performance of the etching equipment, resulting in high complexity and cost of the fabrication process. Summary of the Invention

[0006] Therefore, it is necessary to provide a semiconductor structure fabrication method and semiconductor structure to address the problems mentioned in the background art. This method can at least improve the performance and reliability of fabricating high aspect ratio metal interconnect structures while reducing the number of photomasks used and lowering the complexity and cost of the fabrication process.

[0007] According to various embodiments of this disclosure, a first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0008] A substrate is provided, on which a conductive layer, a first dielectric layer and a second dielectric layer are sequentially stacked along a first direction perpendicular to the top surface of the substrate;

[0009] Based on the target photomask, a first via is formed that penetrates the second dielectric layer along the first direction;

[0010] A target stack is formed on the inner sidewall of the first via, the target stack defining a second via that exposes a portion of the first dielectric layer, the target stack including target carbon layers and isolation layers alternately stacked from the outside to the inside;

[0011] Form a dielectric stack covering the second dielectric layer and the target stack;

[0012] Based on the target photomask, a third via is formed that penetrates the dielectric stack along the first direction and exposes the target stack and the second via.

[0013] After simultaneously etching and removing part of the first dielectric layer through the third via and the second via, a groove is obtained that exposes part of the conductive layer.

[0014] Remove the target carbon layer to obtain the remaining isolation layer with spaced spacing and its top surface flush with the top surface of the second dielectric layer;

[0015] A metal barrier layer is formed covering the inner wall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove, wherein an air gap is included between adjacent remaining isolation layers.

[0016] The semiconductor structure fabrication method in the above embodiments involves sequentially stacking a conductive layer, a first dielectric layer, and a second dielectric layer on a substrate along a first direction perpendicular to the top surface of the substrate. After forming a first via penetrating the second dielectric layer along the first direction based on a target photomask, a target stack is formed on the inner sidewall of the first via. The target stack defines a second via, which exposes a portion of the first dielectric layer. The target stack includes a target carbon layer and an isolation layer stacked alternately from the outside to the inside. The second via exposes the first dielectric layer. Then, a dielectric stack covering the second dielectric layer and the target stack is formed. This allows for setting the aspect ratio of the subsequent interconnect structure fabrication by adjusting the number and thickness of the dielectric stack. A third via penetrating the dielectric stack along the first direction and exposing the target stack and the second via can then be formed again based on the aforementioned target photomask. The shape, position, and size of the third via correspond to the shape, position, and size of the first via. Therefore, without increasing the cost of additional photomask research and design, the fabrication process of interconnect structures for various application scenarios can be satisfied. The requirements are as follows: Further, after simultaneously etching and removing part of the first dielectric layer via the third via and the second via, a groove exposing part of the conductive layer is obtained. Then, the target carbon layer is removed, resulting in an isolation layer spaced apart and with its top surface flush with the top surface of the second dielectric layer. This forms a metal barrier layer covering the inner wall of the third via, the top surface of the isolation layer, and the inner surface of the groove, creating an air gap between adjacent remaining isolation layers. This air gap isolates the bottom of the metal interconnect structure subsequently formed in the third via from the surrounding dielectric sidewalls, effectively improving the isolation effect. Since the opening size of the second via is smaller than that of the third via, a T-shaped metal interconnect structure is formed, preventing voids or gaps from appearing at the bottom due to the decreased kinetic energy of deposited metal ions during the metal interconnect structure deposition process, thus improving the performance of the metal interconnect structure fabrication. The metal barrier layer prevents metal ions from entering the dielectric sidewalls during the subsequent metal interconnect structure deposition process, effectively preventing the generation of current leakage channels and further improving the performance and reliability of the fabricated metal interconnect structure.

[0017] In some embodiments, the dielectric stack includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially along a first direction; wherein the first dielectric layer covers the second dielectric layer and the target stack; and the second via includes a bubble extending into the first dielectric layer along the first direction, the bubble communicating with the second via.

[0018] In some embodiments, the innermost isolation layer of the target stack, which is far from the second dielectric layer, defines a second via. The outermost target carbon layer of the target stack is adjacent to the second dielectric layer, which facilitates the isolation layer to be adjacent to the second dielectric layer via an air gap after the target carbon layer is removed, and avoids the formation of steps on the first dielectric layer in the subsequently fabricated metal interconnect structure, thereby reducing the impedance of the fabricated metal interconnect structure.

[0019] In some embodiments, a first dielectric layer is formed by chemical vapor deposition covering the top surface of the second dielectric layer and the top surface of the target stack.

[0020] In some embodiments, forming the third via includes: obtaining a patterned photoresist layer on the top surface of the dielectric stack based on a target photomask; and etching the dielectric stack based on the patterned photoresist layer, using an isolation layer as an etch stop layer, to obtain the third via. The shape, position, and size of the third via correspond to the shape, position, and size of the first via. Therefore, without increasing the additional photomask R&D and design costs, by reusing the target photomask, the complexity and cost of the fabrication process can be reduced while improving the performance and reliability of fabricating high aspect ratio metal interconnect structures.

[0021] In some embodiments, removing the target carbon layer includes treating and removing the target carbon layer with a target gas containing ozone. The target carbon layer is removed after being oxidized to carbon dioxide and water using the ozone-containing target gas, thereby obtaining an insulating layer spaced apart by an air gap.

[0022] In some embodiments, the target carbon layer comprises α-carbon and / or fluorinated amorphous carbon.

[0023] In some embodiments, the isolation layer includes silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination thereof.

[0024] In some embodiments, the first dielectric layer comprises silicon, nitrogen, and carbon.

[0025] In some embodiments, a second aspect of this disclosure provides a semiconductor structure including a substrate, a dielectric stack, and a metal barrier layer. The substrate includes a conductive layer, a first dielectric layer, and a second dielectric layer sequentially stacked along a first direction perpendicular to the top surface of the substrate. The second dielectric layer includes a first via extending to the first dielectric layer along the first direction. The first via includes isolation layers arranged at intervals along a second direction parallel to the top surface of the substrate, wherein the innermost isolation layer away from the second dielectric layer defines a groove exposing a portion of the conductive layer. The dielectric stack covers the second dielectric layer and the isolation layers, and includes a third via exposing the isolation layers and the second via. The metal barrier layer at least covers a portion of the sidewalls of the third via, the top surface of the isolation layer, and the inner surface of the groove.

[0026] In some embodiments, the innermost insulating layer, away from the second dielectric layer, defines a second via that exposes the groove; a metal barrier layer also covers the inner sidewall of the second via.

[0027] In some embodiments, the dielectric stack includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially along a first direction; wherein the first dielectric layer covers the second dielectric layer and the isolation layer; and the second via includes a bubble extending into the first dielectric layer along the first direction, the bubble communicating with the second via.

[0028] The unexpected technical effects that can be produced by the embodiments of this disclosure include:

[0029] The bottom of the metal interconnect structure is isolated from the surrounding dielectric sidewalls by an air gap, which effectively improves the isolation effect. The T-shaped metal interconnect structure can avoid the formation of voids or gaps at the bottom due to the decrease in the kinetic energy of deposited metal ions during the metal deposition process, thus improving the performance of the metal interconnect structure. The metal barrier layer can prevent metal ions from entering the dielectric sidewalls during the subsequent metal deposition process, effectively preventing the generation of current leakage channels and further improving the performance and reliability of the metal interconnect structure. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 The diagram shows a flowchart of a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0032] Figure 2The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first through-hole in step S20 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0033] Figure 3 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming the target stack in step S30 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0034] Figure 4 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a dielectric stack in step S40 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0035] Figure 5 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a third through-hole in step S50 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0036] Figure 6 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after removing the remaining dielectric stack in the second via in step S60 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0037] Figure 7 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a groove in step S60 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0038] Figure 8 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after removing the target carbon layer in step S70 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0039] Figure 9 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a metal barrier layer in step S80 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0040] Figure 10 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first via and a second via in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0041] Figure 11 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first dielectric layer in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0042] Figure 12The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a patterned photoresist layer in a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0043] Figure 13 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a second via in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0044] Figure 14 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after etching the first dielectric layer through a second via in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0045] Figure 15 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after removing the target carbon layer in a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0046] Figure 16 The diagram shown is a schematic longitudinal section of the semiconductor structure obtained after forming a metal barrier layer in a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0047] Explanation of reference numerals in the attached figures:

[0048] 100. Substrate; 1. Conductive layer; 2. First dielectric layer; 3. Second dielectric layer; 4. Third dielectric layer; PR. Patterned photoresist layer; H1. First via; 20. Target stack; 21. Target carbon layer; 22. Isolation layer; 50. Dielectric stack; 51. First dielectric layer; 52. Second dielectric layer; 53. Third dielectric layer; H2. Second via; H3. Third via; H4. Groove; 7. Air gap; V1. First via; V2. Second via; V2a. Bubble; 9. Metal barrier layer. Detailed Implementation

[0049] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0056] In the embodiments of this disclosure, "stacked" or "layered structure" can refer to one or more layers.

[0057] Please see Figure 1 In some embodiments, a method for fabricating a semiconductor structure is provided, comprising: steps S10-S80, wherein:

[0058] Step S10: Provide a substrate, on which a conductive layer, a first dielectric layer and a support stack are sequentially stacked along a first direction perpendicular to the top surface of the substrate;

[0059] Step S20: Based on the target photomask, form a first through hole that sequentially penetrates the support stack along the first direction;

[0060] Step S30: A target stack is formed on the inner wall of the first via, the target stack defines a second via, the second via exposes part of the first dielectric layer, the target stack includes target carbon layers and isolation layers stacked alternately from the outside to the inside;

[0061] Step S40: Form a dielectric stack that covers the support stack, the target stack, and fills the second via;

[0062] Step S50: Based on the target photomask, form a third via that penetrates the dielectric stack along the first direction and exposes the target stack;

[0063] Step S60: After simultaneously etching the third via and removing the remaining dielectric stack and the isolation layer of the preset thickness in the second via, the first dielectric layer is etched to obtain a groove that exposes part of the conductive layer.

[0064] Step S70: Remove the target carbon layer to obtain the remaining isolation layers arranged at intervals;

[0065] Step S80: Form a metal barrier layer covering the inner wall of the third through hole, the top surface of the remaining isolation layer, and the inner surface of the groove, wherein an air gap is included between adjacent remaining isolation layers.

[0066] Please continue reading. Figure 1 By depositing a conductive layer, a first dielectric layer, and a support layer sequentially stacked along a first direction perpendicular to the top surface of the substrate on a substrate, and forming a first via through the support layer sequentially along the first direction based on a target photomask, a target stack defining a second via is formed on the inner wall of the first via. The target stack includes a target carbon layer and an isolation layer alternately stacked from the outside to the inside, and the second via exposes the first dielectric layer. Then, a dielectric stack covering the support layer and the target stack and filling the second via is formed, which facilitates setting the aspect ratio of the subsequent interconnect structure by setting the number and thickness of the dielectric stack. Then, a third via through the dielectric stack and exposing the target stack can be formed again based on the aforementioned target photomask. The shape, position, and size of the third via correspond to the shape, position, and size of the first via. Therefore, without increasing the additional photomask R&D and design costs, the fabrication process requirements of interconnect structures in various application scenarios can be met. Furthermore, the third via is simultaneously etched and removed. After the remaining dielectric stack and the pre-defined isolation layer in the second via are formed, the first dielectric layer is etched to obtain a groove exposing a portion of the conductive layer. Then, the target carbon layer is removed to obtain the remaining isolation layers arranged at intervals. This forms a metal barrier layer covering the inner wall of the third via, the top surface of the remaining isolation layer, and the inner surface of the groove, resulting in air gaps between adjacent remaining isolation layers. This allows the bottom of the metal interconnect structure subsequently formed in the third via to be isolated from the surrounding dielectric sidewalls via the air gaps, effectively improving the isolation effect. Since the opening size of the second via is smaller than that of the third via, a T-shaped metal interconnect structure is formed, avoiding voids or gaps at the bottom due to the decrease in the kinetic energy of deposited metal ions during the metal deposition process, thus improving the performance of the metal interconnect structure. The metal barrier layer can prevent metal ions from entering the dielectric sidewalls during the subsequent metal deposition process, effectively preventing the generation of current leakage channels, further improving the performance and reliability of the metal interconnect structure.

[0067] Please see Figure 2In some embodiments, the material of the substrate 100 provided in step S10 may include, but is not limited to, semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 100 is a semiconductor structure that provides mechanical support and electrical properties for fabricating a semiconductor structure. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a III / V semiconductor substrate or a II / VI semiconductor substrate. Those skilled in the art can select the type of substrate 100 according to the type of transistors formed on the substrate 100; therefore, the type of substrate 100 should not limit the scope of protection of this disclosure.

[0068] As an example, please continue reading Figure 2 On substrate 100, along a direction away from substrate 100, such as the OY direction, a conductive layer 1, a first dielectric layer 2, a second dielectric layer 3, and a third dielectric layer 4 are sequentially stacked. The second dielectric layer 3 and the third dielectric layer 4 together form a support stack (not shown). Chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes can be used to sequentially form the conductive layer 1, the first dielectric layer 2, the second dielectric layer 3, and the third dielectric layer 4. CVD processes can include, but are not limited to, atmospheric-pressure CVD (APCVD), low-pressure CVD (LPCVD), or plasma-enhanced CVD. One or more of CVD, PECVD, etc. For example, low-pressure chemical vapor deposition has good step coverage. Using low-pressure chemical vapor deposition can improve the deposition rate and output, and reduce the process cost. In addition, low-pressure chemical vapor deposition does not require carrier gas, which can reduce particulate contamination.

[0069] As an example, please continue reading Figure 2In step S20, a photoresist material layer (not shown) can be coated on the top surface of the third dielectric layer 4. Then, the photoresist material layer is patterned based on the target photomask to obtain a patterned photoresist layer PR, which includes an opening pattern defining parameters such as the shape, size, and position of the first via. Then, the third dielectric layer 4 and the second dielectric layer 3 are etched based on the patterned photoresist layer PR to obtain a first via H1 that sequentially penetrates the third dielectric layer 4 and the second dielectric layer 3 along a first direction, such as the OY direction. The first via H1 exposes a portion of the first dielectric layer 2. The material of the first dielectric layer 2 may include, but is not limited to, a nitride-doped silicon carbide (NDC) film, which contains silicon, nitrogen, and carbon. The material of the second dielectric layer 3 may include, but is not limited to, silicon oxide, tetraethyl orthosilicate (TEOS), or combinations thereof. The material of the third dielectric layer 4 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof. The material of conductive layer 1 may include, but is not limited to, titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper, or combinations thereof.

[0070] For example, please refer to Figures 2-3 The thickness of the first dielectric layer 2 can be 400 angstroms to 1200 angstroms, for example, the thickness of the first dielectric layer 2 can be 400 angstroms, 600 angstroms, 800 angstroms, 1000 angstroms, or 1200 angstroms, etc. The thickness of the second dielectric layer 3 can be 5000 angstroms to 7000 angstroms, for example, the thickness of the second dielectric layer 3 can be 5000 angstroms, 6000 angstroms, or 7000 angstroms, etc. The thickness of the third dielectric layer 4 can be 1500 angstroms to 2500 angstroms, for example, the thickness of the third dielectric layer 4 can be 1500 angstroms, 2000 angstroms, or 2500 angstroms, etc.

[0071] For example, please refer to Figures 2-3 In step S30, after removing the patterned photoresist layer PR, a target stack 20 is formed on the inner sidewall of the first via H1. The target stack 20 defines a second via H2, which exposes part of the first dielectric layer 2. The target stack 20 includes a target carbon layer 21 and an isolation layer 22 that are alternately stacked from the outside to the inside.

[0072] For example, please refer to Figure 3 The opening size of the first through-hole H1 can be 1.6μm-1.8μm, for example, the opening size of the first through-hole H1 can be 1.6μm, 1.7μm, or 1.8μm, etc. The opening size of the second through-hole H2 can be 300nm-500nm, for example, the opening size of the second through-hole H2 can be 300nm, 400nm, or 500nm, etc. The opening size can refer to the length along the OX direction.

[0073] For example, please refer to Figure 3The thickness of the target carbon layer 21 is less than half the thickness of the isolation layer 22. In this embodiment, the thickness refers to the length along the OX direction. The thickness of the target carbon layer 21 can be 10nm-20nm, for example, 10nm, 13nm, 15nm, 18nm, or 20nm, etc. The thickness of the isolation layer 22 can be determined based on the opening size of the second via H2 and the thickness and number of target carbon layers 21. For example, if the opening size of the first via H1 is 1.7μm, the opening size of the second via H2 is 324nm, the thickness of the target carbon layer 21 is 10nm, and the number of stacked layers of the target carbon layer 21 is 2, then the thickness of the isolation layer 22 can be 3500nm-4500nm, for example, 3500nm, 3800nm, 4000nm, 4200nm, 4300nm, or 4500nm, etc.

[0074] For example, please refer to Figures 2-3 In step S30, target carbon layers 21 and isolation layers 22 can be deposited alternately to form alternating stacked target carbon layers 21 and 22. These alternating stacked target carbon layers 21 and 22 together constitute the target stack 20. The innermost isolation layer 22 of the target stack 20, furthest from the supporting stack, defines the second via H2. The outermost target carbon layer 21 of the target stack 20 is adjacent to the second dielectric layer 3. This facilitates the removal of the target carbon layer 21, allowing the remaining isolation layer 22 to be adjacent to the second dielectric layer 3 via an air gap 7, and preventing the formation of steps on the first dielectric layer 2 for the subsequently fabricated metal interconnect structure, thus reducing the impedance of the fabricated metal interconnect structure. Then, the target carbon layers 21 and 22 located on the top surface of the third dielectric layer 4 are removed, as are the target carbon layers 21 and 22 exposed by the second via H2, until the second via H2 exposes part of the top surface of the first dielectric layer 2. The patterned photoresist layer PR can protect and prevent damage to the third dielectric layer 4 during the etching of the target carbon layers 21 and 22. Furthermore, the patterned photoresist layer PR can be removed simultaneously during the removal of the target carbon layer 21 and the isolation layer 22 on the top surface of the third dielectric layer 4, avoiding the separate step of removing the patterned photoresist layer PR on the top surface of the third dielectric layer 4. Therefore, the complexity and cost of the fabrication process are reduced.

[0075] For example, please refer to Figures 2-3 The material of the target carbon layer 21 may include, but is not limited to, α-carbon, fluorinated amorphous carbon, or combinations thereof. The insulating layer 22 includes silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof.

[0076] For example, please refer to Figures 3-4In step S40, a deposition process or a spin-coating (SOG) process can be used to form a dielectric stack 50 that covers the third dielectric layer 4 and the target stack 20 and fills the second via H2. The dielectric stack 50 includes at least two dielectric layers stacked sequentially along the first direction. The bottom dielectric layer of the at least two dielectric layers covers the third dielectric layer 4 and the target stack 20 and partially fills the second via H2. This allows the number and thickness of the dielectric stack 50 layers to be set according to the aspect ratio of the metal interconnect structure to meet the actual process requirements of different application scenarios. By setting the bottom dielectric layer of at least two dielectric layers to cover the third dielectric layer 4 and the target stack 20 and partially fill the second via H2, the formation of interfaces between different layers in the second via H2 is avoided, and the presence of the layer interfaces can prevent arcing, thereby improving the yield and reliability of the metal interconnect structure.

[0077] As an example, please continue reading Figure 4 The at least two dielectric layers may include a first dielectric layer 51, a second dielectric layer 52, and a third dielectric layer 53 stacked sequentially along the OY direction. The first dielectric layer 51 covers the third dielectric layer 4 and the target stack 20, and fills the second via H2. The first dielectric layer 51 may be a TEOS (silicon oxide). For example, the first dielectric layer 51 can be formed using an SOG (Sodium Oxide Gel Gel) process, then the top surface of the first dielectric layer 51 can be planarized, and then the second dielectric layer 52 can be formed on the top surface of the first dielectric layer 51. The second dielectric layer 52 may be silicon oxide or TEOS. After planarizing the top surface of the second dielectric layer 52, the third dielectric layer 53 is formed on the top surface of the second dielectric layer 52. The third dielectric layer 53 may be silicon oxide or TEOS.

[0078] As an example, please continue reading Figure 4 The thicknesses of the first dielectric layer 51 and the second dielectric layer 52 can be the same, for example, both being the maximum thickness that can be deposited in a single process of the deposition equipment. Since the thicknesses of the first dielectric layer 51 and the second dielectric layer 52 are still insufficient to meet the height requirements for the subsequent fabrication of the metal interconnect structure, a third dielectric layer 53 is formed, so that the dielectric stack 50 composed of the first dielectric layer 51, the second dielectric layer 52, and the third dielectric layer 53 can meet the height requirements for the metal interconnect structure.

[0079] For example, please refer to Figures 4-5In step S50, after planarizing the top surface of the third dielectric layer 53, a photoresist material layer (not shown) is coated on the top surface of the third dielectric layer 53. Then, the photoresist material layer is patterned based on the target photomask to obtain a patterned photoresist layer PR that includes an opening pattern for defining parameters such as the shape, size, and position of the third via H3. Then, based on the patterned photoresist layer PR, the third dielectric layer 53, the second dielectric layer 52, and the first dielectric layer 51 are etched with the top surface of the third dielectric layer 4 as the etching endpoint to obtain a target stack 20 and a remaining dielectric stack 50 with the top surface flush with the top surface of the third dielectric layer 4, forming a third via H3 that penetrates the third dielectric layer 53, the second dielectric layer 52, and the first dielectric layer 51 along the OY direction and exposes the top surface of the target stack 20.

[0080] For example, please refer to Figures 5-6 Under the same etching conditions, the etching rate of the remaining dielectric stack 50 can be set to be significantly greater than that of the isolation layer 22, and the etching rate of the target carbon layer 21 can be much smaller than that of the remaining dielectric stack 50 and the isolation layer 22. For example, if the remaining dielectric stack 50 is TEOS, the isolation layer 22 is silicon nitride, and the target carbon layer 21 is α-carbon or fluorinated amorphous carbon, under the same etching conditions, the etching rate of silicon nitride is significantly smaller than that of TEOS, while α-carbon or fluorinated amorphous carbon is basically not etched. If the remaining dielectric stack 50 in the second via H2 is removed, and the height of the remaining isolation layer 22 is d2, and the initial thickness of the isolation layer 22 flush with the top surface of the third dielectric layer 4 is d1, then the thickness of the isolation layer 22 removed simultaneously during the removal of the remaining dielectric stack 50 in the second via H2 is d1 - d2. Therefore, the height of the isolation layer 22 and the height of the remaining dielectric stack 50 in the second via H2 can be set according to the etching selectivity ratio of the isolation layer 22 and the remaining dielectric stack 50 in the second via H2.

[0081] For example, please refer to Figures 6-7 In step S60, when the isolation layer 22 of the target thickness is removed under the same etching conditions, the remaining dielectric stack 50 in the second via H2 is removed simultaneously; the thickness of the third dielectric layer 4 is related to the target thickness, which facilitates the removal of the isolation layer 22 of the target thickness through the second via H2 during the etching process of the third dielectric layer 4 after the remaining dielectric stack 50 in the second via H2 is removed.

[0082] As an example, please continue reading Figures 6-7In step S60, under the same etching conditions, the etching rate of the isolation layer 22 can be set to be basically the same as the etching rate of the first dielectric layer 2. If, after the first dielectric layer 2 exposed by the second via H2 is removed, a groove H4 is obtained that exposes part of the conductive layer 1, and a remaining isolation layer 22 with its top surface flush with the top surface of the second dielectric layer 3, and the height of the remaining isolation layer 22 is d3, then the thickness of the isolation layer 22 removed during the removal of the first dielectric layer 2 exposed by the second via H2 is d2-d3. Therefore, the thickness of the first dielectric layer 2 can be set to d2-d3. During the removal of the first dielectric layer 2 exposed by the second via H2, a remaining isolation layer 22 with its top surface flush with the top surface of the second dielectric layer 3 is simultaneously obtained.

[0083] For example, please refer to Figure 8 In step S70, a target gas containing ozone can be used to treat and remove the target carbon layer 21. Ozone (O3), as a strong oxidant, has extremely strong oxidizing power and can react with amorphous carbon, oxidizing it into smaller molecules such as carbon dioxide and water. This reaction is usually carried out at low temperatures, achieving the oxidative decomposition of amorphous carbon through direct contact between ozone and the amorphous carbon. This removes the target carbon layer 21, resulting in an air gap 7 between the adjacent remaining insulating layers 22, and avoids oxidation of the exposed surface of the conductive layer 1 at high temperatures.

[0084] For example, please refer to Figure 9 Since the size of the air gap 7 is less than half the size of the remaining isolation layer 22 (the length along the OX direction), in step S80, during the deposition and formation of the metal barrier layer 9, the air gap 7 is usually sealed in advance due to its small opening size. After the metal barrier layer covering the inner wall of the third through hole H3, the top surface of the remaining isolation layer 22, and the inner surface of the groove H4 is formed, the adjacent remaining isolation layers 22 include the air gap 7. This reduces the dielectric constant between the metal interconnect structure and the dielectric sidewall formed in the third through hole H3 and the groove H4, and avoids the formation of a current leakage path between the metal interconnect structure and the dielectric sidewall. Since the opening size of the second through-hole H2 is smaller than that of the third through-hole H3, it is easier to form a T-shaped metal interconnect structure in the future. This avoids the formation of voids or gaps at the bottom due to the decrease in the kinetic energy of the deposited metal ions during the metal deposition process, thus improving the performance of the metal interconnect structure. The metal barrier layer 9 can prevent metal ions from entering the dielectric sidewall during the subsequent metal deposition process, effectively preventing the generation of current leakage channels and further improving the performance and reliability of the metal interconnect structure.

[0085] In some embodiments, a semiconductor structure is provided, which can be fabricated using any of the semiconductor structure fabrication methods described in this disclosure.

[0086] Please continue reading. Figure 9 In some embodiments, the semiconductor structure includes a substrate 100 and a metal barrier layer 9. The substrate 100 includes a conductive layer 1, a first dielectric layer 2, and a support stack (not shown) stacked sequentially along a first direction perpendicular to the top surface of the substrate 100. The support stack includes a first via H1 extending along the first direction to the top surface of the first dielectric layer 2. The first via H1 includes isolation layers 22 arranged at intervals along a second direction parallel to the top surface of the substrate 100. The innermost isolation layer 22, away from the support stack, defines a groove H4 that exposes a portion of the conductive layer 1. The metal barrier layer 9 covers at least a portion of the sidewalls of the first via H1, the top surface of the isolation layer 22, and the inner surface of the groove H4.

[0087] As an example, please continue reading Figures 8-9 The innermost isolation layer 22, which is far from the support stack, defines a second through-hole H2 that exposes the groove H4; the metal barrier layer 9 also covers the inner sidewall of the second through-hole H2.

[0088] As an example, please continue reading Figures 8-9 The semiconductor structure also includes a dielectric stack 50 located on the top surface of the supporting stack; a first via H1 also penetrates the dielectric stack 50 along a first direction; and a metal barrier layer 9 also extends into the dielectric stack 50 along the first direction.

[0089] As an example, please continue reading Figures 8-9 The supporting stack includes a third dielectric layer 4 and a second dielectric layer 3 located between the first dielectric layer 2 and the third dielectric layer 4; the top surface of the isolation layer 22 is flush with the top surface of the second dielectric layer 3.

[0090] For example, please refer to Figure 10 ,and Figure 3 The differences include: Figure 3 The top surface of the second dielectric layer 3 includes the third dielectric layer 4. Figure 10 The first via V1 penetrates the second dielectric layer 3 along the OY direction, exposing part of the top surface of the first dielectric layer 2. Figure 3 In the process, the inner surface of the first via V1 includes a target carbon layer 21 and an isolation layer 22 alternately stacked from the outside to the inside. The fabrication process of the target carbon layer 21 and the isolation layer 22 can be found in [reference needed]. Figure 3 The preparation process of the target carbon layer 21 and the isolation layer 22 will not be described in detail here.

[0091] As an example, please continue reading Figure 10The thickness of the target carbon layer 21 is less than half the thickness of the isolation layer 22. In this embodiment, the thickness refers to the length along the OX direction. The thickness of the target carbon layer 21 can be 10nm-20nm, for example, 10nm, 13nm, 15nm, 18nm, or 20nm, etc. The thickness of the isolation layer 22 can be determined based on the opening size of the second via V2 and the thickness and number of target carbon layers 21. For example, if the opening size of the first via V1 is 1.7μm, the opening size of the second via V2 is 324nm, the thickness of the target carbon layer 21 is 10nm, and the number of stacked layers of the target carbon layer 21 is 2, then the thickness of the isolation layer 22 can be 3500nm-4500nm, for example, 3500nm, 3800nm, 4000nm, 4200nm, 4300nm, or 4500nm, etc. The material of the target carbon layer 21 may include, but is not limited to, α-carbon, fluorinated amorphous carbon, or combinations thereof. The isolation layer 22 may include silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof.

[0092] For example, please refer to Figure 11 A first dielectric layer 51 is formed by chemical vapor deposition (CVD) covering the top surface of the target carbon layer 21, the top surface of the isolation layer 22, and the top surface of the second dielectric layer 3. The first dielectric layer 51 can be TEOS. Due to the good step coverage of CVD, it is easy to form a bubble V2a above the second via V2 that communicates with the second via V2.

[0093] For example, please refer to Figure 12 After planarizing the top surface of the first dielectric layer 51, a second dielectric layer 52 is formed on the top surface of the first dielectric layer 51. The second dielectric layer 52 can be silicon oxide or TEOS. After planarizing the top surface of the second dielectric layer 52, a third dielectric layer 53 is formed on the top surface of the second dielectric layer 52. The third dielectric layer 53 can be silicon oxide or TEOS.

[0094] For example, please refer to Figures 12-13 After planarizing the top surface of the third dielectric layer 53, a photoresist material layer (not shown) is coated on the top surface of the third dielectric layer 53. Then, the photoresist material layer is patterned based on the target photomask to obtain a patterned photoresist layer PR that includes an opening pattern for defining parameters such as the shape, size, and position of the first via V1. Then, based on the patterned photoresist layer PR, the third dielectric layer 53, the second dielectric layer 52, and the first dielectric layer 51 are etched with the top surface of the second dielectric layer 3 as the etching endpoint to obtain a target carbon layer 21 and an isolation layer 22 with their top surfaces flush with the top surface of the second dielectric layer 3.

[0095] For example, please refer to Figure 14The first dielectric layer 2 is etched through the second via V2, so that the top surface of the conductive layer 1 is partially exposed through the second via V2.

[0096] For example, please refer to Figure 15 The target carbon layer 21 is treated and removed by a target gas containing ozone, resulting in an air gap 7 between adjacent remaining isolation layers 22, and the exposed surface of the conductive layer 1 is protected from oxidation by high temperature.

[0097] For example, please refer to Figure 16 Since the size of the air gap 7 is less than half the size of the remaining insulating layer 22 (referring to its length along the OX direction), it is typically sealed beforehand during the deposition and formation of the metal barrier layer 9 due to the small opening size of the air gap 7. After the metal barrier layer 9 is formed, covering the inner wall of the second via V2 and the top surface of the remaining insulating layer 22, an air gap 7 is included between adjacent remaining insulating layers 22. This reduces the dielectric constant between the metal interconnect structure and the dielectric sidewall formed subsequently in the second via V2, preventing current leakage paths between the metal interconnect structure and the dielectric sidewall. Because the opening size of the second via V2 is smaller than that of the first via V1, it facilitates the subsequent formation of a T-shaped metal interconnect structure. This prevents voids or gaps from appearing at the bottom due to the decreased kinetic energy of deposited metal ions during the metal deposition process, improving the performance of the metal interconnect structure. The metal barrier layer 9 prevents metal ions from entering the dielectric sidewall during the subsequent metal deposition process, effectively preventing the formation of current leakage paths and further improving the performance and reliability of the metal interconnect structure.

[0098] In some embodiments, please refer to Figure 9 or Figure 16 A semiconductor structure is provided, comprising: a semiconductor structure prepared by any of the semiconductor structure preparation methods in the embodiments of this disclosure.

[0099] The unexpected technical effects that can be produced by the embodiments of this disclosure include:

[0100] The bottom of the metal interconnect structure is isolated from the surrounding dielectric sidewalls by an air gap, which effectively improves the isolation effect. The T-shaped metal interconnect structure can avoid the formation of voids or gaps at the bottom due to the decrease in the kinetic energy of deposited metal ions during the metal deposition process, thus improving the performance of the metal interconnect structure. The metal barrier layer can prevent metal ions from entering the dielectric sidewalls during the subsequent metal deposition process, effectively preventing the generation of current leakage channels and further improving the performance and reliability of the metal interconnect structure.

[0101] In some embodiments, an electronic device is provided, including the semiconductor structure of any embodiment of this disclosure.

[0102] The aforementioned electronic devices include, but are not limited to, suitable types of electronic products such as consumer electronics, home electronics, automotive electronics, and financial terminals. Consumer electronics include mobile phones, tablets, laptops, desktop monitors, and all-in-one computers. Home electronics include smart locks, televisions, refrigerators, and wearable devices. Automotive electronics include car navigation systems and car DVD players. Financial terminals include ATMs and self-service terminals.

[0103] Please note that, for the sake of brevity, in the structural diagrams given in the following embodiments, unless a separate cross-sectional structural diagram is given, structural diagrams from different perspectives related to the inventive points of the embodiments of this disclosure can be referred to each other.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate includes a conductive layer, a first dielectric layer and a second dielectric layer sequentially stacked along a first direction perpendicular to the top surface of the substrate; Based on the target photomask, a first via is formed that penetrates the second dielectric layer along the first direction; A target stack is formed on the inner sidewall of the first via, the target stack defining a second via that exposes a portion of the first dielectric layer, the target stack comprising target carbon layers and isolation layers alternately stacked from the outside to the inside; A dielectric stack covering the second dielectric layer and the target stack is formed; Based on the target photomask, a third via is formed that penetrates the dielectric stack along the first direction and exposes the target stack and the second via; After simultaneously etching and removing part of the first dielectric layer through the third via and the second via, a groove is obtained that exposes part of the conductive layer. Remove the target carbon layer to obtain an isolation layer with spaced spacing and a top surface flush with the top surface of the second dielectric layer; A metal barrier layer is formed covering the inner wall of the third through hole, the top surface of the isolation layer, and the inner surface of the groove, wherein an air gap is included between adjacent isolation layers.

2. The semiconductor structure fabrication method according to claim 1, characterized in that, The dielectric stack includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked sequentially along the first direction; Wherein, the first dielectric layer covers the second dielectric layer and the target stack; The second via includes a bubble extending along the first direction into the first dielectric layer, the bubble being in communication with the second via.

3. The semiconductor structure fabrication method according to claim 1, characterized in that, The innermost isolation layer of the target stack, furthest from the second dielectric layer, defines the second via.

4. The semiconductor structure fabrication method according to claim 2 or 3, characterized in that, A first dielectric layer is formed by chemical vapor deposition covering the top surface of the second dielectric layer and the top surface of the target stack.

5. The semiconductor structure fabrication method according to claim 2 or 3, characterized in that, Forming the third through hole includes: A patterned photoresist layer is obtained on the top surface of the dielectric stack based on the target photomask; Based on the patterned photoresist layer, and using the isolation layer as the etching stop layer, the dielectric stack is etched to obtain the third via.

6. The method for fabricating a semiconductor structure according to any one of claims 1-3, characterized in that, Removing the target carbon layer includes: The target carbon layer is treated and removed using a target gas containing ozone.

7. The method for fabricating a semiconductor structure according to any one of claims 1-3, characterized in that, Includes at least one of the following features: The target carbon layer includes α-carbon and / or fluorinated amorphous carbon; The isolation layer comprises silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination thereof; The first dielectric layer contains silicon, nitrogen and carbon.

8. A semiconductor structure, characterized in that, include: A substrate includes a conductive layer, a first dielectric layer, and a second dielectric layer sequentially stacked along a first direction perpendicular to the top surface of the substrate; the second dielectric layer includes a first via extending along the first direction to the first dielectric layer; the first via includes isolation layers arranged at intervals along a second direction parallel to the top surface of the substrate, wherein the innermost isolation layer, away from the second dielectric layer, defines a groove exposing a portion of the conductive layer; the innermost isolation layer, away from the second dielectric layer, defines a second via exposing the groove. A dielectric stack covering the second dielectric layer and the isolation layer, wherein the dielectric stack includes a third via exposing the isolation layer and the second via; A metal barrier layer covers at least a portion of the sidewall of the third through hole, the top surface of the isolation layer, and the inner surface of the groove.

9. The semiconductor structure according to claim 8, characterized in that, The metal barrier layer also covers the inner wall of the second via.

10. The semiconductor structure according to claim 9, characterized in that, The dielectric stack includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked sequentially along the first direction; Wherein, the first dielectric layer covers the second dielectric layer and the isolation layer; The second via includes a bubble extending along the first direction into the first dielectric layer, the bubble being in communication with the second via.

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