Clock signal compensation method

Abstract

The invention discloses a clock signal compensation method, and relates to the technical field of network time synchronization, and the method comprises the steps: detecting a program operation state of a first synchronization program; under the condition that the program running state is used for indicating that a first clock signal synchronized by the first synchronization program for the network equipment has clock signal deviation, generating a clock compensation parameter for the first synchronization program according to the first clock signal and a second clock signal synchronized by the second synchronization program for the network equipment, obtaining a target deviation parameter of the first synchronization program; the first clock signal is compensated according to the clock compensation parameter and the target deviation parameter, the target clock signal is obtained, the network device is used for executing the to-be-operated service through the target clock signal, the technical problem that in the related technology, the time synchronization efficiency of the network device is low is solved, and the time synchronization efficiency of the network device is improved. The technical effect of improving the time synchronization efficiency of the network equipment is achieved.

Description

Technical Field

[0001] This application relates to the technical field of network time synchronization, and particularly to a method for compensating clock signals. Background Art

[0002] In modern network communications, clock signals are key information required by network devices when performing network operation tasks, thus ensuring that the operation tasks of network devices can be efficiently and accurately executed. In related technologies, a clock signal synchronization program is configured for network devices to synchronize clocks. Although this method can basically meet the clock synchronization requirements of network devices, once the running clock signal synchronization program fails, the synchronized clock signal will be inaccurate, thereby affecting the running state of network devices. Summary of the Invention

[0003] This application provides a method for compensating clock signals to at least solve the problem of low time synchronization efficiency for network devices in related technologies.

[0004] This application provides a method for compensating clock signals, including:

[0005] Detect the program running state of the first synchronization program;

[0006] When the program running state indicates that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device, generate clock compensation parameters for the first synchronization program according to the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, and obtain the target deviation parameter of the first synchronization program, where the clock synchronization accuracy of the first synchronization program is higher than that of the second synchronization program, and the target deviation parameter is used to indicate the influence relationship of the clock signal synchronization method currently used by the first synchronization program to synchronize the clock signal for the network device on the clock signal deviation amount;

[0007] Compensate the first clock signal according to the clock compensation parameter and the target deviation parameter to obtain a target clock signal, where the network device is used to execute the to-be-run service using the target clock signal.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above methods for compensating clock signals when executing the computer program.

[0009] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above methods for compensating clock signals are implemented.

[0010] The present application also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of any one of the above clock signal compensation methods.

[0011] Through the present application, by setting two synchronization programs with different synchronization accuracies to synchronize clock signals for a network device, where the program with a higher clock synchronization accuracy is used as the first synchronization program and the program with a lower clock synchronization accuracy is used as the second synchronization program, first, the program running state of the first synchronization program is detected. When the program running state of the first synchronization program indicates that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device, clock compensation parameters for the first synchronization program are generated based on the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, and a target deviation parameter indicating the influence relationship of the clock signal synchronization method currently used by the first synchronization program to synchronize clock signals for the network device on the clock signal deviation amount is obtained. Then, the first clock signal is compensated based on the clock compensation parameters and the target deviation parameter to obtain a target clock signal, thereby ensuring the accuracy of the clock signal synchronized for the network device. Furthermore, the network device can use the target clock signal with higher accuracy to execute the to-be-operated service. Therefore, the technical problem of low time synchronization efficiency for network devices in the related art can be solved, and the technical effect of improving the time synchronization efficiency for network devices can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0013] Figure 1 is a hardware structure block diagram of a clock signal compensation method according to an embodiment of the present application;

[0014] Figure 2 is a flowchart of a clock signal compensation method according to an embodiment of the present application;

[0015] Figure 3 is a system architecture diagram of a PTP / NTP dynamic switching time synchronization system based on an SR-IOV network card according to an embodiment of the present application;

[0016] Figure 4 is a flowchart of a protocol switching trigger condition according to an embodiment of the present application;

[0017] Figure 5 is a flowchart of a protocol switching process according to an embodiment of the present application;

[0018] Figure 6 It is a structural block diagram of a compensation device for a clock signal according to an embodiment of the present application. Specific embodiments

[0019] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection scope of the present application.

[0020] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0021] In order to enable those skilled in the art of the present technology to better understand the solutions of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0022] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the clock signal compensation method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0023] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 It is a hardware structural block diagram of a clock signal compensation method according to an embodiment of the present application. As Figure 1 shown, the server device may include one or more ( Figure 1 only one is shown in the figure) processors 102 (the processors 102 may include, but are not limited to, processing devices such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Among them, the above server device may further include a transmission device 106 for communication functions and an input / output device 108. Those of ordinary skill in the art can understand that Figure 1 the structure shown in the figure is only for illustration and does not limit the structure of the above server device. For example, the server device may further include more or fewer components than those shown in Figure 1 the figure, or have a different configuration from that shown in Figure 1 the figure.

[0024] The memory 104 can be used to store computer programs, such as software programs and modules of application software, such as the computer program corresponding to the startup method of the operating system in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, that is, the above-mentioned method is implemented. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, the memory 104 may further include memories remotely disposed relative to the processor 102, and these remote memories can be connected to the server device through a network. Examples of the above-mentioned network include but are not limited to the Internet, enterprise intranet, local area network, mobile communication network, and combinations thereof.

[0025] The transmission device 106 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wireless network provided by a communication provider of the server device. In one instance, the transmission device 106 includes a network adapter (Network Interface Controller, abbreviated as NIC), which can be connected to other network devices through a base station and thus can communicate with the Internet. In one instance, the transmission device 106 may be a radio frequency (Radio Frequency, abbreviated as RF) module, which is used to communicate with the Internet wirelessly.

[0026] Embodiments of the present application provide a method for compensating a clock signal. In combination with the execution flow of the method for compensating the clock signal, the method is described in detail.

[0027] The following explains the professional terms that appear in the present application:

[0028] PTP: Precision Time Protocol, a high-precision time protocol;

[0029] NTP: Network Time Protocol, a network time protocol;

[0030] VF: Virtual Function, a virtual function;

[0031] VM: Virtual Machine, a virtual machine;

[0032] SR-IOV: Single Root I / O Virtualization. It is single-root I / O virtualization. SR-IOV allows a physical network card to be virtualized into multiple independent virtual functions (VFs). Each VF can be directly mapped to a virtual machine (VM), bypassing the intervention of the hypervisor, thereby reducing network latency and improving performance;

[0033] PF: Physical Function;

[0034] PCIe: Peripheral Component Interconnect Express;

[0035] DMA: Direct Memory Access;

[0036] CPU: Central Processing Unit;

[0037] API: Application Programming Interface.

[0038] In this embodiment, a method for compensating a clock signal is provided. Figure 2 It is a flowchart of the method for compensating a clock signal according to an embodiment of the present application. As Figure 2 shown, the method includes the following steps:

[0039] Step S202, detecting the program running state of the first synchronization program;

[0040] Step S204, when the program running state indicates that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device, generating a clock compensation parameter for the first synchronization program according to the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, and obtaining a target deviation parameter of the first synchronization program, where the clock synchronization accuracy of the first synchronization program is higher than that of the second synchronization program, and the target deviation parameter is used to indicate the influence relationship of the clock signal synchronization method currently adopted by the first synchronization program for synchronizing the clock signal for the clock signal deviation amount;

[0041] Step S206, compensating the first clock signal according to the clock compensation parameter and the target deviation parameter to obtain a target clock signal, where the network device is used to execute the to-be-run service using the target clock signal.

[0042] Through the above steps, clock signals are synchronized for network devices by setting two synchronization programs with different synchronization accuracies. Among them, the program with a higher clock synchronization accuracy is used as the first synchronization program, and the program with a lower clock synchronization accuracy is used as the second synchronization program. First, the program running state of the first synchronization program is detected. When the program running state of the first synchronization program indicates that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device, clock compensation parameters for the first synchronization program are generated based on the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, and a target deviation parameter indicating the influence relationship of the clock signal synchronization method currently used by the first synchronization program to synchronize the clock signal for the network device on the clock signal deviation amount is obtained. Then, the first clock signal is compensated according to the clock compensation parameters and the target deviation parameter to obtain a target clock signal, thereby ensuring the accuracy of the clock signal synchronized for the network device. Furthermore, the network device can use the target clock signal with higher accuracy to execute the to-be-operated service. Therefore, the technical problem of low time synchronization efficiency for network devices in the related art can be solved, and the technical effect of improving the time synchronization efficiency for network devices can be achieved.

[0043] In the embodiment provided in step S202, the first synchronization program is a clock synchronization program with a clock synchronization accuracy higher than a set threshold, and the first synchronization program can be PTP (Precision Time Protocol).

[0044] Optionally, in the embodiment of the present application, detecting the program running state of the first synchronization program is used to monitor the accuracy and stability of the first synchronization program for clock signal synchronization in real time. The program running state of the first synchronization program is detected in the following manner: continuously collect the running data of the first synchronization program, where the running data includes peer delay and clock offset. The peer delay is used to indicate the one-way average delay of the signal transmitted back and forth between the master clock and the slave clock of the first synchronization program, and the clock offset is used to indicate the time deviation value between the master clock and the slave clock of the first synchronization program; set a peer delay threshold and a clock offset threshold for the first synchronization program; when the peer delay of the first synchronization program is greater than the peer delay threshold, or the clock offset is greater than the clock offset threshold, it is determined that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device.

[0045] In the embodiment provided in step S204, the second synchronization program is a clock synchronization program with a clock synchronization accuracy lower than a set threshold. The second synchronization program may be NTP (Network Time Protocol). In this application, the first synchronization program with a higher clock synchronization accuracy (such as the PTP protocol) is used as the primary synchronization program, and the second synchronization program with a lower clock synchronization accuracy (such as the NTP protocol) is used as the secondary synchronization program, forming a dual-mode time synchronization architecture. Under normal working conditions, due to its hardware support characteristics, PTP can provide high-precision time synchronization at the sub-microsecond level, while NTP serves as a backup for ensuring the time synchronization of network devices when the performance of PTP is insufficient or unavailable, ensuring the continuity and accuracy of clock signal synchronization. Furthermore, when the performance of PTP degrades due to reasons such as network fluctuations and hardware failures, high-precision time synchronization can still be maintained through dynamic compensation by NTP, ensuring the stable operation of network devices and service continuity.

[0046] Optionally, in the embodiment of this application, the clock compensation parameter is used to indicate the amount of clock compensation required for the first clock signal currently synchronized by the first synchronization program under the clock synchronization accuracy of the second synchronization program. The clock compensation parameter may be, but is not limited to, the time difference between the first clock signal and the second clock signal.

[0047] Optionally, in the embodiment of this application, when the first synchronization program synchronizes the clock signal, different clock signal synchronization methods will have different degrees of influence on the deviation amount of the synchronized clock signal. Furthermore, the target deviation parameter will affect the compensation amount for compensating the first clock signal. The target deviation parameter is used to quantify the influence degree of the clock signal synchronization method currently adopted by the first synchronization program on the clock signal deviation amount. The occurrence of clock signal deviation in the first clock signal may be caused by various factors. Obtain the influencing factors that affect the clock signal deviation. The influencing factors may include, but are not limited to, network delay, clock offset, node temperature, CPU utilization, etc. Use a causal inference method (such as Granger causality analysis method) to evaluate the causal relationship between the above influencing factors and the clock signal deviation. For each influencing factor, construct a time series model to predict the future clock signal deviation, and use the Granger causality test method to test whether each influencing factor has predictability for the clock signal deviation. For each influencing factor, if its causal relationship with the clock signal deviation is significant, calculate its causal strength according to the contribution of the factor in deviation prediction. Among them, the target deviation parameter includes the causal strength.

[0048] In the embodiment provided in step S206, compensating the first clock signal according to the clock compensation parameter and the target deviation parameter may be to convert the target deviation parameter into a weight parameter, multiply the weight parameter by the initial clock compensation amount indicated by the clock compensation parameter to obtain the target clock compensation amount, and use the target clock compensation amount to compensate the first clock signal to obtain the target clock signal. Furthermore, the network device can use the compensated target clock signal to update and synchronize the internal clock, ensuring that the time bases of all service modules are consistent.

[0049] As an alternative implementation, compensating the first clock signal according to the clock compensation parameter and the target deviation parameter to obtain the target clock signal includes:

[0050] Converting the target deviation parameter into a weight parameter of the initial clock compensation amount, where the clock compensation parameter includes the initial clock compensation amount, and the initial clock compensation amount is used to indicate the difference between the first clock signal and the second clock signal;

[0051] Performing a weighted calculation on the initial clock compensation amount using the weight parameter to obtain the target clock compensation amount;

[0052] Compensating the first clock signal using the target clock compensation amount to obtain the target clock signal.

[0053] Optionally, in the embodiments of the present application, the initial clock compensation amount is the original compensation requirement calculated based on the deviation between the currently measured first clock signal and the second clock signal, and is used to indicate the time difference between the first clock signal and the second clock signal. The weight parameter is converted from the target deviation parameter, and the weight parameter is used to reflect the demand situation of the clock signal synchronized by the first synchronization program using the current synchronization method for the initial clock compensation amount.

[0054] Optionally, in the embodiments of the present application, the target deviation parameter is obtained by performing a causal analysis between the clock signal synchronization method of the first synchronization program under the influence of external factors and the deviation amount of the clock signal synchronized by the first synchronization program, and is used to indicate the contribution degree of the clock signal synchronization method of the first synchronization program under the influence of external factors to the deviation of the clock signal synchronized by the first synchronization program. In this embodiment, first, this contribution degree is converted into a weight parameter W, using the formula:

[0055] ;

[0056] Among them, C is the target deviation parameter, and C0 is a preset threshold for balancing the relationship between the low precision of NTP and the high precision of PTP. By performing a weighted calculation on the weight parameter and the initial clock compensation amount, the final target clock compensation amount is obtained. This process ensures that the compensation amount can not only reflect the immediate deviation but also dynamically adjust the compensation ratio according to the significance of external factors, thereby achieving more accurate time synchronization. After obtaining the target clock compensation amount, the first clock signal is accurately compensated to correct the deviation from the second clock signal.

[0057] Optionally, in the embodiment of the present application, it is assumed that the system monitors a clock signal deviation between the first clock signal and the second clock signal, and the calculated target deviation parameter C = 0.2. Setting the preset threshold C0 = 0.1, the weight parameter W is calculated as follows:

[0058] = ;

[0059] This means that in the current situation, the compensation effect of the second clock signal accounts for approximately 67% of the proportion. Assuming the initial clock compensation amount is 10 μs, then the weighted calculated target clock compensation amount is: the initial clock compensation amount × the weight parameter = 10 μs × 0.67 = 6.7 μs. Subsequently, the system uses 6.7 μs as the target clock compensation amount to compensate the first clock signal.

[0060] Through the above method, not only can the deviation of the first clock signal be effectively corrected, but also through intelligent weight adjustment, it is ensured that the system can respond quickly and accurately in the face of external factors, enhancing the overall time synchronization performance and stability.

[0061] As an alternative implementation, the weight parameter is calculated by the following formula:

[0062] ;

[0063] Where W is the weight parameter, C is the target deviation parameter, and C0 is the preset threshold.

[0064] Optionally, in the embodiment of the present application, by introducing W, C, and C0, the system has the ability to dynamically balance the time synchronization of the first synchronization program and the second synchronization program. When the deviation of the first clock signal increases due to external factors, the value of C will also increase accordingly, thereby driving the value of W to rise, and the system will increase the compensation effect of the second clock signal, and vice versa. This dynamic balancing mechanism enables the system to more flexibly respond to the changing network environment and hardware conditions, improving the overall adaptability and robustness.

[0065] As an alternative implementation, obtaining the target deviation parameter of the first synchronization program includes:

[0066] Obtaining the reference running information of the first synchronization program at each of multiple reference times before the current time and the reference deviation amount of the clock signal synchronized by the first synchronization program at the corresponding reference time, where the reference running information is used to indicate the clock signal synchronization method when the first synchronization program synchronizes the clock signal for the network device at the reference time;

[0067] Generating a target deviation parameter based on the reference running information and the reference deviation amount.

[0068] Optionally, in the embodiments of the present application, the reference running information is used to indicate the influencing factors causing deviations to the first clock signal. The reference running information may include, but is not limited to, node temperature, network round-trip time, CPU utilization, etc. The reference deviation amount is used to indicate the clock signal deviation amount generated when the first synchronization program operates in the clock signal synchronization method indicated by the reference running information. Then, a target deviation parameter is generated based on the reference running information and the reference deviation amount.

[0069] As an alternative implementation, generating a target deviation parameter based on the reference running information and the reference deviation amount includes:

[0070] When the reference running information includes sub-running information of multiple information types, generating an initial deviation parameter corresponding to the sub-running information of the current information type based on the sub-running information of the same information type at multiple reference times and the reference deviation amounts at multiple reference times, where the sub-running information of multiple information types is used to characterize the clock signal synchronization method when the first synchronization program synchronizes the clock signal for the network device in multiple information dimensions;

[0071] Combining the initial deviation parameters of the sub-running information of multiple information types into a target deviation parameter.

[0072] Optionally, in the embodiments of the present application, the sub-run information of multiple information types is used to indicate the influencing factors that cause deviations in the first clock signal in different dimensions. The sub-run information may include, but is not limited to, clock deviation values (the difference between the actual value and the ideal value at a historical moment), network parameters (such as network round-trip time), hardware status (such as DMA latency, CPU utilization), environmental metrics (such as node temperature), etc. The method of combining the initial deviation parameters of the sub-run information of multiple information types to obtain the target deviation parameter may be, but is not limited to, by summing the initial deviation parameters of the sub-run information of multiple information types to obtain the target deviation parameter, or alternatively, the information weights of the sub-run information of multiple information types may be used to perform weighted summation on multiple initial deviation parameters to obtain the target deviation parameter, where the information weight is determined according to the influence of the sub-run information of the corresponding information type on the deviation amount of the clock signal output by the first synchronization program. The method of determining the information weight may be, but is not limited to, obtaining the information deviation amount between the sub-run information of each information type and the information threshold corresponding to this information type, and allocating the information weight of the sub-run information of the corresponding information type according to the information deviation amounts of the sub-run information of multiple information types, where the greater the information deviation amount of the sub-run information of an information type, the greater the information weight of the sub-run information of this information type, and the information threshold is used to indicate the normal information threshold of the running information of the corresponding information type.

[0073] Through the above method, the generated target deviation parameter synthesizes multiple influencing factors and can guide the system to make a more intelligent compensation decision. Whether it is a hardware failure, network fluctuation, or environmental change, the system can automatically adjust the compensation amount and compensation method according to the latest running state to ensure high precision and high stability of time synchronization.

[0074] As an optional implementation manner, the initial deviation parameter corresponding to the sub-run information of the current information type is calculated through the following formula:

[0075] ;

[0076] Wherein, is the initial deviation parameter corresponding to the sub-run information of the current information type, is the reference deviation amount at time t, is the reference deviation amount at time t - i, is the first coefficient, is the second coefficient, is the third coefficient, is the sub-run information of the current information type at time t - j.

[0077] Optionally, in the embodiments of the present application, is the expected clock deviation amount, is the autoregressive coefficient, which is used to measure the deviation at time t affected by the past deviation The degree of influence reflects the autocorrelation of the deviation over time, that is, the predictive ability of the historical trend of the deviation itself on the current deviation. is the random error term, which reflects the uncertain factors in predicting the deviation.

[0078] Optionally, in the embodiment of the present application, a dynamic model is constructed to predict the clock deviation of the current information type. This model not only considers the influence coefficient and autoregressive part of the past value of the deviation on the current deviation, but also considers the predictive effect of the historical data of external factors (such as node temperature, network round-trip time, CPU utilization, etc.) on the clock deviation. This enables the system to more accurately predict the future deviation trend based on past performance and dynamic changes in the current environment, thereby providing a more detailed and quantitative basis for the decision-making of the dynamic time synchronization system (such as when to trigger protocol switching, how to adjust the compensation strategy, etc.).

[0079] As an optional implementation manner, the initial deviation parameters of the sub-run information of multiple information types are combined into a target deviation parameter, including:

[0080] Perform a summation calculation on multiple initial deviation parameters to obtain the target deviation parameter.

[0081] Optionally, in the embodiment of the present application, the target deviation parameter can be obtained by directly summing multiple initial deviation parameters, or it can also be a weighted summation of multiple initial deviation parameters according to the importance degree. For example, different weights are set according to the change degree of the sub-run information. Calculate the change rate within a period of time for each sub-run information, such as the change rate of network delay, the fluctuation range of CPU occupancy rate, etc.; assign weight parameters from large to small to multiple sub-run information in the order of the change rate of multiple sub-run information from high to low, where the sum of the weight parameters of multiple sub-run information is 1; perform a weighted summation of the initial deviation parameter corresponding to each sub-run information and its corresponding weight parameter to obtain the final target deviation parameter.

[0082] As an optional implementation manner, according to the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, generate a clock compensation parameter for the first synchronization program, including:

[0083] Calculate the difference between the first clock signal and the second clock signal to obtain the target clock difference;

[0084] Determine the target clock difference as the initial clock compensation amount for the clock signal synchronized by the first synchronization program, where the clock compensation parameter includes the initial clock compensation amount.

[0085] Optionally, in the embodiments of the present application, since the clock synchronization accuracy between the first synchronization program and the second synchronization program is different, there is a time difference between the first clock signal and the second clock signal. For example, at a certain moment, the time shown by the first clock signal is 10:00:00.00001 seconds, while the time shown by the second clock signal is 10:00:00.0001 seconds, that is, the clock signal synchronization accuracy of the first synchronization program is higher than that of the second synchronization program, resulting in a difference of 0.00009 seconds between the first clock signal and the second clock signal. Then, this 0.00009 seconds is determined as the initial clock compensation amount.

[0086] As an optional implementation manner, detecting the program running state of the first synchronization program includes:

[0087] Detecting the current peer delay of the first synchronization program and detecting the clock offset;

[0088] In the case where the peer delay is greater than or equal to the first threshold and the clock offset is greater than or equal to the second threshold, it is determined that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device.

[0089] Optionally, in the embodiments of the present application, the peer delay is used to indicate the one-way average delay of the signal transmitted back and forth between the master clock and the slave clock of the first synchronization program, and the clock offset is used to indicate the time deviation value between the master clock and the slave clock of the first synchronization program. The following message exchanges are used to obtain timestamps and calculate the peer delay and the clock offset:

[0090] I. Message exchange and timestamp mechanism:

[0091] Sync: The master clock sends a synchronization message and records the transmission time t1 (master clock time).

[0092] Follow_Up (optional): If the master clock does not support embedding a timestamp in the Sync message, t1 is passed through the Follow_Up message.

[0093] Delay_Req: After receiving the Sync, the slave clock sends a delay request message and records the transmission time t3 (slave clock time).

[0094] Delay_Resp: The master clock replies with a Delay_Resp message, carrying the reception time t4 (master clock time).

[0095] II. Deduction of the peer delay time calculation formula:

[0096] 1. Delay from master to slave direction ( )

[0097] ;

[0098] t1: The time when the master clock sends Sync.

[0099] t2: The time when the slave clock receives Sync (the local time of the slave clock, which needs to be corrected for offset and then converted to the time aligned with the master clock).

[0100] 2. Delay from slave to master ( ):

[0101] ;

[0102] t3: The time when the slave clock sends Delay_Req.

[0103] t4: The time when the master clock receives Delay_Req.

[0104] 3. Assuming the network is symmetric (bidirectional delay is equal), the peer delay is:

[0105] ;

[0106] Implementation steps:

[0107] 1. The slave clock records times t2 and t3, and the master clock records times t1 and t4;

[0108] 2. The master clock passes t1 and t4 to the slave clock through Follow_Up and Delay_Resp;

[0109] 3. The slave clock calculates the peer delay D according to the formula.

[0110] III. Clock offset calculation:

[0111] Derivation of the clock offset calculation formula:

[0112] 1. Define the time relationship:

[0113] Master clock time ;

[0114] Slave clock time ;

[0115] 2. According to the timestamps passed by the Sync message (assuming the delay from master to slave is ):

[0116] ;

[0117] 3. Combining the timestamps of the Delay_Req message (delay from slave to master ):

[0118] ;

[0119] 4. Solve for Offset by simultaneous equations: .

[0120] Implementation steps:

[0121] 1. Receive t1 and t4 of the master clock from the slave clock;

[0122] 2. Use the locally recorded t2 and t3 and substitute them into the formula to calculate Offset;

[0123] 3. If Offset is positive, it means the master clock is slower than the slave clock; if negative, it means the slave clock is faster.

[0124] IV. Implementation of the dynamic monitoring stage:

[0125] In a dynamic switching system, it is necessary to continuously calculate the peer delay and clock offset, and compare them with the threshold to trigger a switch. The monitoring process is as follows:

[0126] 1. Periodic message exchange:

[0127] (1) The master and slave clocks exchange messages such as Sync and Delay_Req at fixed intervals (e.g., once per second);

[0128] (2) Collect timestamps t1, t2, t3, t4.

[0129] 2. Real-time calculation:

[0130] (1) Update the peer delay D and clock offset Offset after each message exchange;

[0131] (2) Use a sliding window (e.g., the last 10 calculations) to smooth the data and reduce the impact of instantaneous jitter.

[0132] 3. Threshold judgment:

[0133] (1) Peer delay threshold (e.g., D > 1ms): network congestion or hardware anomaly;

[0134] (2) Clock offset threshold (e.g., ∣Offset∣ > 10μs): clock cumulative error exceeds the limit;

[0135] (3) If any index exceeds the threshold, trigger a switch evaluation.

[0136] As an alternative implementation, after detecting the program running status of the first synchronization program, the method further includes:

[0137] When it is indicated that the first synchronization program is in a fault state during the program running state, release the clock signal synchronization relationship of the first synchronization program with the network device, and establish the clock signal synchronization relationship of the second synchronization program with the network device, where the network device is used to execute the to-be-run service through the clock signal synchronized by the second synchronization program.

[0138] Optionally, in the embodiment of the present application, when the first synchronization program is in a fault state, the program is switched through the following steps: S1: Immediately freeze the update mechanism of the first synchronization program to prevent incorrect time information from further affecting system operations; S2: Send a notification to the system resource manager, requesting to release the SR-IOV virtual function (VF) and other related resources allocated to the first synchronization program to prepare for the startup of the second synchronization program; S3: Start the second synchronization program to ensure that it can normally receive and process time synchronization requests; S4: The client performs a protocol handshake with the second synchronization program to establish the synchronization relationship of the second synchronization program; S5: Obtain the difference between the first clock signal of the current first synchronization program and the second clock signal of the second synchronization program as the initial reference value for clock signal deviation compensation; S6: Apply the time deviation compensation algorithm to ensure that when switching from the first synchronization program to the second synchronization program, the clock signal of the network device can transition smoothly, avoiding service interruption or data inconsistency caused by protocol switching; S6: Update the system state, indicating that the second synchronization program is currently used as the time synchronization source, and record the switching event and reason for subsequent analysis and optimization reference.

[0139] Through the above method, the dynamic switching mechanism ensures that even when the first synchronization program fails, the system can maintain the basic time synchronization function through the backup time synchronization scheme (the second synchronization program), enhancing the overall robustness and continuous operation ability of the system.

[0140] As an optional implementation manner, after releasing the clock signal synchronization relationship of the first synchronization program with the network device and establishing the clock signal synchronization relationship of the second synchronization program with the network device, the method further includes:

[0141] Perform a fault maintenance operation on the first synchronization program to obtain a third synchronization program;

[0142] Detect the target running state of the third synchronization program;

[0143] When the target running state is used to indicate that there is no clock signal deviation in the clock signal synchronized by the third synchronization program for the network device, release the clock signal synchronization relationship of the second synchronization program with the network device, and establish the clock signal synchronization relationship of the third synchronization program with the network device, where the network device is used to execute the to-be-run service through the clock signal synchronized by the third synchronization program.

[0144] Optionally, in an embodiment of the present application, after the first synchronization program fails and switches to the second synchronization program, a fault maintenance operation will be immediately performed on the first synchronization program to ensure that the network device can always use the optimal clock signal to execute the pending business. After switching to the second synchronization program, the system should immediately start the fault diagnosis process to analyze the specific cause of the failure of the first synchronization program, such as hardware failure, software bug, network anomaly, etc., and then perform corresponding repair measures according to the fault diagnosis results, such as replacing the faulty hardware, upgrading the software version, or optimizing the network configuration.

[0145] Optionally, in an embodiment of the present application, the third synchronization program may be the repaired first synchronization program, or may be another clock synchronization program with higher clock accuracy, which is not limited in this solution.

[0146] Optionally, in an embodiment of the present application, after the third synchronization program is started, real-time status monitoring is performed on it, which may include but is not limited to parameters such as peer delay, clock offset, hardware resource status, etc., to evaluate its operating effect; only when the target operating status of the third synchronization program shows that it can provide an unbiased clock signal and is significantly better than the second synchronization program in terms of synchronization accuracy and stability, will the switch from the second synchronization program to the third synchronization program be triggered; the system will release the clock signal synchronization relationship between the second synchronization program and the network device, release the resources occupied by the second synchronization program, and then construct the clock signal synchronization relationship between the third synchronization program and the network device, to ensure the continuity of the time signal and uninterrupted business in this process.

[0147] Through the above method, the system can not only respond quickly and overcome synchronization program failures, but also automatically find and implement the optimal clock synchronization solution after recovery, which significantly improves the overall performance and reliability of the time synchronization system. For business environments that rely on high-precision time synchronization, it has extremely important significance and obvious implementation effects.

[0148] As an optional implementation manner, before detecting the program running state of the first synchronization program, the method further includes:

[0149] Obtaining the amount of running resources required when the first synchronization program is running;

[0150] Allocating a target running area for the first synchronization program from the target network card according to the running resource amount, wherein the target network card is used to provide the running resources required for the clock synchronization program to run;

[0151] The first synchronization program is deployed in the target operation area, and an association relationship between the target operation area and the network device is established.

[0152] Optionally, in the embodiments of the present application, before detecting the program running status of the first synchronization program, it is necessary to pre-determine the amount of running resources required during the operation of the first synchronization program, such as the number of CPU cores, memory size, dedicated network interface, etc.; according to the determined resource requirements, select a target network card that can meet the running conditions of the first synchronization program, and through the SR-IOV technology, divide a sufficient number of virtual functions (VFs) from the target network card as the target running area, which is dedicated to the operation of the PTP protocol to avoid resource conflicts with other applications; deploy the first synchronization program to the previously allocated target running area to ensure that it can directly utilize the hardware resources in this area for timestamp capture and data transmission; the system manager establishes an association relationship between the target running area and the network device, enabling the network device to access the first synchronization program through the VF in this area to achieve high-precision time synchronization.

[0153] Through the above method, the system can ensure the stable operation of the first synchronization program when there are sufficient hardware resources, significantly reduce network latency and time offset, and enhance the accuracy and reliability of overall time synchronization. At the same time, through the clear division of resources, the deployment process is simplified, which provides convenience for subsequent maintenance and switching operations, and improves the performance and time accuracy of network devices when executing critical services.

[0154] As an optional implementation manner, the present application also provides a PTP / NTP dynamic switching high-precision time synchronization system and method, including:

[0155] 1. Dynamic switching engine: Real-time monitor network latency, hardware status and user policies, and trigger protocol switching;

[0156] 2. SR-IOV hardware acceleration: Provide exclusive virtual functions (VFs) for PTP to isolate clock traffic;

[0157] 3. Seamless transition algorithm: Maintain clock continuity through time deviation compensation during switching;

[0158] 4. Hybrid timing architecture: Support the collaborative work of PTP and NTP, and the priority is configurable.

[0159] I. Embodiment 1: System initialization and hardware configuration:

[0160] 1. SR-IOV network card virtualization:

[0161] The physical function (PF) is divided into multiple VFs, and at least 1 VF is dedicated to PTP traffic;

[0162] Bind the VF to the PTP master clock service through the PCIe Passthrough technology;

[0163] Enable the hardware timestamp function with precision calibrated to the nanosecond level.

[0164] 2. Dual-Stack Deployment:

[0165] The PTP service runs on the SR-IOV VF, and the NTP service is bound to the ordinary network card port;

[0166] The client preloads the PTP / NTP dual stack and defaults to PTP with high priority.

[0167] II. Example 2: Dynamic Switching Process:

[0168] 1. Monitoring Phase:

[0169] Continuously collect the status of the SR-IOV network card (such as DMA latency, packet loss rate);

[0170] Calculate the path delay (Peer Delay) and clock offset (Offset) of the PTP path;

[0171] If the PTP path delay > 1ms or the clock offset > 10μs, trigger the handover evaluation.

[0172] 2. Handover Decision:

[0173] If the SR-IOV network card fails, immediately switch to NTP;

[0174] If network fluctuations cause a decline in PTP performance, start the "PTP + NTP" hybrid mode to compensate for long-term deviations with NTP;

[0175] Users can forcefully specify the protocol through the API.

[0176] 3. Seamless Handover Execution:

[0177] Step 1: Freeze the PTP clock update and record the current PTP time T p ;

[0178] Step 2: Obtain the time T from the NTP server n , calculate the deviation ΔT = T p - T n ;

[0179] Step 3: The client clock converges to the NTP time gradually with ΔT as the initial offset;

[0180] Step 4: Release the SR-IOV VF resources for reuse by other virtual machines.

[0181] III. Example 3: Hybrid Timing Mode:

[0182] Master-slave collaboration: PTP is responsible for high-frequency synchronization (1000 times per second), and NTP corrects the cumulative error every 60 seconds;

[0183] Fault fallback: When the PTP interruption exceeds 5 seconds, the client automatically locks NTP as the only source.

[0184] The technical key points of this solution are as follows:

[0185] 1. Hardware virtualization and resource isolation of SR-IOV network cards:

[0186] Divide the physical function (PF) of the SR-IOV network card into multiple virtual functions (VFs), where at least one VF is dedicated to the PTP protocol, and bind it to the PTP master clock service through PCIe Passthrough technology to achieve hardware timestamp and traffic isolation, ensuring that the PTP synchronization accuracy reaches ±100 nanoseconds.

[0187] The DMA channels and interrupt mechanisms of the VFs are independently configured to avoid competing for resources with other virtual machines or applications; the hardware timestamp is directly generated inside the network card chip, bypassing the operating system protocol stack delay.

[0188] 2. Dynamic switching decision engine:

[0189] Trigger protocol switching based on multi-dimensional conditions:

[0190] Hardware status: The DMA latency of the SR-IOV network card > 500 μs, packet loss rate > 1%;

[0191] Network performance: PTP path latency > 1 ms or clock offset > 10 μs;

[0192] User policy: Manually specify the protocol priority or switching timing.

[0193] Algorithm implementation: Use the sliding window algorithm to statistically analyze historical network metrics and combine the Bayesian decision model to evaluate the switching risk.

[0194] 3. Seamless time transition and deviation compensation:

[0195] When switching, maintain time continuity through the following steps:

[0196] Freeze the PTP clock and record the current time T p ;

[0197] Obtain the NTP time T n , calculate the deviation ΔT = T p -T n ;

[0198] The client uses ΔT as the initial offset and gradually converges to the NTP time through the PID controller (convergence time < 500 ms).

[0199] 4. Hybrid time synchronization mode of PTP and NTP:

[0200] Collaboration mechanism: PTP is responsible for high-frequency synchronization (1kHz), and NTP corrects the cumulative error every 60 seconds;

[0201] Fault fallback: If the PTP interruption exceeds 5 seconds, the client automatically switches to the NTP exclusive mode.

[0202] The core invention points of this solution include the following aspects:

[0203] (1) A PTP / NTP dynamic switching time synchronization system based on an SR-IOV network card, including:

[0204] A network card supporting SR-IOV virtualization, at least one virtual function (VF) of which is configured to be dedicated to PTP protocol transmission;

[0205] A protocol control module for running PTP master clock service, NTP service and switching decision logic;

[0206] A client device with a built-in PTP / NTP dual protocol stack, capable of receiving switching instructions and switching clock sources.

[0207] (2) The triggering conditions of the switching decision logic include:

[0208] The DMA delay of the SR-IOV network card exceeds the preset threshold;

[0209] The clock offset of the PTP path exceeds 10 microseconds;

[0210] The user issues a forced switching instruction through the API or the management interface.

[0211] (3) The virtual function (VF) resource allocation method of the SR-IOV network card includes:

[0212] In the PTP active state, the VF is exclusive for timestamp generation and PTP message transmission;

[0213] After switching to NTP, the VF resources are released and reallocated to other virtual machines or applications.

[0214] The seamless time transition method as described in the aforementioned system includes:

[0215] Calculate the time deviation ΔT between PTP and NTP;

[0216] The client uses a PID control algorithm to smoothly migrate the local clock from PTP time to NTP time.

[0217] (4)A PTP / NTP dynamic switching time synchronization method, comprising the following steps:

[0218] Initialize the SR-IOV network card, allocate a dedicated VF for PTP and enable the hardware timestamp;

[0219] Real-time monitor network latency, clock offset and hardware health status;

[0220] When the switching condition is met, freeze the current protocol clock and start deviation compensation;

[0221] After completing the protocol handshake, switch to the target protocol and release or apply for hardware resources.

[0222] Figure 3 It is a system architecture diagram of a PTP / NTP dynamic switching time synchronization system based on an SR-IOV network card according to an embodiment of the present application, as Figure 3 shown, the system includes:

[0223] SR-IOV network card: Allocate a dedicated VF for PTP to achieve hardware timestamp and traffic isolation;

[0224] Protocol control layer: Includes a PTP master clock, an NTP server and a switching decision module;

[0225] Monitoring module: Collect network jitter, clock offset and hardware health status;

[0226] Client: Supports dual protocol stacks, receives synchronization instructions and switches clock sources, and includes a PTP high-precision network, a PTP backup clock and an NTP client.

[0227] Figure 4 It is a flowchart of protocol switching trigger conditions according to an embodiment of the present application, as Figure 4 shown, the trigger conditions include: SR-IOV network card failure, network latency exceeding the threshold, user manual switching; Figure 5 It is a flowchart of the protocol switching process according to an embodiment of the present application, as Figure 5 shown, the switching process includes three stages: clock deviation calculation, resource release / request, and protocol handshake.

[0228] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0229] An embodiment of the present application also provides a compensation device for clock signals, Figure 6 It is a structural block diagram of a compensation device for clock signals according to an embodiment of the present application, as Figure 6As shown, the device includes:

[0230] A first detection module 602, configured to detect the program running state of the first synchronization program;

[0231] A generation module 604, configured to generate a clock compensation parameter for the first synchronization program according to the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, and obtain a target deviation parameter of the first synchronization program when the program running state is used to indicate that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device. Herein, the clock synchronization accuracy of the first synchronization program is higher than that of the second synchronization program, and the target deviation parameter is used to indicate the influence relationship of the clock signal synchronization method currently adopted by the first synchronization program to synchronize the clock signal for the network device on the clock signal deviation amount;

[0232] A compensation module 606, configured to compensate the first clock signal according to the clock compensation parameter and the target deviation parameter to obtain a target clock signal, where the network device is used to execute the to-be-run service using the target clock signal.

[0233] With the above device, by setting two synchronization programs with different synchronization accuracies to synchronize the clock signal for the network device, where the program with a higher clock synchronization accuracy is used as the first synchronization program and the program with a lower clock synchronization accuracy is used as the second synchronization program, first, the program running state of the first synchronization program is detected. When the program running state of the first synchronization program is used to indicate that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device, a clock compensation parameter for the first synchronization program is generated according to the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, and a target deviation parameter for indicating the influence relationship of the clock signal synchronization method currently adopted by the first synchronization program to synchronize the clock signal for the network device on the clock signal deviation amount is obtained. Then, the first clock signal is compensated according to the clock compensation parameter and the target deviation parameter to obtain a target clock signal, thereby ensuring the accuracy of the clock signal synchronized for the network device. Furthermore, the network device can use the target clock signal with higher accuracy to execute the to-be-run service. Therefore, the technical problem of low time synchronization efficiency for the network device in the related art can be solved, and the technical effect of improving the time synchronization efficiency for the network device can be achieved.

[0234] Optionally, the compensation module includes:

[0235] A conversion unit, configured to convert the target deviation parameter into a weight parameter of an initial clock compensation amount, where the clock compensation parameter includes the initial clock compensation amount, and the initial clock compensation amount is used to indicate the difference situation between the first clock signal and the second clock signal;

[0236] A first calculation unit, configured to perform weighted calculation on an initial clock compensation amount by using weight parameters to obtain a target clock compensation amount;

[0237] A compensation unit, configured to compensate a first clock signal by using the target clock compensation amount to obtain a target clock signal.

[0238] Optionally, the conversion unit is further configured to:

[0239] calculate the weight parameters through the following formula:

[0240] ;

[0241] where W is the weight parameter, C is the target deviation parameter, and C0 is a preset threshold.

[0242] Optionally, the generation module includes:

[0243] An acquisition unit, configured to acquire the reference operation information of each reference moment among multiple reference moments before the current moment of a first synchronization program and the reference deviation amount of the clock signal synchronized by the first synchronization program at the corresponding reference moment, where the reference operation information is used to indicate the clock signal synchronization method when the first synchronization program synchronizes the clock signal for the network device at the reference moment;

[0244] A generation unit, configured to generate a target deviation parameter according to the reference operation information and the reference deviation amount.

[0245] Optionally, the generation unit is further configured to:

[0246] in a case where the reference operation information includes sub-operation information of multiple information types, generate an initial deviation parameter corresponding to the sub-operation information of the current information type according to the sub-operation information of multiple reference moments of the same information type and the reference deviation amounts of multiple reference moments, where the sub-operation information of multiple information types is used to characterize the clock signal synchronization method when the first synchronization program synchronizes the clock signal for the network device in multiple information dimensions;

[0247] merge the initial deviation parameters of the sub-operation information of multiple information types into a target deviation parameter.

[0248] Optionally, the generation unit is further configured to:

[0249] calculate the initial deviation parameter corresponding to the sub-operation information of the current information type through the following formula:

[0250] ;

[0251] where is the initial deviation parameter corresponding to the sub-operation information of the current information type, is the reference deviation amount at time t, is the reference deviation at time t-i, is the first coefficient, is the second coefficient, is the third coefficient, is the sub-operation information of the current information type at time t-j.

[0252] Optionally, the generating unit is further configured to:

[0253] Sum multiple initial deviation parameters to obtain a target deviation parameter.

[0254] Optionally, the generating module further includes:

[0255] A second calculation unit for calculating the difference between the first clock signal and the second clock signal to obtain a target clock difference;

[0256] A first determination unit for determining the target clock difference as the initial clock compensation amount for the clock signal synchronized by the first synchronization program, where the clock compensation parameter includes the initial clock compensation amount.

[0257] Optionally, the first detection module includes:

[0258] A detection unit for detecting the current peer delay of the first synchronization program and detecting the clock offset;

[0259] A second determination unit for determining that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device when the peer delay is greater than or equal to the first threshold and the clock offset is greater than or equal to the second threshold.

[0260] Optionally, the device further includes:

[0261] A first construction module for, after detecting the program running state of the first synchronization program, in the case where the program running state indicates that the first synchronization program is in a fault state, releasing the clock signal synchronization relationship of the first synchronization program for the network device and constructing a clock signal synchronization relationship of the second synchronization program for the network device, where the network device is used to execute the to-be-run service through the clock signal synchronized by the second synchronization program.

[0262] Optionally, the device further includes:

[0263] An execution module for, after releasing the clock signal synchronization relationship of the first synchronization program for the network device and constructing a clock signal synchronization relationship of the second synchronization program for the network device, performing a fault maintenance operation on the first synchronization program to obtain a third synchronization program;

[0264] A second detection module for detecting the target running state of the third synchronization program;

[0265] A second construction module, configured to, when there is no clock signal deviation in the clock signal synchronized by the third synchronization program for the network device in the target operating state, release the clock signal synchronization relationship of the second synchronization program for the network device, and construct the clock signal synchronization relationship of the third synchronization program for the network device, where the network device is used to execute the to-be-operated service by the clock signal synchronized by the third synchronization program.

[0266] Optionally, the apparatus further includes:

[0267] An acquisition module, configured to acquire the amount of operating resources required during the operation of the first synchronization program;

[0268] An allocation module, configured to allocate a target operating area for the first synchronization program from the target network card according to the amount of operating resources, where the target network card is used to provide the operating resources required for the operation of the clock synchronization program;

[0269] A third construction module, configured to deploy the first synchronization program in the target operating area and construct the association relationship between the target operating area and the network device.

[0270] For the description of the features in the corresponding embodiment of the clock signal compensation apparatus, reference may be made to the relevant description in the corresponding embodiment of the clock signal compensation method, which will not be elaborated here one by one.

[0271] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above embodiments of the clock signal compensation method.

[0272] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, where the computer program is configured to execute the steps in any one of the above embodiments of the clock signal compensation method when running.

[0273] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0274] An embodiment of the present application further provides a computer program product, where the computer program product includes a computer program, and the computer program implements the steps in any one of the above embodiments of the clock signal compensation method when executed by a processor.

[0275] Embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps in any of the above-described embodiments of the clock signal compensation method.

[0276] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0277] The above has introduced in detail a clock signal compensation method provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for compensating a clock signal, characterized in that Including: Detecting the program running state of the first synchronization program; When the program running state is used to indicate that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device, generating a clock compensation parameter for the first synchronization program according to the first clock signal and the second clock signal synchronized by the second synchronization program for the network device, and obtaining a target deviation parameter of the first synchronization program, where the clock synchronization accuracy of the first synchronization program is higher than that of the second synchronization program, and the target deviation parameter is used to indicate the influence relationship of the clock signal synchronization method currently adopted by the first synchronization program for synchronizing the clock signal for the network device on the clock signal deviation amount; Compensating the first clock signal according to the clock compensation parameter and the target deviation parameter to obtain a target clock signal, where the network device is used to execute the to-be-run service using the target clock signal.

2. The method according to claim 1, wherein: The compensating the first clock signal according to the clock compensation parameter and the target deviation parameter to obtain a target clock signal includes: Converting the target deviation parameter into a weight parameter of an initial clock compensation amount, where the clock compensation parameter includes the initial clock compensation amount, and the initial clock compensation amount is used to indicate the difference situation between the first clock signal and the second clock signal; Performing weighted calculation on the initial clock compensation amount using the weight parameter to obtain a target clock compensation amount; Compensating the first clock signal using the target clock compensation amount to obtain the target clock signal.

3. The method according to claim 2, wherein: Calculating the weight parameter through the following formula: ； Where W is the weight parameter, C is the target deviation parameter, and C0 is a preset threshold.

4. The method according to claim 1, wherein: The obtaining the target deviation parameter of the first synchronization program includes: Obtaining the reference running information of each reference moment among multiple reference moments before the current moment of the first synchronization program and the reference deviation amount of the clock signal synchronized by the first synchronization program at the corresponding reference moment, where the reference running information is used to indicate the clock signal synchronization method when the first synchronization program synchronizes the clock signal for the network device at the reference moment; Generating the target deviation parameter according to the reference running information and the reference deviation amount.

5. The method according to claim 4, wherein: The generating the target deviation parameter according to the reference running information and the reference deviation amount includes: When the sub - run information of multiple information types is included in the reference run information, an initial deviation parameter corresponding to the sub - run information of the current information type is generated according to the sub - run information of multiple reference times of the same information type and the reference deviation amounts of multiple reference times, where the sub - run information of multiple information types is used to characterize the clock signal synchronization method when the first synchronization program synchronizes the clock signal for the network device in multiple information dimensions; The initial deviation parameters of the sub - run information of multiple information types are combined into the target deviation parameter.

6. The method according to claim 5, wherein: The initial deviation parameter corresponding to the sub - run information of the current information type is calculated by the following formula: ； wherein, is the initial deviation parameter corresponding to the sub-operation information of the current information type; is the reference deviation at time t; is the reference deviation at time t-i; is the first coefficient; is the second coefficient; is the third coefficient; is the sub-operation information of the current information type at time t-j.

7. The method according to claim 5, wherein: The combining of the initial deviation parameters of the sub - run information of multiple information types into the target deviation parameter includes: Performing a summation calculation on multiple initial deviation parameters to obtain the target deviation parameter.

8. The method according to claim 1, wherein: Generating a clock compensation parameter for the first synchronization program according to the first clock signal and the second clock signal synchronized by the second synchronization program for the network device includes: Calculating the difference between the first clock signal and the second clock signal to obtain a target clock difference; Determining the target clock difference as the initial clock compensation amount for the clock signal synchronized by the first synchronization program, where the clock compensation parameter includes the initial clock compensation amount.

9. The method according to claim 1, wherein: Detecting the program running state of the first synchronization program includes: Detecting the current peer - to - peer delay of the first synchronization program and detecting the clock offset; When the peer - to - peer delay is greater than or equal to a first threshold and the clock offset is greater than or equal to a second threshold, it is determined that there is a clock signal deviation in the first clock signal synchronized by the first synchronization program for the network device.

10. The method according to claim 1, wherein: After detecting the program running state of the first synchronization program, the method further includes: When the program running state is used to indicate that the first synchronization program is in a fault state, releasing the clock signal synchronization relationship of the first synchronization program for the network device and constructing the clock signal synchronization relationship of the second synchronization program for the network device, where the network device is used to execute the to - be - run service through the clock signal synchronized by the second synchronization program.

11. The method according to claim 10, wherein: After releasing the clock signal synchronization relationship of the first synchronization program for the network device and constructing the clock signal synchronization relationship of the second synchronization program for the network device, the method further includes: Performing a fault maintenance operation on the first synchronization program to obtain a third synchronization program; Detecting the target running state of the third synchronization program; When the clock signal deviation does not exist in the clock signal synchronized by the third synchronization program for the network device in the target operating state, the second synchronization program is released from the clock signal synchronization relationship with the network device, and the third synchronization program is established for the clock signal synchronization relationship with the network device, where the network device is used to execute the to-be-operated service through the clock signal synchronized by the third synchronization program.

12. The method according to claim 11, wherein Before detecting the program operating state of the first synchronization program, the method further includes: Obtaining the amount of operating resources required during the operation of the first synchronization program; Allocating a target operating area for the first synchronization program from a target network card according to the amount of operating resources, where the target network card is used to provide operating resources required for the operation of the clock synchronization program; Deploying the first synchronization program in the target operating area and establishing an association relationship between the target operating area and the network device.

13. An electronic device, characterized in that, including: A memory for storing computer programs; A processor for implementing the steps of the clock signal compensation method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the clock signal compensation method according to any one of claims 1 to 12.

15. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the clock signal compensation method according to any one of claims 1 to 12.

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