Image acquisition method and imaging system based on double-sided array visible light detector

Abstract

The application relates to the field of image processing, and provides an image acquisition method based on a double-surface-array visible light detector and an imaging system.The method comprises the following steps: determining a first frame valid signal of a first half area of the double-surface-array visible light detector and determining a second frame valid signal of a second half area; performing shaping on the second frame valid signal, then performing OR operation on the first frame valid signal and the second frame valid signal to determine a third frame valid signal, the third frame valid signal is set to a high level when dark rows in the first half area are read out, and is set to a low level after effective row reading in the second half area is completed; and based on the third frame valid signal, the double-surface-array visible light detector is controlled to perform image acquisition.The application can solve the defect that the real-time requirement cannot be met when the double-surface-array visible light detector is applied to image acquisition in the related art, and the frame valid signals of two subareas of the detector are integrated in the scheme, so that the images of the two half areas are exposed at the same time, and the real-time requirement is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, and in particular to an image acquisition method based on a double-surface array visible light detector and an imaging system. BACKGROUND

[0002] The visible light detector includes a single-surface array and a double-surface array, wherein the single-surface array visible light detector often faces signal loss, noise interference and imaging speed bottleneck when improving image resolution and dynamic range, which affects the image quality and limits the performance of real-time applications, and the double-surface array visible light detector arranges pixel arrays on the upper and lower sides, and the signal acquisition and processing of the upper and lower halves can be performed in parallel. This design effectively reduces signal loss and interference and significantly improves imaging speed, and is particularly suitable for real-time imaging applications that require fast processing.

[0003] When the double-surface array visible light detector is applied to the field of hyperspectral cameras, etc., due to filter manufacturing errors or film pasting process errors, the upper and lower halves of the visible light detector will be required to be windowed, i.e., the effective image areas of the upper and lower halves are set, and the scales are inconsistent, and the upper and lower halves cannot be collected at the same time. For this situation, the processing methods in the related art include two kinds, the first kind is to store one frame of image data of the upper and lower halves into an external large-capacity storage chip such as DDR3, and then read out in sequence. The second method is to configure the visible light detector to realize alternate exposure of the upper and lower halves and read out in sequence.

[0004] Both of the above two implementation methods have their own disadvantages, the first method has complex hardware design and high power consumption, and adding a DDR3 chip will greatly increase the power consumption of the entire system, and the second method cannot expose the upper and lower halves at the same time, which causes the images of the upper and lower halves to be not real-time synchronized, and cannot meet the real-time requirement. SUMMARY

[0005] The present application provides an image acquisition method based on a double-surface array visible light detector and an imaging system, to solve the defect that the real-time requirement cannot be met when the double-surface array visible light detector is applied to image acquisition in the related art, in the scheme of the present application, the frame effective signals of the two partitions of the detector are integrated, the images of the two halves are exposed at the same time, the real-time requirement is met, and no additional hardware design is required, and the power consumption is reduced.

[0006] The present application provides an image acquisition method based on a double-surface array visible light detector, comprising:

[0007] determining a first frame effective signal of a first half of the double-surface array visible light detector, and determining a second frame effective signal of a second half;

[0008] After shaping the second frame valid signal, the first frame valid signal and the second frame valid signal are subjected to OR operation to determine a third frame valid signal, the third frame valid signal being set to high level when the dark row in the first half area is read out, and being set to low level after the valid row in the second half area is read out;

[0009] Based on the third frame valid signal, the double-sided array visible light detector is controlled to perform image acquisition;

[0010] The shaping of the second frame valid signal comprises:

[0011] The dark row counting is performed at the rising edge of the second frame valid signal, and the second frame valid signal to be shaped is set to low level;

[0012] During image acquisition, the second frame valid signal to be shaped is set to high level.

[0013] According to the image acquisition method based on the double-sided array visible light detector provided by the application, the determination of the first frame valid signal of the first half area of the double-sided array visible light detector and the determination of the second frame valid signal of the second half area comprise:

[0014] The first valid row number, the first invalid row number of the first half area of the double-sided array visible light detector and the second valid row number of the second half area are determined;

[0015] Based on the first valid row number and the first invalid row number, the second invalid row number of the second half area of the double-sided array visible light detector is determined;

[0016] The first valid row number, the first invalid row number, the second valid row number and the second invalid row number are input into the double-sided array visible light detector, and the first frame valid signal and the second frame valid signal output by the double-sided array visible light detector are acquired.

[0017] According to the image acquisition method based on the double-sided array visible light detector provided by the application, the determination of the first valid row number and the first invalid row number of the first half area of the double-sided array visible light detector comprises:

[0018] The first starting row, the first ending row and the first dark row of the first half area of the double-sided array visible light detector are acquired;

[0019] Based on the first starting row and the first ending row, the first valid row number is calculated;

[0020] Based on the first dark row, the first invalid row number is calculated.

[0021] According to the application, the image acquisition method based on the double-sided array visible light detector comprises the following steps:

[0022] The first effective row number and the first invalid row number are summed to obtain the second invalid row number of the second half area.

[0023] According to the application, the image acquisition method based on the double-sided array visible light detector comprises the following steps:

[0024] The maximum dark row number of the second half area of the double-sided array visible light detector is obtained.

[0025] The second dark row of the second half area is modified based on the size relationship between the maximum dark row number and the second invalid row number.

[0026] The dark row counting is performed based on the modified second dark row.

[0027] According to the application, the image acquisition method based on the double-sided array visible light detector comprises the following steps:

[0028] If the second invalid row number is greater than the maximum dark row number of the second half area, the second dark row is modified to the maximum dark row number.

[0029] If the second invalid row number is less than or equal to the maximum dark row number of the second half area, the second dark row is modified to the second invalid row number.

[0030] The application further provides an image acquisition system based on a double-sided array visible light detector, comprising:

[0031] A signal acquisition unit is configured to determine a first frame effective signal of a first half area of a double-sided array visible light detector and determine a second frame effective signal of a second half area.

[0032] A signal processing unit is configured to perform shaping on the second frame effective signal, perform or operation on the first frame effective signal and the second frame effective signal to determine a third frame effective signal, and set the third frame effective signal to a high level when a dark row of the first half area is read out and set the third frame effective signal to a low level after effective row reading of the second half area is completed.

[0033] An image acquisition unit is configured to control the double-sided array visible light detector to perform image acquisition based on the third frame effective signal.

[0034] The signal processing unit is further configured to:

[0035] The dark line counting is performed at the rising edge of the second frame valid signal, and the second frame valid signal to be shaped is set to low level;

[0036] The second frame valid signal to be shaped is set to high level during image acquisition.

[0037] The application further provides a real-time imaging system based on the dual-face array visible light detector, comprising:

[0038] The control chip comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the above-mentioned any one of the image acquisition systems based on the dual-face array visible light detector when executing the program.

[0039] The dual-face array visible light detector comprises a first half region and a second half region.

[0040] The image display device is used for imaging the image acquired by the dual-face array visible light detector.

[0041] The application further provides a non-transient computer readable storage medium, which stores a computer program, and the computer program is executed by the processor to implement the above-mentioned any one of the image acquisition systems based on the dual-face array visible light detector.

[0042] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by the processor to implement the above-mentioned any one of the image acquisition systems based on the dual-face array visible light detector.

[0043] The image acquisition method based on the dual-face array visible light detector provided by the application can acquire the frame valid signals of two sub-regions of the dual-face array visible light detector respectively, and the two frame valid signals are operated through or operation after shaping, so that the frame valid signals of the two sub-regions are changed from the state of independent control to the state of synchronization, and then the two sub-regions can realize synchronous image exposure, pseudo single-face array operation is realized, the disadvantages that the two sub-regions cannot be exposed at the same time due to the asynchronization of the frame valid signals of the two sub-regions are avoided, and the synchronization requirement in the application of the visible light detector for image acquisition is met. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0045] Figure 1 is a flow block diagram of an image acquisition method provided by an embodiment of the present application;

[0046] Figure 2 is an array composition block diagram of a double-sided array visible light detector provided by an embodiment of the present application;

[0047] Figure 3 is a structural schematic diagram of an image acquisition system provided by an embodiment of the present application;

[0048] Figure 4 is a structural schematic diagram of a real-time imaging system provided by an embodiment of the present application;

[0049] Figure 5 is a connection relationship schematic diagram of a detector and a control chip provided by an embodiment of the present application;

[0050] Figure 6 is a flow structure diagram of an image acquisition method provided by an embodiment of the present application;

[0051] Figure 7 is a timing diagram of an image acquisition method provided by an embodiment of the present application;

[0052] Figure 8 is a physical structure schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, but not all embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0054] Figure 1 is a flow block diagram of an image acquisition method provided by an embodiment of the present application.

[0055] As shown in Figure 1 , the present embodiment provides an image acquisition method based on a double-sided array visible light detector, which comprises:

[0056] Step 101, determining a first frame of valid signals of a first half area of the double-sided array visible light detector, and determining a second frame of valid signals of a second half area;

[0057] In actual application, the double-sided array visible light detector can comprise the first half area and the second half area, and the first half area and the second half area are independently controlled and independently operated, wherein the first half area can be referred to as a TOP half area, and the second half area can be referred to as a BOTTOM half area.

[0058] An exemplary model of the dual-side array visible light detector in the embodiment can be CIS2521F.

[0059] Since the first half region and the second half region work independently, the first frame valid signal of the first half region and the second frame valid signal of the second half region can be obtained in the embodiment. The frame valid signal (FVAL) is a control signal used to indicate whether a certain frame of image data is valid. For example, during image transmission, if a certain frame of image data is being transmitted, the frame valid signal is at a high level, representing that the frame of image data is valid. If the frame valid signal is at a low level, it represents that the frame of data is ended or the frame of image data is invalid.

[0060] In step 102, after the second frame valid signal is shaped, the first frame valid signal and the second frame valid signal are subjected to OR operation to determine a third frame valid signal. The third frame valid signal is at a high level when the dark row of the first half region is read out, and is at a low level after the valid row of the second half region is read out.

[0061] The shaping of the second frame valid signal includes:

[0062] The dark row counting is performed at the rising edge of the second frame valid signal, and the second frame valid signal to be shaped is set to a low level.

[0063] During image acquisition, the second frame valid signal to be shaped is set to a high level.

[0064] The OR operation belongs to a kind of Boolean operation, and its core rule is that as long as one of the operands is true (1), the result is true (1). Only when all the operands are false (0), the result is false (0).

[0065] In actual application, after the first frame valid signal and the second frame valid signal are subjected to OR operation, the final single-side array frame valid signal can be obtained. This signal can be pulled high when the dark row of the first half region is read out, and can be pulled low after the valid image data row of the second half region is read out, so as to realize seamless connection of the valid image data row read out of the first half region and the second half region.

[0066] In actual application, after the first frame valid signal and the second frame valid signal of the dual-face array visible light detector are obtained, the frame valid signals of the two half regions can be integrated. Specifically, the frame valid signal of the visible light detector is generally pulled high during physical row reading, that is, pulled high during reading of dark rows and valid image rows, and pulled low during reading of pre-scanning rows. In this step, the frame valid signal of the second half region is shaped to be pulled high only during reading of the valid image rows of the second half region, and thus the dark row counting is required. First, the second dark row number of the second half region is determined. If the second invalid row number of the second half region is greater than the maximum dark row number, the second dark row number of the second half region is modified to the maximum dark row number, otherwise the second dark row number is modified to the second invalid row number. When the rising edge of the second frame valid signal arrives, the dark row counting is started through the row valid signal, and the frame valid signal to be shaped is pulled low. When the valid image data is output, the frame valid signal to be shaped is continuously pulled high until the reading of the valid image data is completed.

[0067] In step 103, the third frame valid signal is used to control the dual-face array visible light detector to collect image data.

[0068] Specifically, the third frame valid signal obtained through calculation is used to screen the image data collected by the dual-face array visible light detector, and the image data not meeting the third frame valid signal is removed.

[0069] In the image collection method based on the dual-face array visible light detector provided in this embodiment, the frame valid signals of the two half regions of the dual-face array visible light detector can be obtained respectively, and the two frame valid signals are shaped and then ORed, so that the frame valid signals of the two half regions are changed from the state of independent control to the state of synchronization, and then the two half regions can be synchronously collected at the same time, pseudo-single-face array operation is realized, and the problem that the two half regions cannot be exposed at the same time due to the asynchronization of the frame valid signals of the two half regions is avoided, and the synchronization requirement in the application of the visible light detector to collect image data is met.

[0070] In the example embodiment, the determination of the first frame valid signal of the first half region and the second frame valid signal of the second half region of the dual-face array visible light detector comprises:

[0071] The first valid row number, the first invalid row number of the first half region, and the second valid row number of the second half region of the dual-face array visible light detector are determined.

[0072] The second invalid row number of the second half region of the dual-face array visible light detector is determined based on the first valid row number and the first invalid row number.

[0073] The first valid row count, the first invalid row count, the second valid row count, and the second invalid row count are input into the dual-array visible light detector, and the first frame valid signal and the second frame valid signal output by the dual-array visible light detector are obtained.

[0074] The step of determining the first effective row number and the first invalid row number of the first half-region of the dual-array visible light detector includes:

[0075] Obtain the first start line, the first end line, and the first dark line of the first half-region of the dual-array visible light detector;

[0076] Based on the first starting row and the first ending row, the number of the first valid rows is calculated;

[0077] Based on the first hidden line, the number of the first invalid lines is calculated.

[0078] In practical applications, the array of a dual-array visible light detector typically includes invalid rows with a configurable number of readout rows. These invalid rows include dark rows and pre-scan rows. Dark rows are a fixed array of several rows from which no real image can be acquired. Pre-scan rows are virtual, read out before the dark rows, and are used to configure the readout timing; their configurable number is often much larger than the number of valid image data rows. In this step, the number of the first valid rows in the first half of the detector is calculated based on the serial port configuration data, and the number of the first invalid rows in the first half of the detector is determined.

[0079] Figure 2 This is a block diagram of the array composition of a dual-array visible light detector provided in an embodiment of the present invention.

[0080] like Figure 2 As shown, the image data for each half-area of ​​the dual-array visible light detector provided in this embodiment includes configurable valid image rows and configurable invalid data rows. The invalid data rows include 16 physical dark rows and a pre-scan row with a maximum number of 261,048 rows. Valid image rows can start from row 0, with a maximum row address of 1079, meaning a maximum of 1080 rows.

[0081] Furthermore, the number of the first valid row in the first half of the partition satisfies the following formula:

[0082] M T =T END -T START +1

[0083] Where T END For the first terminating line, T START This is the first starting line.

[0084] The number of the first invalid line can be set to the minimum value of the first dark line to ensure high-frequency frames in image acquisition.

[0085] In the example embodiment, the determining the second number of invalid rows of the second half region of the dual-face array visible light detector based on the first number of valid rows and the first number of invalid rows comprises:

[0086] Summing the first number of valid rows and the first number of invalid rows to obtain the second number of invalid rows of the second half region.

[0087] The second number of invalid rows satisfies the following formula:

[0088] N BINVAL =M T +N TINVAL

[0089] Wherein, M T is the first number of valid rows, and N TINVAL is the first number of invalid rows.

[0090] The dark row counting at the start of the rising edge of the second frame valid signal comprises:

[0091] Obtaining the maximum number of dark rows of the second half region of the dual-face array visible light detector;

[0092] Based on the size relationship between the maximum number of dark rows and the second number of invalid rows, modifying the second dark row of the second half region;

[0093] Based on the modified second dark row, performing dark row counting.

[0094] The modifying the second dark row of the second half region based on the size relationship between the maximum number of dark rows and the second number of invalid rows comprises:

[0095] If the second number of invalid rows is greater than the maximum number of dark rows of the second half region, the second dark row is modified to the maximum number of dark rows;

[0096] If the second number of invalid rows is less than or equal to the maximum number of dark rows of the second half region, the second dark row is modified to the second number of invalid rows.

[0097] The following describes the image acquisition system based on the dual-face array visible light detector provided by the present application. The image acquisition system based on the dual-face array visible light detector described below can be correspondingly referred to the image acquisition method based on the dual-face array visible light detector described above.

[0098] Figure 3 FIG. 1 is a structural schematic diagram of the image acquisition system provided by the embodiment of the present application.

[0099] As Figure 3As shown, the image acquisition system based on the double-sided array visible light detector comprises:

[0100] The signal acquisition unit 301 is configured to determine a first frame valid signal of a first half area of the double-sided array visible light detector, and determine a second frame valid signal of a second half area;

[0101] The signal processing unit 302 is configured to perform an or operation on the first frame valid signal and the second frame valid signal after shaping the second frame valid signal to determine a third frame valid signal, wherein the third frame valid signal is set to a high level when a dark row in the first half area is read out, and is set to a low level after the valid row in the second half area is read out.

[0102] The image acquisition unit 303 is configured to control the double-sided array visible light detector to perform image acquisition based on the third frame valid signal.

[0103] Figure 4 is a structural schematic diagram of the real-time imaging system provided by the embodiment of the present application.

[0104] As Figure 4 shown, the present application further provides a real-time imaging system based on a double-sided array visible light detector, comprising a control chip, which is configured to implement the image acquisition method based on the double-sided array visible light detector according to any one of the above embodiments.

[0105] The double-sided array visible light detector comprises a first half area and a second half area.

[0106] The image display device is configured to image the image acquired by the double-sided array visible light detector.

[0107] The first half area and the second half area of the double-sided array visible light detector can synchronously perform image exposure.

[0108] Specifically, the control chip can be a field programmable gate array (FPGA). In addition to the FPGA, the double-sided array visible light detector, and the image display device, the real-time imaging system can further comprise a camera power supply circuit. The camera power supply circuit can comprise a +12V power supply interface, an FPGA power supply circuit, a visible light detector power supply circuit, a DAC driving circuit, and an operational amplifier subtraction circuit.

[0109] The FPGA power supply circuit adopts a switching power supply chip to sequentially power on the FPGA chip. The visible light detector power supply circuit adopts a low-dropout linear voltage stabilizing chip to provide low-ripple power supply for the visible light detector. The DAC driving circuit and the operational amplifier subtraction circuit are backup modules for the power supply of the visible light detector. The output voltage of the DAC driving circuit and the operational amplifier subtraction circuit is adjustable, which facilitates the switching of the bias voltage when the working mode of the visible light detector is changed.

[0110] The double-sided array visible light detector provided in the embodiment is model CIS2521F and works in an externally triggered rolling shutter mode. The feature is that it has two independently working upper and lower half regions, i.e. a first half region and a second half region, and the two half regions are independently controlled. The first half region and the second half region each have an external trigger control pin READ for controlling the exposure and imaging of the visible light detector, a plurality of register configuration pins for internal register configuration, and a pulse indication signal pin CHARGE_TRANS, which performs edge control on the READ signal when at a low level.

[0111] Further, the exposure control of the visible light detector is realized by pulling up or pulling down the READ signal through the FPGA. The visible light detector detects the READ signal at the rising edge of the line validity, starts exposure when the rising edge of the READ signal is detected, and ends exposure and starts reading of the image data when the falling edge of the READ signal is detected.

[0112] Figure 5 is a schematic diagram of the connection relationship between the detector and the control chip provided in the embodiment of the application.

[0113] As Figure 5As shown, each half of the detector has an independent input clock pin CLK IN, an external trigger pin READ, JTAG configuration pins, a data synchronization clock output pin SCLK, a pulse indication signal pin CHARGE TRANS, 11 bits of image data output pin DATA, a frame valid signal F VALID, and a line valid signal L VALID. The F VALID is pulled high when reading a physical line, i.e., a dark line in an invalid line and a valid image line, pulled low when reading a pre-scan line, and pulled low at other times. The L VALID is pulsed high at the beginning of each line and pulled low at the end of each line. The CHARGE TRANS is a flag signal that is pulled high at the time of a line period, which means that the ADC is collecting data. At this time, a control signal pulse should not be given to avoid interrupting the ADC collection. The READ signal is an external trigger signal for exposure and reading of the CIS2521F. The exposure control of the visible light detector is achieved by pulling the READ signal high or low through the FPGA. The visible light detector detects the READ signal at the rising edge of the line valid. When the rising edge of the READ signal is detected, the visible light detector starts exposure. When the falling edge of the READ signal is detected, the visible light detector ends exposure and starts reading of the image data. The CIS2521F has multiple registers for mode configuration. The present application mainly involves registers 6, 7, and 8. The register 6 is a valid image start line address configuration register for a half area, the register 7 is a valid image end line address configuration register for a half area, and the register 8 is a number of invalid data lines configuration register for a half area. When the value of the register 8 is less than or equal to 16, the invalid data lines are all dark lines. When the value of the register 8 is greater than 16, the invalid data lines include pre-scan lines and dark lines.

[0114] Further, the register configuration of the CIS2521F uses a JTAG interface, and the upper and lower halves have independent JTAG configuration interfaces.

[0115] Further, as shown, Figure 2 The image data of each half of the CIS2521F includes configurable valid image lines and configurable invalid data lines. The invalid data lines include 16 physical dark lines and pre-scan lines with a maximum of 261048 lines. The valid image lines can start from the 0th line and have a maximum of 1080 lines.

[0116] The FPGA includes an RS422 serial port receiving module, an ROI parameter calculation module, a JTAG data sending module, a detector control module, a frame valid signal waveform integration module, and an image data acquisition module.

[0117] The RS422 serial port receiving module is used for receiving register configuration information and camera control information from the host computer, including the first half area effective image area start and end row TSTART and TEND, the second half area effective image area start and end row BSTART and BEND, frame frequency, exposure time and other parameters.

[0118] The ROI parameter calculation module is used for calculating the number of invalid rows of the second half area according to the data accepted by the RS422 serial port receiving module, so as to ensure that the first half area and the second half area can not overlap data under the premise of simultaneous exposure, and the visible light detector is read out in turn. The number of effective image data rows M of the first half area T = T END -T START +1. The number of invalid rows N of the first half area TINVAL is set to the minimum value of the dark row to ensure the high frame frequency of image acquisition. According to the calculation result M T of the number of effective image rows of the first half area and the number of invalid rows N TINVAL , the number of invalid rows N of the second half area is determined BINVAL = M T +N TINVAL .

[0119] The JTAG data sending module is used for configuring the internal register of the visible light detector, and writes information such as the start and end rows of the effective image of the two half areas and the number of invalid rows into the visible light detector.

[0120] The detector control module is used for controlling the external trigger signal READ of the visible light detector. According to the frame frequency F and exposure time T EXP sent by the host computer, the READ signals of the first and second half areas are synchronously controlled. The first falling edge of CHARGE_TRANS pulls up the READ signal after the register configuration is completed, and the first rising edge of the READ signal starts counting. When the counting time reaches T EXP , the READ signal is pulled down after the falling edge of CHARGE_TRANS arrives. When the counting time reaches 1 / F seconds, the READ signal is pulled up again after the falling edge of CHARGE_TRANS arrives, so that the visible light detector performs the exposure of the next frame, and the above steps are started to be recycled.

[0121] The frame valid signal waveform integration module is used to generate the final frame valid signal waveform for pseudo-single-plane array image data receiving. In this module, first, the second dark row row number of the second half area is judged, and after the second dark row row number is determined, the dark row row counting is started at the rising edge of the frame valid signal of the second half area, and the frame valid signal to be shaped is pulled low. When the counting value reaches the second dark row, the counting value is cleared and the frame valid signal to be shaped is pulled high. When the valid image data is output, the frame valid signal to be shaped is continuously pulled high until the valid image data reading is completed. Finally, the frame valid signals of the shaped second half area and the first half area are ORed to obtain the final pseudo-single-plane array frame valid signal. This signal is pulled high when the first half area dark row is read out, and is pulled low after the second half area valid image data row reading is completed, realizing the seamless connection of the first half area and the second half area valid image data row reading.

[0122] The image data acquisition module uses the shaped frame valid signal to perform pseudo-single-plane array acquisition on the image data and transmit the image data to the upper computer for display through the camera link interface.

[0123] Figure 6 is a flow structure diagram of the image acquisition method provided by the embodiment of the present application.

[0124] Figure 7 is a timing diagram of the image acquisition method provided by the embodiment of the present application.

[0125] The image acquisition system provided by the present application will be described in detail below in combination with the real-time imaging system provided by the present application, as shown in Figure 6 and Figure 7 , comprising the following steps:

[0126] Step 1: The exposure time T EXP =1ms, the frame frequency F=100HZ, the first start row and the first end row of the first half area, and the second start row and the second end row of the second half area are sent by the upper computer and received by the RS422 serial port receiving module of the FPGA. START =0 and T END =99, the second start row and the second end row of the second half area are respectively denoted as B START =0 and B END =199.

[0127] Step 2: The first valid row row number of the first half area is calculated and the first invalid row row number of the first half area is determined in the ROI parameter calculation module according to the serial port configuration data. The first valid row row number of the first half area is denoted as M T =T END -T START +1=99-0+1=100 rows. The first invalid row row number N TINVALSet to 2 in the program to ensure high frame frequency of image acquisition. According to the calculation result M of the first valid row number of the first half area T = 100 rows and the first invalid row number N of the first half area TINVAL = 2 to determine the second invalid row number N of the second half area BINVAL = M T + N TINVAL = 100 + 2 = 102 rows.

[0128] Step 3: The result of step 2 is sent to the visible light detector through the JTAG interface by the JTAG data sending module, and the register configuration is completed, so that the visible light detector normally works in the externally triggered rolling shutter mode, and the valid image row start and end addresses and the invalid row number are successfully configured.

[0129] Step 4: The exposure and imaging of the visible light detector are controlled by the detector control module. First, the working clock input CLK_IN of the visible light detector is set to 130 MHZ, and the main clock of the detector control module also uses the same 130 MHZ clock. Then, according to the frame frequency F and the exposure time T EXP The READ signals of the first half area and the second half area are synchronously controlled. After the register configuration is completed, the falling edge of the first CHARGE_TRANS is waited for, and when the CHARGE_TRANS falling edge is detected, the READ signals of the first half area and the second half area are simultaneously pulled high, the visible light detector starts exposure, and a counter starts exposure time counting. Since the 130M main clock is used, the maximum value of the exposure time counting should be 130M*T EXP / 1000-1 = 130M / 1000-1 = 129999, and the maximum value of the frame time counting should be 130M*(1 / F)-1 = 130M*(1 / 100)-1 = 1299999. When the counting value reaches 129999, the READ signal is pulled low when the next CHARGE_TRANS falling edge arrives, so as to ensure that the exposure time of each frame is the same. Otherwise, the exposure time between frames may have a time difference of one row, resulting in image flicker. When the counting value reaches 1299999, the counting value is cleared and the READ signal is pulled high again, so that the visible light detector performs exposure of the next frame and starts the cycle.

[0130] Step 5: The frame valid signal waveform used for pseudo-single-plane operation is generated by the frame valid signal waveform integration module. In this module, first, the second dark row number N BBLACK of the second half area is determined. Since the second invalid row number N BINVAL of the second half area of the embodiment of the present application is 102 rows, which is greater than the maximum number of dark rows, the second dark row number N BBLACK= 16. After determining the number of dark rows, the dark row count is started at the rising edge of the second half area frame valid signal. The count value is increased by 1 each time a rising edge of the row valid signal is detected, and the frame valid signal to be shaped is pulled low. When the count value reaches 16, the count value is cleared and the frame valid signal to be shaped is pulled high. The frame valid signal to be shaped is continuously pulled high when outputting valid image data until the image data reading is completed. Finally, the frame valid signals of the shaped second half area and the first half area are logically ORed to obtain the final pseudo single-plane array frame valid signal. This signal is pulled high during the reading of the dark rows of the first half area, and is pulled low after the reading of the valid image data rows of the second half area is completed, thereby realizing seamless connection of the reading of the valid image data rows of the first half area and the second half area.

[0131] Step 6: The image data is collected by the image data collection module using the shaped frame valid signal, and is transmitted to the host computer for display through the CameraLink interface. The CameraLink transmission chip of the camera system uses a 65 MHZ main clock, and uses a double-TAP mode, that is, two pixels are transmitted to the host computer at a time, thereby ensuring a high frame rate.

[0132] Figure 8 An example of an electronic device is shown in FIG. 1, which can include a processor 810, a communications interface 820, a memory 830, and a communications bus 840. The processor 810, the communications interface 820, and the memory 830 can communicate with each other through the communications bus 840. The processor 810 can invoke a logical instruction in the memory 830 to execute an image collection method based on a dual-plane array visible light detector, which includes the following steps: Figure 8

[0133] determining a first frame valid signal of a first half area of the dual-plane array visible light detector, and determining a second frame valid signal of a second half area;

[0134] after shaping the second frame valid signal, logically ORing the first frame valid signal and the second frame valid signal to determine a third frame valid signal, the third frame valid signal being set to a high level during the reading of dark rows of the first half area, and being set to a low level after the reading of valid rows of the second half area is completed;

[0135] based on the third frame valid signal, controlling the dual-plane array visible light detector to collect images;

[0136] wherein shaping the second frame valid signal includes:

[0137] ​Counting the dark row at the beginning of the rising edge of the second frame valid signal, and setting the second frame valid signal to be shaped to low level;

[0138] Setting the second frame valid signal to be shaped to high level during image acquisition.

[0139] In addition, the logical instructions in the memory 830 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or the part of the prior art that contributes essentially or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0140] On the other hand, the present application also provides a computer program product, the computer program product comprising a computer program, the computer program being storable on a non-transitory computer readable storage medium, and the computer program being executable by a processor, so that the computer can execute the image acquisition method based on the double-sided array visible light detector provided by the above-mentioned method, the method comprising:

[0141] Determining a first frame valid signal of a first half region of the double-sided array visible light detector, and determining a second frame valid signal of a second half region;

[0142] After shaping the second frame valid signal, performing or operation on the first frame valid signal and the second frame valid signal to determine a third frame valid signal, the third frame valid signal being set to high level when reading out the dark row in the first half region, and being set to low level after completing reading out the valid row in the second half region;

[0143] Based on the third frame valid signal, controlling the double-sided array visible light detector to perform image acquisition;

[0144] Wherein, shaping the second frame valid signal comprises:

[0145] Counting the dark row at the beginning of the rising edge of the second frame valid signal, and setting the second frame valid signal to be shaped to low level;

[0146] Setting the second frame valid signal to be shaped to high level during image acquisition.

[0147] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the image acquisition method based on a double-sided array visible light detector provided by the above method, the method comprising:

[0148] determining a first frame valid signal of a first half region of the double-sided array visible light detector, and determining a second frame valid signal of a second half region;

[0149] performing an OR operation on the first frame valid signal and the second frame valid signal to determine a third frame valid signal after shaping the second frame valid signal, the third frame valid signal being set to a high level when a dark row of the first half region is read out, and being set to a low level after the valid row of the second half region is read out;

[0150] controlling the double-sided array visible light detector to perform image acquisition based on the third frame valid signal;

[0151] wherein the shaping of the second frame valid signal comprises:

[0152] starting dark row counting at the rising edge of the second frame valid signal, and setting the second frame valid signal to be shaped to a low level;

[0153] setting the second frame valid signal to be shaped to a high level during image acquisition.

[0154] The device embodiments described above are merely illustrative, wherein the units shown as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0155] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary general hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods of the various embodiments or some parts of the embodiments.

[0156] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An image acquisition method based on a dual-array visible light detector, characterized in that, include: Determine the first frame of valid signal in the first half of the dual-array visible light detector, and determine the second frame of valid signal in the second half of the detector; After shaping the second frame valid signal, the first frame valid signal and the second frame valid signal are ORed to determine the third frame valid signal. The third frame valid signal is set to a high level when the dark line of the first half-zone is read out, and is set to a low level after the valid line of the second half-zone is read out. Based on the valid signal of the third frame, control the dual-array visible light detector to acquire images; The shaping of the second frame of valid signal includes: The dark line count begins at the rising edge of the second frame valid signal, and the second frame valid signal to be shaped is set to a low level; During image acquisition, the valid signal of the second frame to be shaped is set to a high level; The step of performing dark line counting at the beginning of the rising edge of the second frame's valid signal includes: Calculate the number of valid image rows and the number of invalid rows in the first half of the image region; Based on the number of valid image rows and the number of invalid rows in the first half of the region, determine the number of second invalid rows in the second half of the region; Obtain the maximum number of dark rows in the second half of the dual-array visible light detector; Based on the relationship between the maximum number of dark lines and the number of the second invalid lines, the second dark line in the second half of the region is modified; Count the number of secret lines based on the modified second secret line; The modification of the second dark line in the second half of the region based on the relationship between the maximum number of dark lines and the number of the second invalid lines includes: If the number of the second invalid lines is greater than the maximum number of dark lines in the second half of the area, the second dark line will be modified to the maximum number of dark lines. If the number of the second invalid lines is less than or equal to the maximum number of dark lines in the second half of the zone, the second dark line is modified to the number of the second invalid lines.

2. The image acquisition method based on a dual-array visible light detector according to claim 1, characterized in that, The determination of the first frame valid signal of the first half of the first half of the dual-array visible light detector, and the determination of the second frame valid signal of the second half of the second half, include: Determine the first effective row number, the first invalid row number, and the second effective row number of the second half-region of the dual-array visible light detector; Based on the first valid row count and the first invalid row count, determine the second invalid row count of the second half of the second half of the dual-array visible light detector; The first valid row count, the first invalid row count, the second valid row count, and the second invalid row count are input into the dual-array visible light detector, and the first frame valid signal and the second frame valid signal output by the dual-array visible light detector are obtained.

3. The image acquisition method based on a dual-array visible light detector according to claim 2, characterized in that, Determining the first effective row number and the first invalid row number of the first half-region of the dual-array visible light detector includes: Obtain the first start line, the first end line, and the first dark line of the first half-region of the dual-array visible light detector; Based on the first starting row and the first ending row, the number of the first valid rows is calculated; Based on the first hidden line, the number of the first invalid lines is calculated.

4. The image acquisition method based on a dual-array visible light detector according to claim 2, characterized in that, Determining the second invalid row count of the second half-region of the dual-array visible light detector based on the first valid row count and the first invalid row count includes: The sum of the first valid row count and the first invalid row count is used to obtain the second invalid row count of the second half of the region.

5. An image acquisition system based on a dual-array visible light detector, applied to the image acquisition method based on a dual-array visible light detector as described in any one of claims 1-4, characterized in that, include: The signal acquisition unit is used to determine the first frame of valid signal in the first half of the dual-array visible light detector, and to determine the second frame of valid signal in the second half of the detector. The signal processing unit is used to shape the second frame valid signal, and then perform an OR operation on the first frame valid signal and the second frame valid signal to determine the third frame valid signal. The third frame valid signal is set to a high level when the dark line of the first half-zone is read out, and is set to a low level after the valid line of the second half-zone is read out. The image acquisition unit is used to control the dual-array visible light detector to acquire images based on the valid signal of the third frame. The signal processing unit is also used for: The dark line count begins at the rising edge of the second frame valid signal, and the second frame valid signal to be shaped is set to a low level; During image acquisition, the valid signal of the second frame to be shaped is set to a high level.

6. A real-time imaging system based on a dual-array visible light detector, characterized in that, include: A control chip for implementing the image acquisition method based on a dual-array visible light detector as described in any one of claims 1-4; A dual-array visible light detector, comprising a first half-region and a second half-region; An image display device for imaging images acquired by a dual-array visible light detector.

Images