Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. A first ion implantation is performed on the NMOS region of the core device area and the NMOS region of the SRAM device area to adjust the threshold voltage of the NMOS region of the core device area to a target value. At this time, the NMOS region of the SRAM device area has a first threshold voltage value. A second threshold voltage value of the PMOS region of the SRAM device area corresponding to the highest yield is determined based on the first threshold voltage value and the relationship between the yield and threshold voltage of the SRAM device. A second ion implantation is performed on the PMOS region of the core device area and the PMOS region of the SRAM device area to adjust the threshold voltage of the PMOS region of the SRAM device area to the second threshold voltage value. The threshold voltage of the PMOS region of the core device area is adjusted a second time to adjust the threshold voltage of the PMOS region of the core device area to the target value. The present invention has the unexpected effect of ensuring that the threshold voltage of the core device area reaches the target value and the threshold voltage corresponding to the highest yield of the SRAM device area while sharing a mask for the core and SRAM device areas to reduce manufacturing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Integrated circuits often contain multiple types of devices, such as core devices and SRAM (static random access memory) devices. Sharing ion implantation masks for these different devices can reduce the number of masks needed, thereby lowering the manufacturing cost of the integrated circuit. However, different devices often require different doping doses to adjust their threshold voltage. When using the same ion implantation mask, it is difficult to achieve the optimal threshold voltage for all devices simultaneously.

[0003] When the core and SRAM devices share the same ion implantation mask, the core and SRAM devices manufactured using conventional processes have exactly the same dopant ions. In this case, after adjusting the core device's threshold voltage to the target value, the SRAM device's threshold voltage may fall into a low-yield region, as the yield of the SRAM device is closely related to the threshold voltage setting of the SRAM device. This makes it impossible to achieve the optimal threshold voltage setting for both the core and SRAM devices simultaneously. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device and a method for forming the same, so as to solve the problem that the Core device and the SRAM device cannot achieve the optimal threshold voltage setting at the same time.

[0005] To solve the above technical problems, the present invention provides a method for forming a semiconductor device, comprising:

[0006] Providing a substrate, the substrate comprising a core device region and an SRAM device region, the core device region comprising a PMOS region and an NMOS region, the SRAM device region comprising a PMOS region and an NMOS region;

[0007] Performing a first ion implantation process to perform well doping and threshold voltage adjustment on the NMOS region of the core device area and the NMOS region of the SRAM device area, so that the threshold voltage of the NMOS region of the core device area is adjusted to a target value. At this time, the NMOS region of the SRAM device area has a first threshold voltage value;

[0008] Determining a second threshold voltage value of the PMOS region of the SRAM device region corresponding to a highest yield based on a first threshold voltage value of the NMOS region of the SRAM device region and a relationship between a yield rate and a threshold voltage of the SRAM device;

[0009] performing a second ion implantation process to perform well doping and threshold voltage adjustment on the PMOS region of the core device area and the PMOS region of the SRAM device area, so that the threshold voltage of the PMOS region of the SRAM device area reaches a second threshold voltage value, and the PMOS region of the core device area has a third threshold voltage value;

[0010] A third ion implantation process is performed to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device region, so that the threshold voltage of the PMOS region of the Core device region reaches a target value.

[0011] Optionally, in the third ion implantation process, the ion type and ion implantation dose are calculated according to the difference between the third threshold voltage value of the PMOS region of the Core device region and the target value.

[0012] Optionally, the type of implanted ions in the third ion implantation process is P-type or N-type.

[0013] Optionally, after the second ion implantation process, if the third threshold voltage of the PMOS region of the Core device region is greater than a target value, P-type ions are implanted.

[0014] Optionally, after the second ion implantation process, if the third threshold voltage of the PMOS region of the Core device region is less than a target value, N-type ions are implanted.

[0015] Optionally, the third ion implantation process uses tilted-angle ion implantation to implant only into the PMOS region of the Core device region.

[0016] Optionally, the distance between the peak value of the implanted ion concentration in the third ion implantation process and the substrate surface is 20 nm to 50 nm.

[0017] Optionally, the PMOS region of the SRAM device area includes a pull-up transistor device area, the NMOS region of the SRAM device area includes a pull-down transistor device area and a transmission gate transistor device area, and the first threshold voltage value of the NMOS region of the SRAM device area is the threshold voltage of the pull-down transistor device area or the transmission gate transistor device area.

[0018] Optionally, the line width of the well-doped ion implantation region of the PMOS region of the Core device region is much larger than the line width of the well-doped ion implantation region of the pull-up transistor device region of the SRAM device region.

[0019] Based on the same inventive concept, the present invention further provides a semiconductor device, which is manufactured using any of the above-mentioned methods for forming a semiconductor device.

[0020] In the method for forming a semiconductor device provided by the present invention, a first ion implantation process is performed to perform well doping and threshold voltage adjustment on the NMOS region of the Core device region and the NMOS region of the SRAM device region, so that the threshold voltage of the NMOS region of the Core device region is adjusted to a target value, and at this time, the NMOS region of the SRAM device region has a first threshold voltage value; based on the first threshold voltage value of the NMOS region of the SRAM device region and the relationship between the yield and the threshold voltage of the SRAM device, a second threshold voltage value of the PMOS region of the SRAM device region corresponding to the highest yield is determined; a second ion implantation process is performed to perform well doping and threshold voltage adjustment on the PMOS region of the Core device region and the PMOS region of the SRAM device region, so that the threshold voltage of the PMOS region of the SRAM device region reaches the second threshold voltage value, and at this time, the PMOS region of the Core device region has a third threshold voltage value; a third ion implantation process is performed to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device region, so that the threshold voltage of the PMOS region of the Core device region reaches the target value. The unexpected effect of the present invention is that while the Core device area and the SRAM device area share the mask to reduce manufacturing costs, it also ensures that the threshold voltage of the Core device area reaches the target value and that the SRAM device area reaches the threshold voltage corresponding to the highest yield. That is, while saving masks and reducing manufacturing costs, good Core device performance and SRAM yield are guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0022] Figure 1 The present invention is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0023] Figure 2 It is a partial top view schematic diagram of the Core device area of ​​an embodiment of the present invention.

[0024] Figure 3 FIG. 1 is a schematic diagram of a partial top view of an SRAM device area according to an embodiment of the present invention.

[0025] Figure 4 It is a schematic structural diagram of the Core device area and the SRAM device area performing the first ion implantation process according to an embodiment of the present invention.

[0026] Figure 5 4 is a graph showing the relationship between the yield and threshold voltage of an SRAM device according to an embodiment of the present invention.

[0027] Figure 6It is a schematic structural diagram of the Core device area and the SRAM device area performing the second ion implantation process according to an embodiment of the present invention.

[0028] Figure 7 It is a schematic structural diagram of the Core device area and the SRAM device area performing the third ion implantation process according to an embodiment of the present invention.

[0029] In the accompanying drawings: 11-Core device area; 11a-PMOS area of ​​the Core device area; 11b-NMOS area of ​​the Core device area; 12-SRAM device area; 12a-pull-up transistor device area; 12b-transmission gate transistor device area; 12c-pull-down transistor device area; 13-shallow trench isolation structure; 14-patterned first photoresist layer; 15-patterned second photoresist layer. DETAILED DESCRIPTION

[0030] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0031] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is provided on another element, which generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements can be direct or indirect through an intermediate element, and should not be understood to indicate or imply the spatial position relationship between the two elements, that is, one element can be in any orientation such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] Figure 1 FIG. 1 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 1As shown, this embodiment provides a method for forming a semiconductor device, including:

[0033] Step S10, providing a substrate, wherein the substrate includes a core device region and an SRAM device region, wherein the core device region includes a PMOS region and an NMOS region, and the SRAM device region includes a PMOS region and an NMOS region;

[0034] Step S20, performing a first ion implantation process to perform well doping and threshold voltage adjustment on the NMOS region of the Core device region and the NMOS region of the SRAM device region, so that the threshold voltage of the NMOS region of the Core device region is adjusted to a target value. At this time, the NMOS region of the SRAM device region has a first threshold voltage value.

[0035] Step S30, determining a second threshold voltage value of the PMOS region of the SRAM device region corresponding to the highest yield based on the first threshold voltage value of the NMOS region of the SRAM device region and the relationship between the yield rate and the threshold voltage of the SRAM device;

[0036] Step S40, performing a second ion implantation process to perform well doping and threshold voltage adjustment on the PMOS region of the Core device region and the PMOS region of the SRAM device region, so that the threshold voltage of the PMOS region of the SRAM device region reaches a second threshold voltage value. At this time, the PMOS region of the Core device region has a third threshold voltage value.

[0037] Step S50 , performing a third ion implantation process to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device region, so that the threshold voltage of the PMOS region of the Core device region reaches a target value.

[0038] In order to make the above-mentioned purpose, features and beneficial effects of the present invention more obvious and easy to understand, the following Figures 2 to 7 The specific embodiments of the present invention are described in detail.

[0039] like Figure 2 and Figure 3 As shown, Figure 2 It is a partial top view schematic diagram of the Core device area of ​​an embodiment of the present invention. Figure 3 FIG. 1 is a schematic diagram of a partial top view of an SRAM device area according to an embodiment of the present invention. Figure 2 and Figure 3The semiconductor device layout includes a core device and an SRAM device, and the core device and the SRAM device share the same ion implantation mask, thereby saving the number of masks and reducing manufacturing costs. Correspondingly, the substrate includes a core device area 11 and an SRAM device area 12. The core device area 11 includes a PMOS area and an NMOS area. The SRAM device area 12 also includes a PMOS area and an NMOS area. The device in the PMOS area of ​​the SRAM device area 12 is a pull-up transistor (PU) device area 12a. In terms of layout design, the line width CD1 of the well-doped ion implantation area of ​​the PMOS area 11a of the core device area is much larger than the line width CD2 of the well-doped ion implantation area of ​​the pull-up transistor device area 12a of the SRAM device area.

[0040] like Figure 4 As shown, a substrate is provided, which can serve as an operating platform for subsequent processes. The substrate can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, including a bare die or a wafer processed through an epitaxial growth process. Specifically, the substrate can be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate is a silicon substrate. The substrate includes a core device region 11 and an SRAM device region 12. The core device region 11 includes a PMOS region and an NMOS region, namely, a PMOS region 11a of the core device region and an NMOS region 11b of the core device region 11. The adjacent PMOS region 11a and NMOS region 11b of the core device region 11 are separated by a shallow trench isolation structure 13. The SRAM device region 12 includes a PMOS region and an NMOS region. The PMOS region includes a pull-up transistor (PU) device region 12a, and the NMOS region includes a pass gate transistor (PG) device region 12b and a pull-down transistor (PD) device region 12c. The pull-up transistor device region 12a is located between the pass gate transistor device region 12b and the pull-down transistor device region 12c. The pull-up transistor device region 12a, the pass gate transistor device region 12b, and the pull-down transistor device region 12c are isolated from each other by a shallow trench isolation structure 13.

[0041] Please continue to refer to Figure 4A first ion implantation process is performed to perform well doping and threshold voltage adjustment on the NMOS region 11b of the Core device region and the NMOS region of the SRAM device region, so that the threshold voltage of the NMOS region 11b of the Core device region is adjusted to a target value. At this time, the NMOS region of the SRAM device region has a first threshold voltage value. Specifically, a first photoresist layer is formed, the first photoresist layer covering the substrate of the Core device region and the SRAM device region, and a photolithography process is performed to form a patterned first photoresist layer 14. The patterned first photoresist layer 14 exposes the NMOS region 11b of the Core device region and the NMOS region of the SRAM device region. The NMOS region of the SRAM device region is also the transfer gate transistor device region 12b and the pull-down transistor device region 12c. Using the patterned first photoresist layer 14 as a mask, a first ion implantation process is performed on the NMOS region 11b of the Core device region and the pass-gate transistor region 12b and pull-down transistor region 12c of the SRAM device region. The first ion implantation process includes a well doping ion implantation process and a threshold voltage adjustment ion implantation process. The ions used in the first ion implantation process are P-type ions. This forms a P-well in the substrate of the NMOS region 11b of the Core device region and the pass-gate transistor region 12b and pull-down transistor region 12c of the SRAM device region, and adjusts the threshold voltage of the NMOS region 11b of the Core device region to a target value. At this point, the pull-down transistor region 12c of the SRAM device region has a first threshold voltage value, Vtlin_PD, and the pass-gate transistor region 12b of the SRAM device region has a first threshold voltage value, Vtlin_PG.

[0042] Figure 5 4 is a graph showing the relationship between the yield and threshold voltage of an SRAM device according to an embodiment of the present invention. Figure 5 The horizontal axis is the threshold voltage of the PD, that is, the threshold voltage of the pull-down transistor in the SRAM device area. Figure 5 The vertical axis is the threshold voltage of PU, that is, the threshold voltage of the pull-up transistor in the SRAM device area. Pass ratio_32M refers to the yield of the 32M capacity SRAM device, and different colors represent the size of the SRAM device yield. Blue represents a lower yield, and red represents a higher yield. According to the first threshold voltage value of the NMOS area of ​​the SRAM device area, that is, the first threshold voltage value Vtlin_PD of the pull-down transistor device area 12c of the SRAM device area, or the first threshold voltage value Vtlin_PG of the transmission gate transistor device area 12b of the SRAM device area, and the relationship between the yield and threshold voltage of the SRAM device, the second threshold voltage value of the PMOS area of ​​the SRAM device area corresponding to the highest yield is determined. Figure 5As shown, since the first threshold voltage value Vtlin_PD of the pull-down transistor device area 12c of the SRAM device area is the same as the first threshold voltage value Vtlin_PG of the transfer gate transistor device area 12b of the SRAM device area, this embodiment takes the first threshold voltage value Vtlin_PD of the pull-down transistor device area 12c of the SRAM device area as an example to determine the second threshold voltage value of the PMOS area of ​​the SRAM device area corresponding to the highest yield, that is, the second threshold voltage value Vtlin_PU of the pull-up transistor device area 12a of the SRAM device area.

[0043] like Figure 6 As shown, a second ion implantation process is performed to perform well doping and threshold voltage adjustment on the PMOS region 11a of the Core device region and the PMOS region of the SRAM device region, so that the threshold voltage of the PMOS region of the SRAM device region reaches a second threshold voltage value. At this time, the PMOS region of the Core device region has a third threshold voltage value. Specifically, a second photoresist layer is formed, the second photoresist layer covering the substrate of the Core device region 11 and the SRAM device region 12. A photolithography process is performed to form a patterned second photoresist layer 15. The patterned second photoresist layer 15 exposes the PMOS region 11a of the Core device region and the PMOS region of the SRAM device region. The PMOS region of the SRAM device region is also the pull-up transistor device region 12a. Using the patterned second photoresist layer 15 as a mask, a second ion implantation process is performed on the PMOS region 11a of the Core device region and the pull-up transistor device region 12a of the SRAM device region. The second ion implantation process includes a well doping ion implantation process and a threshold voltage adjustment ion implantation process. The ions used in the second ion implantation process are N-type ions, forming an N-well in the substrate of the PMOS region 11a of the Core device region and the pull-up transistor device region 12a of the SRAM device region, and causing the threshold voltage of the pull-up transistor device region 12a of the SRAM device region to reach a second threshold voltage value, Vtlin_PU. At this point, the PMOS region 11a of the Core device region has a third threshold voltage value, Vtlin_Core_PMOS. The third threshold voltage value, Vtlin_Core_PMOS, of the PMOS region 11a of the Core device region may or may not reach the target value of the PMOS region 11a of the Core device region.

[0044] like Figure 7As shown, the difference between the third threshold voltage value Vtlin_Core_PMOS of the PMOS region 11a in the Core device area and the target value of the PMOS region 11a in the Core device area is compared, and a third ion implantation process is performed to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region 11a in the Core device area so that the threshold voltage of the PMOS region 11a in the Core device area reaches the target value. In the third ion implantation process, the ion type and ion implantation dose of the ion implantation are calculated based on the difference between the third threshold voltage value of the PMOS region 11a in the Core device area and the target value. The implanted ions in the third ion implantation process are P-type or N-type. If the third threshold voltage Vtlin_Core_PMOS of the PMOS region 11a in the Core device area is greater than the target value, P-type ions are implanted to consume excess N-type ions by inversion. If the third threshold voltage Vtlin_Core_PMOS of the PMOS region 11a in the Core device area is less than the target value, N-type ions are implanted to increase the dose of N-type ions. The distance between the peak value of the injected ion concentration in the third ion implantation process and the surface of the substrate is 20nm~50nm. If the ion implantation is too shallow, that is, too close to the surface of the substrate, the hole mobility on the substrate surface will be affected. If the ion implantation is too deep, it will not be conducive to adjusting the threshold voltage. Since the threshold voltage of the pull-up transistor device area 12a in the SRAM device area has reached the threshold voltage corresponding to the highest yield of the SRAM device area, the third ion implantation process only implants the PMOS area 11a in the Core device area and cannot implant the pull-up transistor device area 12a in the SRAM device area. The third ion implantation process adopts tilted ion implantation to implant only the PMOS area 11a in the Core device area. Because the line width CD1 of the well-doped ion implantation region of the PMOS region 11a of the Core device region is much larger than the line width CD2 of the well-doped ion implantation region of the pull-up transistor device region 12a of the SRAM device region, the angle between the ion beam and the substrate must be at least less than a first preset angle based on the line width CD2 of the well-doped ion implantation region of the pull-up transistor device region 12a of the SRAM device region and the thickness of the patterned second photoresist layer 15, so as to avoid implantation into the pull-up transistor device region 12a of the SRAM device region. In other words, the angle between the ion beam and the vertical direction must be at least greater than a second preset angle θ, so as to avoid implantation into the pull-up transistor device region 12a of the SRAM device region. The first preset angle and the second preset angle are complementary, that is, the sum of the first preset angle and the second preset angle is 90°. In this embodiment, the second preset angle θ is, for example, 15° to 25°.Because the blocking of the patterned second photoresist layer 15 will not be injected into the pull-up transistor device area 12a of the SRAM device area, the third ion implantation process can increase or decrease the threshold voltage of the PMOS area 11a of the Core device area relative to the threshold voltage of the pull-up transistor device area 12a of the SRAM device area, so as to adjust the threshold voltage of the PMOS area 11a of the Core device area to reach the target value. It is worth noting that the doping ions for adjusting the threshold voltage of the Core device area 11 and the SRAM device area 12 are uniformly distributed in the direction parallel to the channel surface, which can ensure good threshold voltage uniformity. This embodiment uses the above method to ensure that the threshold voltage of the Core device reaches the target value while the SRAM device reaches the threshold voltage corresponding to the highest yield, that is, while saving masks and reducing manufacturing costs, it ensures good Core device performance and SRAM yield.

[0045] This embodiment also provides a semiconductor device, which is prepared using the semiconductor device formation method as described in any of the above items. The semiconductor device includes a Core device and an SRAM device. The Core device and the SRAM device share a mask to reduce manufacturing costs, while ensuring that the threshold voltage of the Core device reaches a target value and that the SRAM device reaches a threshold voltage corresponding to the highest yield. That is, while saving masks and reducing manufacturing costs, good Core device performance and SRAM yield are guaranteed.

[0046] In summary, it can be seen that in the method for forming a semiconductor device provided in an embodiment of the present invention, a first ion implantation process is performed to perform well doping and adjust the threshold voltage of the NMOS region of the Core device area and the NMOS region of the SRAM device area, so that the threshold voltage of the NMOS region of the Core device area is adjusted to a target value, and at this time the NMOS region of the SRAM device area has a first threshold voltage value; according to the first threshold voltage value of the NMOS region of the SRAM device area and the relationship between the yield and the threshold voltage of the SRAM device, the second threshold voltage value of the PMOS region of the SRAM device area corresponding to the highest yield is determined; a second ion implantation process is performed to perform well doping and adjust the threshold voltage of the PMOS region of the Core device area and the PMOS region of the SRAM device area, so that the threshold voltage of the PMOS region of the SRAM device area reaches the second threshold voltage value, and at this time the PMOS region of the Core device area has a third threshold voltage value; a third ion implantation process is performed to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device area, so that the threshold voltage of the PMOS region of the Core device area reaches the target value. The unexpected effect of the present invention is that while the Core device area and the SRAM device area share the mask to reduce manufacturing costs, it also ensures that the threshold voltage of the Core device area reaches the target value and that the SRAM device area reaches the threshold voltage corresponding to the highest yield. That is, while saving masks and reducing manufacturing costs, good Core device performance and SRAM yield are guaranteed.

[0047] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0048] Furthermore, it should be recognized that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. Any person skilled in the art can utilize the above disclosed technical content to make many possible changes and modifications to the technical solution of the present invention, or modify it into equivalent embodiments with equivalent variations, without departing from the scope of the technical solution of the present invention. Therefore, any simple modifications, equivalent variations, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a core device region and an SRAM device region, the core device region comprising a PMOS region and an NMOS region, the SRAM device region comprising a PMOS region and an NMOS region; Performing a first ion implantation process to perform well doping and threshold voltage adjustment on the NMOS region of the core device area and the NMOS region of the SRAM device area, so that the threshold voltage of the NMOS region of the core device area is adjusted to a target value. At this time, the NMOS region of the SRAM device area has a first threshold voltage value; Determining a second threshold voltage value of the PMOS region of the SRAM device region corresponding to a highest yield based on a first threshold voltage value of the NMOS region of the SRAM device region and a relationship between a yield rate and a threshold voltage of the SRAM device; performing a second ion implantation process to perform well doping and threshold voltage adjustment on the PMOS region of the core device area and the PMOS region of the SRAM device area, so that the threshold voltage of the PMOS region of the SRAM device area reaches a second threshold voltage value, and the PMOS region of the core device area has a third threshold voltage value; A third ion implantation process is performed to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device region, so that the threshold voltage of the PMOS region of the Core device region reaches a target value.

2. The method for forming a semiconductor device according to claim 1, wherein: In the third ion implantation process, the ion type and ion implantation dose of the ion implantation are calculated according to the difference between the third threshold voltage value of the PMOS region of the Core device region and the target value.

3. The method for forming a semiconductor device according to claim 2, wherein: The type of implanted ions in the third ion implantation process is P-type or N-type.

4. The method for forming a semiconductor device according to claim 3, wherein: After the second ion implantation process, if the third threshold voltage of the PMOS region of the Core device region is greater than a target value, P-type ions are implanted.

5. The method for forming a semiconductor device according to claim 3, wherein: After the second ion implantation process, if the third threshold voltage of the PMOS region in the Core device region is less than a target value, N-type ions are implanted.

6. The method for forming a semiconductor device according to claim 2, wherein: The third ion implantation process uses tilted-angle ion implantation to implant only the PMOS region of the Core device region.

7. The method for forming a semiconductor device according to claim 6, wherein: The distance between the position of the implanted ion concentration peak in the substrate and the substrate surface in the third ion implantation process is 20 nm to 50 nm.

8. The method for forming a semiconductor device according to claim 1, wherein: The PMOS region of the SRAM device region includes a pull-up transistor device region, the NMOS region of the SRAM device region includes a pull-down transistor device region and a transmission gate transistor device region, and the first threshold voltage value of the NMOS region of the SRAM device region is the threshold voltage of the pull-down transistor device region or the transmission gate transistor device region.

9. The method for forming a semiconductor device according to claim 8, wherein: The line width of the well-doped ion implantation region of the PMOS region of the Core device region is much larger than the line width of the well-doped ion implantation region of the pull-up transistor device region of the SRAM device region.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for forming the semiconductor device according to any one of claims 1 to 9.

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