Large-scale integration method for ultra-clean and extensible two-dimensional flash memory

Abstract

The invention belongs to the technical field of semiconductor memories, and particularly relates to a super-clean and extensible two-dimensional flash memory large-scale integration method. According to the invention, large-scale two-dimensional flash memory array integration is realized through ultra-clean interface engineering and extensible material stacking design. The method has the ultra-clean interface characteristic, and a heterogeneous interface with atomic-scale flatness can be achieved; the method has high expandability and is suitable for large-scale manufacturing of different two-dimensional material stacking systems. The prepared array device is not obviously polluted under optical microscopes, atomic force microscopes and scanning electron microscopes. The ultra-clean characteristic and the highly extensible characteristic effectively solve the integration problem of the two-dimensional flash memory array.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor memories, and particularly relates to a method for large-scale integration of flash memories based on two-dimensional materials. Background Art

[0002] With the rapid development of artificial intelligence technology, the demand for high-bandwidth storage technology has become increasingly urgent. Since the invention of flash memory technology by Bell Labs in 1967, with its simple storage mechanism and the ability to support low-cost, high-density integration, it currently occupies more than 99% of the non-volatile memory market. However, the relatively low read / write speed of traditional flash memory limits its application in high-performance computing fields such as artificial intelligence.

[0003] Due to their atomic-scale thickness, excellent electrical properties, and the absence of dangling bonds on the surface, two-dimensional materials are regarded as ideal candidate materials for the next-generation non-volatile storage technology. Flash memory devices based on two-dimensional materials can significantly improve the storage speed, shortening the programming time of silicon-based flash memory from dozens of microseconds to dozens of nanoseconds.

[0004] Currently, only long-channel two-dimensional flash memory devices assembled from two-dimensional materials by manual exfoliation can achieve ultra-fast programming speeds. However, in large-scale integrated long-channel two-dimensional flash memory arrays, their operating speed is still limited to the millisecond level, and the yield is low. This phenomenon is mainly attributed to many technical bottlenecks in the large-scale integration process of two-dimensional flash memory. First, impurities and defects are inevitably introduced during the transfer process of two-dimensional materials, and the residual organic matter will significantly reduce the device performance and production yield. Second, traditional processing techniques are difficult to ensure the high cleanliness of the device interface, thus seriously affecting the electrical properties and reliability of the device. In addition, the existing two-dimensional flash memory integration process lacks a standardized process and good scalability, and is difficult to meet the requirements of large-scale production. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for large-scale integration of ultra-clean and scalable flash memory devices based on two-dimensional materials (hereinafter referred to as two-dimensional flash memory).

[0006] The ultra-clean and scalable two-dimensional flash memory large-scale integration method provided by the present invention realizes the integration of large-scale two-dimensional flash memory arrays through ultra-clean interface engineering and scalable material stack design; its process is as Figure 1 shown. The specific steps are as follows:

[0007] (1) First, clean the Si / SiO2 substrate with acetone;

[0008] (2) The bottom gate electrode is prepared by direct writing lithography and electron beam evaporation; the bottom gate electrode is cleaned by ultrasonic bath and soaking in N-methyl-2-pyrrolidone (NMP) at room temperature, and is further cleaned and activated by annealing in an inert atmosphere and O2 plasma treatment for dielectric deposition;

[0009] Preferably, the bottom gate metal electrode material is selected from one or more of metals such as chromium, gold, platinum, bismuth, and titanium;

[0010] Preferably, the inert atmosphere is selected from nitrogen, argon, etc., the thermal annealing temperature is 200-400 °C, and the annealing time is 2-4 h;

[0011] Preferably, the O2 plasma treatment power is 30-50 W, and the O2 plasma treatment time is 20-180 s;

[0012] (3) An atomic layer deposition (ALD) barrier oxide layer is adopted; a floating gate metal is deposited by direct writing lithography, electron beam evaporation and lift-off process; the floating gate surface is cleaned by ultrasonic bath and soaking in NMP at room temperature; the surface is further cleaned and activated by annealing in an inert atmosphere and O2 plasma treatment for dielectric deposition;

[0013] Preferably, the barrier oxide layer material is selected from alumina (Al2O3), hafnium oxide (HfO2), etc.;

[0014] Preferably, the thickness of the barrier oxide layer is 20-40 nm;

[0015] Preferably, the floating gate metal material is selected from platinum, gold, etc.;

[0016] Preferably, the thickness of the floating gate metal is 1-3 nm;

[0017] Preferably, the inert atmosphere is selected from nitrogen, argon, etc., the thermal annealing temperature is 200-400 °C, and the annealing time is 2-4 h;

[0018] Preferably, the O2 plasma treatment power is 30-50 W, and the O2 plasma treatment time is 20-180 s;

[0019] (4) An ALD is used to deposit a tunneling oxide layer, and thus a storage stack (tunneling oxide layer / floating gate metal / barrier oxide layer) is obtained;

[0020] Preferably, the tunneling oxide layer material is selected from alumina (Al2O3), hafnium oxide (HfO2), etc.;

[0021] Preferably, the thickness of the tunneling oxide layer is 7-15 nm;

[0022] (5) Transfer the two-dimensional material to the storage stack by a polystyrene (PS) assisted transfer process. Remove the PS by soaking in toluene. Anneal the sample in an inert atmosphere thermally to further remove residues and enhance the adhesion to the substrate;

[0023] Preferably, the two-dimensional material is selected from monolayer molybdenum disulfide (MoS2), tungsten diselenide (WSe2), etc.;

[0024] Preferably, the inert atmosphere is selected from nitrogen, argon, etc., the thermal annealing temperature is 200 - 400 °C, and the annealing time is 2 - 4 h;

[0025] (6) Pattern the channel using direct write lithography technology and etch it with O2 plasma; then, soak it in molybdenum nitride and perform thermal annealing in an inert atmosphere to remove photoresist residues and flatten the film;

[0026] Preferably, the O2 plasma treatment power is 30 - 50 W, and the O2 plasma treatment time is 20 - 180 s;

[0027] Preferably, the inert atmosphere is selected from nitrogen, argon, etc., the thermal annealing temperature is 200 - 400 °C, and the thermal annealing time is 2 - 4 h;

[0028] (7) Prepare source and drain electrodes by direct write lithography and electron beam evaporation.

[0029] Preferably, the source and drain electrode materials are selected from one or more of metals such as chromium, gold, platinum, bismuth, titanium, etc.

[0030] The present invention realizes the integration of a 1 Kb two-dimensional flash memory array through innovative ultra-clean interface engineering and scalable material stack design. The present invention has ultra-clean interface characteristics, can achieve an atomically flat heterogeneous interface, and no obvious contamination is observed under an optical microscope, an atomic force microscope (AFM), and a scanning electron microscope (SEM); at the same time, the present invention has high scalability and is suitable for large-scale manufacturing of different stack systems, such as Al2O3 / Pt / Al2O3, HfO2 / Pt / HfO2, etc. The array devices prepared by the present invention have data retention characteristics of more than ten years. The ultra-clean characteristics and high scalability of the present invention effectively solve the integration problem of two-dimensional flash memory arrays. Description of the Drawings

[0031] Figure 1 It is a flow chart of the method for large-scale integration of two-dimensional flash memory.

[0032] Figure 2 It is a schematic diagram of the array substrate.

[0033] Figure 3 It is a schematic diagram after depositing a metal bottom gate.

[0034] Figure 4 It is a schematic diagram after depositing a blocking oxide layer.

[0035] Figure 5 It is a schematic diagram after depositing a metal floating gate.

[0036] Figure 6 It is a schematic diagram after depositing a tunneling oxide layer.

[0037] Figure 7 It is a schematic diagram after transferring a two-dimensional material.

[0038] Figure 8 It is a schematic diagram after patterning a two-dimensional material channel.

[0039] Figure 9 It is a schematic diagram of the structure of a single device in the array. Detailed implementation manners

[0040] The present invention will be further introduced below through embodiments in conjunction with the accompanying drawings.

[0041] The following is in accordance with the process of the two-dimensional flash memory large-scale integration method, in conjunction with Figures 1 to 9 Specific descriptions will be given.

[0042] Step S11: Use Si / SiO2 as the insulating substrate 1001, and clean the substrate with acetone. As Figure 2 shown;

[0043] Step S12: Pattern the bottom gate array by direct write lithography and double-layer photoresist process (LOR 10A / S1818), and deposit a 5 / 10 / 5 nm Cr / Au / Pt stack on the silicon substrate by electron beam evaporation. As Figure 3 shown, the bottom gate metal 1002 is deposited above the substrate 1001. Clean the bottom gate electrode by ultrasonic bath (~45 s) and soak it in N-methyl-2-pyrrolidone (NMP) at room temperature for more than 12 h, and further clean and activate the surface for dielectric deposition by N2 atmosphere thermal annealing (200 °C, 2.5 h) and O2 plasma treatment (50 W, 20 s);

[0044] Step S13: Prepare a 20 nm Al2O3 blocking oxide by atomic layer deposition (ALD). Determine the floating gate pattern by direct write lithography, and then deposit 3 nm Pt by electron beam evaporation and lift-off process. As Figure 4 、 5As shown, the floating gate metal 1004 and the blocking oxide layer 1003 are above the bottom gate 1002. The surface of the floating gate is cleaned by ultrasonic bath (~10 s) and NMP immersion at room temperature for more than 12 h, and the surface is further cleaned and activated for dielectric deposition by N2 atmosphere thermal annealing (200 °C, 2.5 h) and O2 plasma treatment (50 W, 20 s);

[0045] Step S14, deposit 8 nm Al2O3 as the tunneling oxide layer using the same ALD system. As Figure 6 shown, the APA (Al2O3 / Pt / Al2O3) storage stack is obtained thus far;

[0046] Step S15, as Figure 7 shown, transfer the monolayer MoS2 film 1005 onto the APA memory stack through a polystyrene (PS)-assisted transfer process. Immerse in toluene for more than 12 h to remove PS. The sample is thermally annealed in N2 atmosphere (200 °C, 2.5 h) to further remove residues and enhance the adhesion to the substrate;

[0047] Step S16, as Figure 8 shown, pattern the MoS2 channel using direct write lithography technology and etch it with O2 plasma (50 W, 20 s). Immerse in molybdenum nitride at 80 °C for 3 hours, and then perform heat treatment in N2 atmosphere (200 °C, 2.5 hours) to remove photoresist residues and flatten the MoS2 thin film;

[0048] Step S17, as Figure 9 shown, prepare the source and drain electrodes using direct write lithography technology, and then deposit a 5 nm / 30 nm Cr / Au stack 1006 by electron beam evaporation.

[0049] The present invention realizes large-scale two-dimensional flash memory array integration through innovative ultra-clean interface engineering and scalable material stack design. This process has ultra-clean interface characteristics, enabling an atomically flat heterogeneous interface, and no obvious contamination is observed under optical microscopy, atomic force microscopy (AFM), and scanning electron microscopy (SEM); meanwhile, this process has high scalability and is suitable for large-scale manufacturing of different stack systems, such as Al2O3 / Pt / Al2O3, HfO2 / Pt / HfO2, etc. The array devices prepared by the present invention have data retention characteristics of more than a decade. The ultra-clean characteristics and high scalability of the present invention effectively solve the integration problem of two-dimensional flash memory arrays.

[0050] The above has elaborated in detail the ultra-clean and scalable flash memory scale integration process based on two-dimensional materials of the present invention. It should be noted that the above embodiments are only used to exemplarily illustrate the technical solutions of the present invention, rather than a limitation on the present invention. Without departing from the core concept of the present invention, those skilled in the art can make various improvements and deformations to the process, and these improvements and deformations should all be covered within the protection scope of the present invention.

Claims

1. A super-clean and scalable method for large-scale integration of two-dimensional flash memory, characterized in that Large-scale integration of two-dimensional flash memory arrays is achieved through ultra-clean interface engineering and scalable material stack design. The specific steps are as follows: (1) Clean the Si / SiO2 substrate with acetone. (2) Fabricate the bottom gate electrode using direct-write lithography and electron beam evaporation. Clean the bottom gate electrode by ultrasonic bath and room-temperature immersion in N-methyl-2-pyrrolidone (NMP), and further clean and activate the surface by annealing in an inert atmosphere and O2 plasma treatment for dielectric deposition. (3) Deposit the blocking oxide layer using atomic layer deposition (ALD). Deposit the floating gate metal by direct-write lithography, electron beam evaporation, and lift-off process. Clean the floating gate surface by ultrasonic bath and room-temperature immersion in NMP. Further clean and activate the surface by annealing in an inert atmosphere and O2 plasma treatment for dielectric deposition. (4) Deposit the tunneling oxide layer using ALD, and thus obtain the storage stack, i.e., tunneling oxide layer / floating gate metal / blocking oxide layer. (5) Transfer the two-dimensional material onto the storage stack through a polystyrene (PS)-assisted transfer process. Remove the PS by toluene immersion. Anneal the sample in an inert atmosphere to further remove residues and enhance the adhesion to the substrate. (6) Pattern the channel using direct-write lithography and etch it with O2 plasma. Then, immerse it in molybdenum nitride and perform annealing in an inert atmosphere to remove the photoresist residues and flatten the film. (7) Fabricate the source and drain electrodes using direct-write lithography and electron beam evaporation.

2. The two-dimensional flash memory large-scale integration method according to claim 1, wherein In step (2): The bottom gate metal electrode material is selected from one or more of chromium, gold, platinum, bismuth, and titanium. The inert atmosphere is selected from nitrogen and argon. The annealing temperature is 200 - 400 °C, and the annealing time is 2 - 4 h. The power of the O2 plasma treatment is 30 - 50 W, and the O2 plasma treatment time is 20 - 180 s.

3. The two-dimensional flash memory large-scale integration method according to claim 1, wherein In step (3): The blocking oxide layer material is selected from aluminum oxide and hafnium oxide. The thickness of the blocking oxide layer is 20 - 40 nm. The floating gate metal material is selected from platinum and gold. The thickness of the floating gate metal is 1 - 3 nm. The inert atmosphere is selected from nitrogen, argon, etc. The annealing temperature is 200 - 400 °C, and the annealing time is 2 - 4 h. The power of the O2 plasma treatment is 30 - 50 W, and the O2 plasma treatment time is 20 - 180 s.

4. The two-dimensional flash memory large-scale integration method according to claim 1, characterized in that In step (4), the tunneling oxide layer material is selected from aluminum oxide and hafnium oxide. The thickness of the tunneling oxide layer is 7 - 15 nm.

5. The two-dimensional flash memory large-scale integration method according to claim 1, wherein In step (5): The two-dimensional material is selected from monolayer molybdenum disulfide and tungsten diselenide. The inert atmosphere is selected from nitrogen and argon. The annealing temperature is 200 - 400 °C, and the annealing time is 2 - 4 h.

6. The two-dimensional flash memory large-scale integration method according to claim 1, wherein In step (6), the power of the O2 plasma treatment is 30 - 50 W, and the O2 plasma treatment time is 20 - 180 s. The inert atmosphere is selected from nitrogen, argon, etc. The annealing temperature is 200 - 400 °C, and the annealing time is 2 - 4 h.

7. The method for large-scale integration of two-dimensional flash memory according to claim 1, characterized in that In step (7), the source and drain electrode material is selected from chromium, gold, platinum, bismuth, and titanium.

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