Flat panel detector and detection device

Abstract

The invention relates to a flat panel detector and a detection device. The flat panel detector comprises a substrate; the substrate is provided with a transistor region and a photodiode region which are adjacent to each other; the transistor area is provided with a transistor and a black matrix layer; the transistor comprises a grid electrode, a grid insulating layer, a source electrode, a drain electrode and a channel layer, the grid electrode is connected with a grid line, and the source electrode or the drain electrode is connected with a data line; the black matrix layer is arranged on the side, away from the substrate, of the channel layer, and the black matrix layer is made of an insulating shading material and comprises a first part and a second part; the orthographic projection of the first part on the substrate covers the orthographic projection of the channel layer on the substrate, and the second part is laid along the routing of the data line and / or the grid line. According to the invention, the problem of electric leakage caused by light entering a transistor channel is solved, and the problem of light scattering between adjacent photodiodes (PIN) is also solved.

Description

Technical Field

[0001] The present invention relates to the field of photodetectors, and particularly to a flat panel detector and a detection device. Background Art

[0002] A flat panel detector is a detector that uses semiconductor technology to convert X-ray energy into an electrical signal and generate an X-ray image. The flat panel detector is composed of millions or even tens of millions of pixel unit circuits. The pixel unit circuit is generally composed of a thin film transistor (TFT) and a photodiode (PD), and the photodiode is connected to a bias circuit. The working principle of this flat panel detector is as follows: An electric field is formed in the PD under the action of the bias circuit. The photoelectrons generated by the photodiode when irradiated by light migrate and accumulate on the bottom electrode under the action of the applied electric field. After the gate line controls the TFT to open, the electrons accumulated on the bottom electrode are read out through the TFT data line and converted into digital signals by the reading chip, and digital signal image processing is performed at the backend. During the above working process, when external light irradiates into the channel of the TFT through the device, it will cause the problem of photocurrent leakage in the TFT switching element.

[0003] Therefore, the present invention is proposed. Summary of the Invention

[0004] The main object of the present invention is to provide a flat panel detector and a detection device, which solve the leakage problem caused by light entering the transistor channel and also solve the light scattering problem between adjacent photodiodes (PINs).

[0005] In order to achieve the above object, the present invention provides the following technical solutions.

[0006] The first aspect of the present invention provides a flat panel detector, which includes a substrate; adjacent transistor regions and photodiode regions are provided on the substrate; a transistor and a black matrix layer are provided in the transistor region; the transistor includes a gate, a gate insulating layer, a source electrode, a drain electrode, and a channel layer, the gate is connected to a gate line, and the source electrode or the drain electrode is connected to a data line; the black matrix layer is disposed on a side of the channel layer away from the substrate, the black matrix layer is made of an insulating light-shielding material and includes a first part and a second part; a positive projection of the first part on the substrate covers a positive projection of the channel layer on the substrate, and the second part is laid along the routing of the data line and / or the gate line.

[0007] Therefore, a black matrix layer is provided on the incident light side of the flat panel detector in the present invention. Since the black matrix layer is made of an insulating light-shielding material, it can not only block light from entering the channel in the transistor, but also prevent the black matrix layer from forming a capacitor with each electrode in the transistor, thereby avoiding the problem of signal-to-noise ratio reduction caused by the capacitor. In addition, a part of the black matrix layer (i.e., the second part) is laid along at least one of the data line and the gate line, which can avoid the scattering of light between adjacent photodiodes (PINs), thus preventing light from irradiating the side wall of the PIN and ultimately improving the detection accuracy of a single pixel.

[0008] On this basis, further improvements can be made, such as the following examples.

[0009] The width W of the first part of the black matrix layer satisfies the following conditions:

[0010] W≥L + 2×H / tanα,

[0011] where L is the width of the channel layer, H is the vertical distance between the black matrix layer and the channel layer, and α is the angle between the incident light and the plane of the flat panel detector.

[0012] The present invention can block all the light effectively entering the channel by optimizing the width W of the black matrix layer.

[0013] Furthermore, W≤5μm. Controlling the width W of the first part of the black matrix layer below 5μm can avoid the problem of too low fill factor FF when it is too wide, thereby improving the detection sensitivity.

[0014] Furthermore, the flat panel detector further includes a bias voltage line, and a lower insulating layer, a middle insulating layer, and an upper insulating layer stacked in sequence from bottom to top above the transistor;

[0015] The photodiode region includes a bottom electrode, a photoelectric conversion layer, and a top electrode stacked from bottom to top;

[0016] The bottom electrode is connected to the source electrode of the transistor through a via in the lower insulating layer, and the bias voltage line is connected to the top electrode through a via in the middle insulating layer.

[0017] Furthermore, the black matrix layer is disposed between the lower insulating layer and the middle insulating layer where the bias voltage line is located. Generally, the lower the height, the smaller the required width of the black matrix layer. This solution precisely places the black matrix layer in a position closer to the bottom to reduce the width of the black matrix layer and ultimately achieve the effect of weight reduction.

[0018] Furthermore, the black matrix layer is disposed between the middle insulating layer and the upper insulating layer.

[0019] Further, the intermediate insulating layer includes a plurality of layers stacked in sequence from bottom to top, and at least one of the layers is integral with the black matrix layer.

[0020] Further, the intermediate insulating layer includes a second insulating layer, a third insulating layer, and a fourth insulating layer stacked in sequence from bottom to top, wherein the third insulating layer is integral with the black matrix layer.

[0021] In this way, unnecessary light can be blocked over a large area, so that when setting the bias voltage line, an aperture of any size can be opened above the top electrode in the photodiode region to receive light of different intensities, and thus a product that can be used for multiple purposes can be prepared. In addition, one manufacturing step can be reduced.

[0022] Further, it includes at least two photodiode regions; the bias voltage line is electrically connected to the top electrode through a via in the intermediate insulating layer; in different photodiode regions, the aperture of the via is different.

[0023] Further, the direction of the bias voltage line is parallel to the direction of the data line, or the direction of the bias voltage line is parallel to the direction of the gate line. Setting the directions of the wires in the detector parallel to each other can make the device wiring more regular and reduce the safety risk caused by chaotic wiring.

[0024] Further, one of the data line and the gate line is arranged in a staggered parallel manner with the bias voltage line. It is easy to generate a coupling capacitance between the gate line or the data line and the bias voltage line. At this time, if they are arranged in a "staggered parallel" manner, the overlapping area between them can be reduced, thereby reducing the coupling capacitance and reducing noise.

[0025] Further, the gate, the gate insulating layer, and the channel layer are stacked in sequence from bottom to top, the gate is close to the substrate, and the source and the drain are respectively located on the left and right sides of the channel layer; the first insulating layer covers the source, the channel layer, and the drain.

[0026] The second aspect of the present invention provides a detection device, which includes the flat panel detector of the first aspect.

[0027] In summary, compared with the prior art, the present invention achieves the following technical effects:

[0028] (1) Using an insulating light-shielding material to form the black matrix layer solves the leakage problem caused by light entering the transistor channel.

[0029] (2) The black matrix layer is laid along the routing of the data line and / or the gate line, which can avoid the scattering of light between PINs and prevent light from irradiating the sidewalls of the PINs, improving the detection accuracy of single-point pixels.

[0030] (3) Establish the correlation between the width of the black matrix layer, the incident angle of light, the width of the channel layer, and the set position, and design a more scientific and reasonable width of the black matrix layer to balance multiple performances such as low leakage and pixel fill factor FF;

[0031] (4) The set position of the black matrix layer can be flexibly adjusted to meet the requirements of different processes.

[0032] (5) The black matrix layer can also be integrated with the intermediate insulating layer, which can play a role in blocking light over a large area, making the set position of the bias voltage line and the size of the via aperture more flexible to adjust, so as to manufacture a product that can be used for multiple purposes.

[0033] (6) On the basis that the black matrix layer can cover the gate line or data line, there are more choices for the trend of the bias voltage line, which can be parallel to the data line or parallel to the gate line. Description of the Drawings

[0034] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention.

[0035] Figure 1 It is a schematic cross-sectional structure diagram of a flat panel detector provided by the present invention;

[0036] Figure 2 It is another schematic cross-sectional structure diagram of a flat panel detector provided by the present invention;

[0037] Figure 3 It is another schematic cross-sectional structure diagram of a flat panel detector provided by the present invention;

[0038] Figure 4 It is Figure 1 a top view of the flat panel detector shown;

[0039] Figure 5 It is Figure 4 a top view of the flat panel detector after removing the second part of the black matrix layer in

[0040] Figure 6 It is another top view of a flat panel detector provided by the present invention;

[0041] Figure 7 It is another top view of a flat panel detector provided by the present invention.

[0042] Reference Signs:

[0043] 1 - Substrate, 2 - Gate, 2' - Gate line, 3 - Gate insulating layer, 4 - Channel layer, 51 - Drain, 52 - Source, 52' - Data line, 6 - First insulating layer, 7 - Bottom electrode, 8 - Photoelectric conversion layer, 9 - Top electrode, 10 - Second insulating layer, 11 - Black matrix layer, 1101 - First part, 1102 - Second part, 12 - Third insulating layer, 13 - Fourth insulating layer, 14 - Bias voltage line, 15 - Fifth insulating layer, 16 - Sixth insulating layer, 1701, 1702 - Via hole.

[0044] Wherein, Figures 4 to 7 For clearly showing the structures described in the specification, perspective processing is performed on some layers, that is, the layers shown in the figure do not represent that the layer is located at the topmost of the detector. Detailed implementation manners

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0046] Schematic diagrams of various structures according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures and their relative sizes and positional relationships are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0047] In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0048] During the operation of the flat panel detector, if external light irradiates into the channel of the TFT through the device, it will cause the problem of photocurrent leakage in the TFT. To solve this problem, when making the bias voltage line on the photodiode, after synchronously depositing the conductive layer, through specific template etching, part of the conductive layer is used as the bias voltage line and part of the conductive layer is used as the shielding block to shield the light of the channel in the transistor. Although this structure blocks the light entering the TFT, it also couples with the channel or the source and drain in the TFT to form a capacitor, resulting in a decrease in the signal-to-noise ratio. For this reason, the present invention proposes a flat panel detector provided with a black matrix layer, which will be specifically introduced below.

[0049] Combination Figures 1 to 3 An introduction is made to a flat panel detector, which includes a substrate 1; adjacent transistor regions and photodiode regions are provided on the substrate 1; a transistor and a black matrix layer 11 are provided in the transistor region; the transistor includes a gate 2, a gate insulating layer 3, a source 52, a drain 51, and a channel layer 4; the black matrix layer 11 is provided on a side of the channel layer 4 away from the substrate 1, and the black matrix layer (BM) 11 is made of an insulating light-shielding material and includes a first part and a second part. A positive projection of the first part of the black matrix layer 11 on the substrate 1 covers a positive projection of the channel layer 4 on the substrate 1 (as the first part can be seen in the cross-sectional direction of Figure 1 ), and the first part can block light from entering the channel in the transistor, solving the leakage problem caused thereby. The second part of the black matrix layer 11 is laid along the routing of the data line and / or the gate line (as the first part 1101 and the second part 1102 can be seen in the top view direction of Figure 4 ), and the second part 1102 can avoid light scattering between adjacent photodiodes (PINs), thereby preventing light from irradiating the sidewalls of the PINs, and finally improving the detection accuracy of a single-point pixel. To clearly show the difference between the second part and the first part, the present invention also provides a schematic diagram of a detector in which the black matrix layer is only composed of the first part, as shown in Figure 5 i.e., the black matrix layer 11' only covers the channel of the transistor.

[0050] In the present invention, the laying of the second part 1102 of the black matrix layer 11 along the routing of the data line and / or the gate line includes the following three cases.

[0051] Case 1: The second part includes two branch routings, one branch is laid along the routing of the data line, and the other branch is laid along the routing of the gate line. Since the data line and the gate line are usually perpendicular to each other in routing, in this case, when viewed from the top view direction, the second part surrounds each photodiode region and is distributed in a grid pattern, for example, the detector shown in Figure 7 .

[0052] Case 2: The second part has only one branch routing, which is laid along the routing of the data line, for example, the detectors shown in Figure 4 and 6 .

[0053] Case 3: The second part has only one branch routing, which is laid along the routing of the gate line.

[0054] In the above Case 1, the black matrix layer surrounds the PIN unit, and in Case 2 and Case 3, the PINs are in a semi-surrounded form.

[0055] In the above, "line A is laid along the routing of line B" means that the extension directions of line A and line B are consistent, but there is no restriction on the size of the overlapping area of their orthographic projections on the substrate, and they can overlap completely, partially, or not at all. In some embodiments, the second portion of the black matrix layer 11 overlaps at least partially with the orthographic projection of the data line and / or gate line on the substrate, so that the second portion can act as an insulating layer between the bias voltage line and the gate or source and drain, reducing the coupling capacitance between the electrodes. For example, Figure 7 As shown, the orthographic projection of the second part of the black matrix layer 11 on the substrate covers the orthographic projection of the data line and the gate line 2' on the substrate (in order to show the routing of the gate line 2' and the bias voltage line 14, Figure 7 The black matrix layer blocked by the gate line 2' and the bias voltage line is not shown. Figure 4 and 6 , the orthographic projection of the second part of the black matrix layer 11 on the substrate only covers the orthographic projection of the data line on the substrate and only partially overlaps.

[0056] The above “coverage” regarding orthographic projection has the following meaning: if A covers B, it means that B is completely surrounded by A, and the area of A ≥ the area of B.

[0057] The above substrate 1 can be a flexible substrate 1 substrate, such as a plastic substrate with excellent heat resistance and durability made of polyethylene ether phthalate, polyethylene naphthalate, polycarbonate, polyarylate, polyetherimide, polyethersulfone or polyimide; it can also be a rigid substrate 1 substrate, such as a glass substrate, which is not limited here.

[0058] The black matrix layer 11 is made of insulating and light-shielding materials, which may be silicon oxide (SiO2), silicon oxynitride, silicon nitride (SiN x ) and resin and the like, preferably resin.

[0059] The present invention has no special requirements for the specific structure of the transistor, including but not limited to planar transistors, ring-gate transistors, fin transistors, etc., and has no special requirements for the material of the transistor, including but not limited to amorphous silicon thin film transistors, oxide thin film transistors, LTPS thin film transistors, etc. Regardless of the type of transistor, it is usually provided with four basic structures: gate 2, source 52, drain 51 and channel. In some embodiments, a planar transistor is used, and its preparation process is simpler, and the integration level meets the requirements of flat panel detectors. Planar transistors also include many types of structures, such as Figures 1 to 3In the structure shown, the gate 2, the gate insulating layer 3, and the channel layer 4 are stacked in sequence from bottom to top. The gate 2 is close to the substrate 1, and the source 52 and the drain 51 are respectively located on the left and right sides of the channel layer 4; the first insulating layer 6 covers the source 52, the channel layer 4, and the drain 51. The gate line connected to the gate is a conductive wire that leads the gate to the driving circuit. Usually, one gate line is connected to the gates of multiple transistors. The data line connects the source or the drain to the driving circuit. Usually, one data line is connected to the source / drain of multiple transistors.

[0060] In the present invention, a photodiode is provided in the photodiode region, which includes upper and lower electrodes and a photoelectric conversion layer 8 located in the middle. The photoelectric conversion layer 8 usually adopts a PIN structure.

[0061] Usually, different processes such as forming the two regions of the transistor region and the photodiode region in different layers successively or synchronously result in differences in the middle layer structure in the flat panel detector.

[0062] In some embodiments, the width of the first part of the black matrix layer 11 is also optimized. Specifically, the width W of the first part of the black matrix layer 11 satisfies the following condition: W≥L + 2×H / tanα. Wherein, L is the width of the channel layer 4, H is the vertical distance between the black matrix layer 11 and the channel layer 4, and α is the angle between the incident light and the plane of the flat panel detector.

[0063] The direction of the above "width" refers to the direction in which the drain 51, the channel layer 4, and the source 52 are connected in sequence. The width direction of the channel layer 4 is the same as the width direction of the first part of the black matrix layer 11. α usually refers to the maximum angle between the incident light and the plane of the flat panel detector. Taking Figure 2 the structure shown as an example, H, L’, and α are respectively marked. According to the incident path of the light, it can be determined that when W≥L + 2×L’, L’ = H / tanα, the first part of the black matrix layer 11 can almost completely block the light effectively entering the channel, thereby reducing the leakage problem to a greater extent. Although the larger W is, the larger the light shielding area is, but if W is too large, it will cause the reduction of the light transmission opening area in the photodiode region, and then lead to the reduction of the fill factor FF, and the device sensitivity will decrease accordingly. Therefore, in some embodiments, controlling the width W of the black matrix layer 11 to be below 5 μm can avoid the problem of too low fill factor FF when it is too wide.

[0064] In some embodiments, the flat panel detector further includes a bias voltage line, and a lower insulating layer, an intermediate insulating layer, and an upper insulating layer stacked in sequence from bottom to top above the transistor; the photodiode region includes a bottom electrode, a photoelectric conversion layer, and a top electrode stacked in sequence from bottom to top; the bottom electrode is connected to the source electrode of the transistor through a via in the lower insulating layer, and the bias voltage line is connected to the top electrode through a via in the intermediate insulating layer. Usually, the intermediate insulating layer and the photodiode are at substantially the same height, and the lower insulating layer is used for insulation between the transistor and the photodiode; the intermediate insulating layer serves as an insulating layer on the one hand, and a buffering and planarizing layer on the other hand, and the upper insulating layer is used for insulation of the photodiode. According to different process characteristics, the intermediate insulating layer can be composed of only one layer or multiple stacked layers. For example Figure 1 The flat panel detector shown includes a first insulating layer 6, a second insulating layer 10, a third insulating layer 12, a fourth insulating layer 13, and a fifth insulating layer 15 stacked in sequence from bottom to top. The first insulating layer 6 is the lower insulating layer, and the stack of the second insulating layer 10, the third insulating layer 12, and the fourth insulating layer 13 serves as the intermediate insulating layer, and the fifth insulating layer 15 is the upper insulating layer. At the same time, in Figure 1 , the photodiode region includes a bottom electrode 7, a photoelectric conversion layer 8, and a top electrode 9 stacked in sequence from bottom to top. The bottom electrode 7 is connected to the source electrode 52 of the transistor through a via in the first insulating layer 6, and the bias voltage line 14 is connected to the top electrode 9 through vias in the fourth insulating layer 13, the third insulating layer 12, and the second insulating layer 10. In some embodiments, a sixth insulating layer 16 is further provided above the fifth insulating layer 15 to complete the insulation encapsulation.

[0065] Taking Figure 1 as an example, the first insulating layer 6, the second insulating layer 10, the third insulating layer 12, the fourth insulating layer 13, and the fifth insulating layer 15 are usually formed successively in different steps, but can be made of the same or different materials, which can be silicon oxide (SiO2), silicon oxynitride, silicon nitride (SiN x ), and resin and other materials. In addition, the third insulating layer 12 is usually at the same height as the photoelectric conversion layer 8 in the photodiode region and occupies a relatively large volume. In order to achieve a good shockproof effect, the third insulating layer 12 can be made of a resin with better flexibility. The fourth insulating layer 13 is adjacent to the bias voltage line 14, and usually requires a high bonding force between the two and a high supporting strength for the fourth insulating layer 13. Therefore, materials such as silicon nitride are preferably used.

[0066] Since there are multiple layers of insulating layers covering the transistor, there are various choices for the setting position of the black matrix layer. For example, it can be set between the bias voltage line in the lower insulating layer and the intermediate insulating layer, or between the intermediate insulating layer and the upper insulating layer. Taking Figure 1Taking the five insulating layers shown as an example, the black matrix layer 11 can be disposed between the first insulating layer 6 and the second insulating layer 10, or between the second insulating layer 10 and the third insulating layer 12 (as Figure 1 shown), or between the third insulating layer 12 and the fourth insulating layer 13, or between the fourth insulating layer 13 and the fifth insulating layer 15 (as Figure 2 shown).

[0067] Among the above options, it is preferably disposed between the first insulating layer 6 and the second insulating layer 10, or between the second insulating layer 10 and the third insulating layer 12 (as Figure 1 shown), or between the third insulating layer 12 and the fourth insulating layer 13. In these settings, the black matrix layer 11 is located below the bias voltage line 14, and the following effects can be achieved: the external leakage of the bias voltage line 14 is convenient for identifying relevant defects, and it is also convenient for failure analysis and improvement after production. It can also reduce the light crosstalk between the pixels of the PIN detection unit.

[0068] In addition, the fill factor FF calculation formula of the flat panel detector is usually: (CD pin *CD pin -CD BM1* CD BM2 -CD BM1* (CD pin -CD BM1 ))*100% / (CD Pixcel *CD Pixcel ), where CD pin is the PIN CD of the pixel region, CD BM1 is the BM width, and CD BM2 is the BM length. It can be seen that the width of the black matrix layer 11 affects the fill factor of the detector, and the width of the black matrix layer 11 is related to its distance from the channel. Therefore, the distance between the black matrix layer 11 and the channel indirectly affects the FF.

[0069] Considering the influence of the distance between the black matrix layer 11 and the channel on the FF, taking the flat panel detector provided with the first to sixth insulating layers as an example, in some embodiments, the black matrix layer 11 is disposed between the first insulating layer 6 and the second insulating layer 10, or between the second insulating layer 10 and the third insulating layer 12, and at this time the fill factor FF of the detector is relatively high.

[0070] Therefore, this article also compares the fill factors of the detector when disposed at the following three positions: ① Disposed between the second insulating layer 10 and the third insulating layer 12 (as Figure 1as shown), ② is disposed between the fourth insulating layer 13 and the fifth insulating layer 15, and ③ is disposed above the fifth insulating layer 15. Taking industrial non-destructive testing application as an example for this comparative test, assume Pixel CD is 70μm ± 1μm, PIN CD is 50; assume α is 30°, then H / Tan30 is √3H; and assume the channel length L is a fixed value of 2.8μm ± 0.1μm, and the thicknesses of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are 0.4μm ± 0.01μm, 0.2μm ± 0.01μm, 2.1μm ± 0.01μm, 0.1μm ± 0.01μm, 1.0μm ± 0.01μm respectively. Usually, CD BM2 is CD BM1 twice that of, CD Pixcel is Pixel CD, and PIN CD is affected by the gate and data line wiring, and its value is 20μm smaller than Pixel CD.

[0071] First, calculate the minimum width of the black matrix layer (BM) at the above three positions according to the formula W = L + 2×H / tanα.

[0072] For ①, the designed width of BM is 2.8 + 2*(0.4 + 0.2)√3 = 4.88μm.

[0073] For ②, the designed width of BM is 2.8 + 2*(0.4 + 0.2 + 2.1 + 0.1)√3 = 12.50μm.

[0074] For ③, the designed width of BM is 2.8 + 2*(0.4 + 0.2 + 2.1 + 0.1 + 1)√3 = 15.96μm.

[0075] Secondly, calculate the theoretical FF value according to the BM width in the previous step.

[0076] For ①, FF = ((50*50 - 4.88*4.88*2 - 4.88(50 - 4.88))*100% / (70*70) = 45.6%.

[0077] For ②, FF = ((50*50 - 12.5*12.5*2 - 12.5(50 - 12.5))*100% / (70*70) = 35.1%.

[0078] For ③, FF = ((50*50 - 15.96*15.96*2 - 15.96(50 - 15.96))*100% / (70*70) = 29.5%.

[0079] It can be confirmed therefrom that as the distance between the BM and the channel increases, the fill factor FF of the detector decreases. Therefore, it is optimal to design the BM above the second insulating layer and the third insulating layer. Compared with setting the BM between the fourth insulating layer and the fifth insulating layer, the FF can be significantly increased by about 10%.

[0080] Although in the solutions introduced above, the black matrix layer and each insulating layer are independent layers, the present invention does not exclude the solution where the black matrix layer and some insulating layers are integrated. Here, "integrated" means that a certain insulating layer and the black matrix layer are the same structure, which is a layer formed of a material with insulating and light-absorbing characteristics. For example, in some embodiments, as Figure 3 shown, the third insulating layer 12 and the black matrix layer 11 are integrated and can be made of resin. In this way, unnecessary light can be blocked over a large area, thereby reducing the light crosstalk between different pixels and improving the spatial resolution of the flat panel detector. In some embodiments, the flat panel detector further includes at least two photodiode regions; the bias voltage line is electrically connected to the top electrode through a via in the intermediate insulating layer; in different photodiode regions, the via aperture is different. Thus, different intensities of light can be received in different regions of the flat panel detector, so a multi-functional product applicable to multiple working conditions or application scenarios can be obtained. And in these embodiments, since the black matrix and the insulating layer are an integrated structure, one manufacturing step can be saved, and the production cost can be reduced. As Figure 6 shown, when the bias voltage line passes through the via in the intermediate insulating layer and is connected to the top electrode, the via aperture is D. The flat panel detector includes at least two photodiode regions with different Ds, that is, it includes a via 1702 with a large aperture and a via 1701 with a small aperture. The via of the bias voltage line 14 in the middle row of pixel units is larger.

[0081] Regarding the routing directions of the bias voltage line, the gate line, and the data line in the flat panel detector, the present invention also provides some preferred solutions. For example, in some embodiments, as Figure 4 and 6 shown, the routing direction of the bias voltage line 14 is parallel to the routing direction of the data line 52'; or as Figure 7 shown, the routing direction of the bias voltage line 14 is parallel to the routing direction of the gate line 2'. This can make the device routing more regular and reduce the safety risk caused by chaotic routing. Here, "routing direction parallel" can be parallel and the orthographic projection does not completely overlap (such as Figure 4 and 6 are staggeredly parallel, that is, they do not completely overlap), or it can be parallel and the orthographic projection completely overlaps (such as Figure 7 shown, the routing direction of the bias voltage line 14 completely overlaps with the gate line 2').

[0082] In the above parallel wiring scheme, the following problems may exist: when the gate line or data line is not covered by the black matrix layer, a coupling capacitance is likely to be generated between it and the bias voltage line. Especially when the orthographic projection of the data line or gate line on the substrate is not covered by the orthographic projection of the second part of the black matrix layer on the substrate, the data line or gate line is preferably arranged in a misaligned parallel manner with the bias voltage line. In this way, the overlapping area of the orthographic projections of the data line / gate line and the bias voltage line is reduced, thereby reducing the coupling capacitance and noise. The "misaligned parallel arrangement" in the present invention means that two lines are parallel but their orthographic projections on the substrate do not completely overlap.

[0083] The flat panel detector of each of the above embodiments of the present invention can be formed by a layer-by-layer deposition method. The shape or wiring of each layer can be completed by means of masking, etching, etc. The manufacturing method of each layer can adopt CVD, PVD or solution method, etc. The present invention will not elaborate on this.

[0084] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A flat panel detector, characterized in that, Comprising a substrate; adjacent transistor regions and photodiode regions are provided on the substrate; a transistor and a black matrix layer are provided in the transistor region; the transistor includes a gate, a gate insulating layer, a source electrode, a drain electrode, and a channel layer, the gate is connected to a gate line, and the source electrode or the drain electrode is connected to a data line; the black matrix layer is disposed on a side of the channel layer away from the substrate, the black matrix layer is made of an insulating light-shielding material and includes a first part and a second part; a positive projection of the first part on the substrate covers a positive projection of the channel layer on the substrate, and the second part is laid along a routing of the data line and / or the gate line.

2. The flat panel detector according to claim 1, wherein The width W of the first part of the black matrix layer satisfies the following condition: W≥L + 2×H / tanα, wherein, L is the width of the channel layer, H is a vertical distance between the black matrix layer and the channel layer, and α is an angle between incident light and a plane of the flat panel detector.

3. The flat panel detector according to claim 1 or 2, characterized in that The flat panel detector further includes a bias voltage line, and a lower insulating layer, an intermediate insulating layer, and an upper insulating layer stacked in sequence from bottom to top above the transistor; The photodiode region includes a bottom electrode, a photoelectric conversion layer, and a top electrode stacked from bottom to top; The bottom electrode is connected to the source electrode of the transistor through a via in the lower insulating layer, and the bias voltage line is connected to the top electrode through a via in the intermediate insulating layer.

4. The flat panel detector according to claim 3, wherein, The black matrix layer is disposed between the lower insulating layer and the intermediate insulating layer where the bias voltage line is provided.

5. The flat panel detector according to claim 3, characterized in that, The black matrix layer is disposed between the intermediate insulating layer and the upper insulating layer.

6. The flat panel detector according to claim 3, characterized in that The intermediate insulating layer includes a second insulating layer, a third insulating layer, and a fourth insulating layer stacked in sequence from bottom to top, wherein the third insulating layer and the black matrix layer are integrated.

7. The flat panel detector according to claim 6, wherein Including at least two photodiode regions; The bias voltage line is electrically connected to the top electrode through a via on the intermediate insulating layer; in different photodiode regions, the via aperture is different.

8. The flat panel detector according to claim 3, characterized in that, The routing of the bias voltage line is parallel to the routing of the data line, or the routing of the bias voltage line is parallel to the routing of the gate line.

9. The flat panel detector according to claim 3, characterized in that, One of the data line and the gate line is disposed in a staggered parallel manner with the bias voltage line.

10. A detection device, characterized in that, Including the flat panel detector according to any one of claims 1-9.

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