Tunneling oxide layer of TOPCon battery and preparation method and application thereof
By controlling the ratio of alkali etching and PECVD oxidation processes, the method addresses uneven tunnel oxide layer thickness in TOPCon solar cells, reducing stone boat sticking and improving efficiency and yield.
Patent Information
- Application Number
- CN202510434036.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-27
- Filing Date
- 2025-04-08
- Publication Date
- 2025-07-15
AI Technical Summary
The existing TOPCon batteries have problems with blocking and printing during the tunneling oxide layer preparation process, resulting in low battery yield, especially the high blocking and printing ratio of graphite boats.
By controlling the thickness ratio of the alkali-throwing oxide layer formed by alkali-throwing treatment and PECVD oxidation treatment to the PECVD oxidation layer, the thickness uniformity of the tunneling oxide layer is ensured. Pickling reagents that do not react with silicon oxide, such as hydrochloric acid, are used to combine PECVD oxidation treatment under specific process conditions to form a tunneling oxide layer with uniform thickness.
It effectively reduces the blocking ratio and improves the battery yield, especially in long-term production, which is stably controlled below 0.1%, and the battery efficiency and filling factor have also been significantly improved.
Smart Images
Figure CN120322045A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of batteries, and in particular relates to a tunneling oxide layer of a TOPCon battery, a preparation method thereof, and an application thereof. Background Art
[0002] The tunneling oxide passivated contact (TOPCon) battery structure proposed by the Fraunhofer ISE Research Institute in Germany not only has excellent surface passivation characteristics of HIT technology, but also is compatible with the manufacturing process flow of N-PERT / PERL batteries. For the TOPCon battery structure, the energy band bending at the interface caused by the work function difference between the highly doped polycrystalline silicon (Poly-Si) layer and the n-type silicon substrate reduces the electron transport barrier, making it easier for electrons to tunnel; while the valence band edge occupied by holes is in the forbidden band of Poly-Si and is not easy to tunnel, effectively reducing the surface minority carrier recombination rate and enhancing the passivation effect of the back surface. The tunneling oxide layer passivated contact technology is one of the new technologies that are key research in the domestic photovoltaic industry, and the doping concentration distribution of the back surface plays a key role in its passivation characteristics. Among them, the tube PECVD equipment technology has comprehensive advantages in preparing ultra-thin silicon oxide layers and heavily doped polycrystalline silicon with low cost and high performance for TOPCon solar cells. It is more efficient in realizing key steps such as amorphous silicon layer deposition and in-situ doping. It not only integrates the in-situ preparation of ultra-thin silicon oxide layers and doped amorphous silicon layers, but also has the advantages of low equipment price, easy maintenance, high reliability, and small floor area.
[0003] In the currently widely used tube PECVD equipment for depositing amorphous silicon, the silicon wafer carrier used is a graphite boat, which has a low cost, but there are also many problems: such as a high proportion of sticking marks on the graphite boat, resulting in a low product yield. How to avoid the occurrence of such problems from the perspective of process optimization is an important research direction for improving the process yield of battery wafers. Summary of the Invention
[0004] In order to overcome at least one of the above-mentioned problems existing in the prior art, one of the objectives of the present invention is to provide a preparation method for a tunneling oxide layer of a TOPCon battery, which is beneficial to obtaining a tunneling oxide layer with good thickness uniformity, and further obtaining a TOPCon battery with a low proportion of sticking marks and a high battery yield.
[0005] The second objective of the present invention is to provide a tunneling oxide layer of a TOPCon battery prepared by the above-mentioned preparation method.
[0006] The third objective of the present invention is to provide a TOPCon battery including the above-mentioned tunneling oxide layer.
[0007] The fourth objective of the present invention is to provide a preparation method for the above-mentioned TOPCon battery.
[0008] To achieve the above object, the technical solution adopted by the present invention is as follows:
[0009] A first aspect of the present invention provides a method for preparing a tunneling oxide layer of a TOPCon cell, comprising the following steps: subjecting a pre-treated silicon wafer to alkali polishing treatment and PECVD oxidation treatment in sequence to obtain the tunneling oxide layer; wherein, an alkali polishing oxide layer is formed after the alkali polishing treatment, and a PECVD oxide layer is formed after the PECVD oxidation treatment, and the average thickness ratio of the alkali polishing oxide layer to the PECVD oxide layer is 1:(0.01 - 0.5); the average thickness of the alkali polishing oxide layer ≥ 1 nm.
[0010] Through tracking tests, the present invention finds that the key step causing the existence of stuck point marks in TOPCon cells is the preparation process of the tunneling oxide layer, and the tunneling oxide layer is composed of an alkali polishing oxide layer formed after alkali polishing treatment and a PECVD oxide layer formed by PECVD oxidation treatment. If the thickness proportion of the PECVD oxide layer is larger, the thickness difference of the tunneling oxide layer between the stuck point position and the non-stuck point position is also larger, which is likely to cause the generation of stuck point marks. Therefore, by means of alkali polishing treatment and PECVD oxidation treatment, controlling the thickness of the alkali polishing oxide layer and its ratio to the thickness of the PECVD oxide layer, a tunneling oxide layer with good thickness uniformity can be obtained, thereby effectively reducing the generation of stuck point marks.
[0011] Preferably, the average thickness of the alkali polishing oxide layer is 1 - 2.4 nm.
[0012] Preferably, the average thickness of the PECVD oxide layer is 0.01 - 1.5 nm.
[0013] Preferably, the total thickness of the tunneling oxide layer is 1 - 3 nm.
[0014] Preferably, the process of the alkali polishing treatment includes pickling treatment, and the reagent used in the pickling treatment does not react with silicon oxide.
[0015] Preferably, the reagent used in the pickling treatment does not contain hydrofluoric acid; further preferably, the reagent used in the pickling treatment contains at least one of hydrochloric acid, sulfuric acid, nitric acid, acetic acid or hypochlorous acid.
[0016] Preferably, the silicon wafer obtained after the pickling treatment is placed in the air for oxidation for 0 - 100 min.
[0017] Preferably, the deposition time used in the PECVD oxidation treatment is 50 - 200 s.
[0018] Preferably, the radio frequency power used in the PECVD oxidation treatment is 5000 - 20000 W.
[0019] Preferably, the gas flow rate used in the PECVD oxidation treatment is 5000 - 20000 sccm.
[0020] Preferably, the pressure used in the PECVD oxidation treatment is 800 - 2500 mTorr.
[0021] The second aspect of the present invention provides a tunneling oxide layer prepared by the preparation method as described in the first aspect of the present invention.
[0022] The third aspect of the present invention provides a TOPCon cell, which includes the tunneling oxide layer as described in the second aspect of the present invention.
[0023] Preferably, the sticking point printing ratio of the TOPCon cell is ≤ 0.1%.
[0024] The fourth aspect of the present invention provides a preparation method of the TOPCon cell as described in the third aspect of the present invention, including the following steps: subjecting the silicon wafer to be processed to pre-treatment, alkaline polishing treatment, PECVD oxidation treatment and post-treatment in sequence to obtain the TOPCon cell.
[0025] Preferably, the post-treatment includes laser-assisted sintering treatment.
[0026] The beneficial effects of the present invention are: through alkaline polishing treatment and PECVD oxidation treatment, the present invention controls the thickness of the alkaline polishing oxide layer and its ratio to the thickness of the PECVD oxide layer, and can form a tunneling oxide layer with good uniformity, which is beneficial to reducing the influence of the sticking points of the graphite boat on the silicon wafer, and further obtaining a TOPCon cell with a low sticking point printing ratio.
[0027] Specifically, compared with the prior art, the present invention has the following advantages:
[0028] 1. The reagent used in the pickling process of the present invention does not react with silicon oxides. For example, in the hydrochloric acid pickling route, the alkaline polishing oxide layer can be effectively retained. Combined with the PECVD oxidation treatment under specific process conditions, the sticking point printing ratio can be effectively reduced. During the long-term production process, the sticking point printing ratio can be stably controlled below 0.1%, and can be reduced to 0% at the lowest, with good production stability and high battery yield.
[0029] 2. The TOPCon cell obtained by the present invention has a low sticking point printing ratio and good electrical performance, especially high battery efficiency, fill factor and external quantum efficiency. Description of the Drawings
[0030] Figure 1 It is a schematic structural diagram of a TOPCon cell in some embodiments of the present invention.
[0031] Figure 2This is the EL image of the contact points on the back surface of the TOPCon cell in some embodiments of the present invention.
[0032] Figure 3 This is the distribution map of the contact points of the graphite boat in some embodiments of the present invention.
[0033] Figure 4 This is the external quantum efficiency map of the cell with contact point printing in some embodiments of the present invention.
[0034] Figure 5 This is the test result of the thickness of the alkali-polished oxide layer every 20 minutes under different pickling methods in Example 1 and Comparative Example 1.
[0035] Figure 6 This is the trend map of the contact point printing of the cells obtained by different pickling methods in Example 1 and Comparative Example 1. Detailed implementation manners
[0036] The content of the present invention will be further described in detail through specific embodiments below. It should also be understood that the following embodiments are only used to further illustrate the present invention and cannot be construed as limiting the protection scope of the present invention. Some non-essential improvements and adjustments made by those skilled in the art based on the principles described in the present invention fall within the protection scope of the present invention. The specific process parameters and the like in the following examples are only an example within a suitable range, that is, those skilled in the art can make selections within a suitable range through the description in this article, rather than being limited to the specific data in the following examples. The raw materials, reagents or devices used in the following examples and comparative examples can be obtained from conventional commercial channels or can be obtained by existing known methods without special instructions.
[0037] The first aspect of the embodiment of the present invention provides a method for preparing a tunneling oxide layer of a TOPCon cell, including the following steps: successively performing alkali polishing treatment and PECVD oxidation treatment on the pretreated silicon wafer to obtain the tunneling oxide layer; wherein, an alkali-polished oxide layer is formed after the alkali polishing treatment, and a PECVD oxide layer is formed after the PECVD oxidation treatment, and the average thickness ratio of the alkali-polished oxide layer to the PECVD oxide layer is 1:(0.01 - 0.5); the average thickness of the alkali-polished oxide layer ≥ 1 nm.
[0038] Contact point printing refers to the EL defect existing on the cell, which is caused by the contact between the cell and the contact points of the graphite boat during the preparation process of the cell. There are mainly the following three types of contact point printing: single contact point printing (only the contact point position is bright, without other defects), black edge contact point printing (the contact point position is bright and the edge of the cell is black), and dark sheet contact point printing (the contact point position is bright and the whole surface of the cell is black), and the first two types account for the vast majority.
[0039] Through tracking tests, the present invention finds that the key step causing pinholes in TOPCon cells is the preparation process of the tunneling oxide layer, which is composed of an alkaline-etched oxide layer formed after alkaline etching treatment and a PECVD oxide layer formed by PECVD oxidation treatment. If the proportion of the PECVD oxide layer thickness is larger, the thickness difference of the tunneling oxide layer at the pinhole position and the non-pinhole position is also larger, which is likely to lead to the generation of pinholes. Therefore, through alkaline etching treatment and PECVD oxidation treatment, controlling the thickness of the alkaline-etched oxide layer and its ratio to the PECVD oxide layer thickness can obtain a tunneling oxide layer with good thickness uniformity, thereby effectively reducing the generation of pinholes.
[0040] Figure 1 FIG. [ID] is a schematic structural diagram of a TOPCon cell in some embodiments of the present invention, which is composed of a front surface structure, an n-type silicon substrate, and a back surface structure. The front surface structure includes an electrode (such as an Ag / Al electrode), a mask (SiN x :H), a passivation layer (AlO3), and an emitter (p). The back surface structure includes a tunneling oxide layer (SiOx), a doped polysilicon layer (Poly-Si), a mask (SiN x :H), and an electrode (such as an Ag electrode). The present invention mainly aims to improve the performance of the tunneling oxide layer in the back surface structure of the TOPCon cell structure.
[0041] In some embodiments of the present invention, the average thickness of the alkaline-etched oxide layer is 1-2.4 nm; in some specific embodiments of the present invention, the average thickness of the alkaline-etched oxide layer is 1.1-2 nm; in some examples of the present invention, the average thickness of the alkaline-etched oxide layer is 1.2-1.6 nm; non-limiting examples are 1.3 nm, 1.4 nm, or 1.5 nm.
[0042] In some embodiments of the present invention, the average thickness of the PECVD oxide layer is 0.01-1.5 nm; in some specific embodiments of the present invention, the average thickness of the PECVD oxide layer is 0.05-1.2 nm; in some examples of the present invention, the average thickness of the PECVD oxide layer is 0.1-0.6 nm; non-limiting examples are 0.2 nm, 0.3 nm, 0.4 nm, or 0.5 nm.
[0043] In some embodiments of the present invention, the ratio of the average thickness of the alkaline-etched oxide layer to the PECVD oxide layer is 1:(0.05-0.47); in some specific embodiments of the present invention, the ratio of the average thickness of the alkaline-etched oxide layer to the PECVD oxide layer is 1:(0.08-0.44); in some examples of the present invention, the ratio of the average thickness of the alkaline-etched oxide layer to the PECVD oxide layer is 1:(0.1-0.42); non-limiting examples are 1:0.2, 1:0.3, 1:0.35, or 1:0.4.
[0044] In some embodiments of the present invention, the total thickness of the tunneling oxide layer is 1 - 3 nm; in some specific embodiments of the present invention, the total thickness of the tunneling oxide layer is 1 - 2.7 nm; in some examples of the present invention, the total thickness of the tunneling oxide layer is 1.5 - 2.5 nm; non-limiting examples are 1.6 nm, 1.8 nm, 2 nm, 2.2 nm or 2.4 nm.
[0045] In the embodiments of the present invention, after the alkali polishing treatment, the alkali polishing oxide layer formed on the surface of the silicon wafer has good uniformity, can effectively protect the silicon interface, and reduce the influence of environmental humidity, temperature, cleanliness, etc. on the interface. However, the growth of the PECVD oxide layer is easily affected by the PECVD oxidation treatment process, which easily leads to uneven growth of the PECVD oxide layer. For example, when there is a difference in the electric field strength between the stuck point position and the non-stuck point position, it is easy to cause a difference in the thickness of the PECVD oxide layer, and finally the ohmic contact at the stuck point position is better than the area around the stuck point. Furthermore, after the EL test, an image with different brightnesses is presented, forming a stuck point mark where the stuck point is bright and the area around the stuck point is dark. Therefore, since the tunneling oxide layer is composed of the alkali polishing oxide layer and the PECVD oxide layer, when the total thickness of the tunneling oxide layer is the same, controlling the formation of a thicker alkali polishing oxide layer can reduce the requirement for the thickness of the PECVD oxide layer, thereby maintaining the uniformity of the thickness of the tunneling oxide layer and avoiding the generation of stuck point marks.
[0046] In some embodiments of the present invention, the process of the alkali polishing treatment includes pickling treatment, and the reagent used in the pickling treatment does not react with silicon oxide.
[0047] An alkali polishing oxide layer will be formed on the surface of the silicon wafer during the alkali polishing treatment. The main component of the alkali polishing oxide layer is silicon oxide (SiOx). And the process of the alkali polishing treatment includes pickling treatment. If the reagent used in the pickling treatment reacts with silicon oxide, the thickness of the alkali polishing oxide layer will be reduced, which is not conducive to obtaining a tunneling oxide layer with good uniformity.
[0048] In some embodiments of the present invention, the reagent used in the pickling treatment does not contain hydrofluoric acid.
[0049] Since hydrofluoric acid will react with silicon oxide, if the reagent used in the pickling treatment contains hydrofluoric acid, the thickness of the alkali polishing oxide layer will be reduced, which is not conducive to obtaining a tunneling oxide layer with good uniformity.
[0050] In some specific embodiments of the present invention, the reagent used in the pickling treatment contains at least one of hydrochloric acid, sulfuric acid, nitric acid, acetic acid or hypochlorous acid; in some examples of the present invention, the reagent used in the pickling treatment contains hydrochloric acid.
[0051] In some embodiments of the present invention, the silicon wafers obtained after pickling treatment are placed in the air for oxidation for 0 to 100 minutes; in some embodiments of the present invention, the silicon wafers obtained after pickling treatment are placed in the air for oxidation for 0 to 80 minutes; non-limiting examples are 20 minutes, 40 minutes or 60 minutes.
[0052] The silicon wafers after pickling treatment will undergo natural oxidation when exposed to the air, thereby increasing the thickness of the alkaline polishing oxide layer.
[0053] In some embodiments of the present invention, the deposition time used for PECVD oxidation treatment is 50 to 200 s; in some embodiments of the present invention, the deposition time used for PECVD oxidation treatment is 90 to 120 s; non-limiting examples are 100 s, 105 s or 110 s.
[0054] In some embodiments of the present invention, the radio frequency power used for PECVD oxidation treatment is 5000 to 20000 W; in some embodiments of the present invention, the radio frequency power used for PECVD oxidation treatment is 9000 to 11000 W; non-limiting examples are 9800 W, 10000 W or 10200 W.
[0055] In some embodiments of the present invention, the gas flow rate used for PECVD oxidation treatment is 5000 to 20000 sccm; in some embodiments of the present invention, the gas flow rate used for PECVD oxidation treatment is 9000 to 11000 sccm; non-limiting examples are 9800 sccm, 10000 sccm or 10200 sccm.
[0056] In some embodiments of the present invention, the pressure used for PECVD oxidation treatment is 800 to 2500 mTorr; in some embodiments of the present invention, the pressure used for PECVD oxidation treatment is 1600 to 2000 mTorr; non-limiting examples are 1750 mTorr, 1800 mTorr or 1850 mTorr.
[0057] The second aspect of the embodiments of the present invention provides a tunneling oxide layer of a TOPCon cell prepared by the preparation method provided in the first aspect of the embodiments of the present invention.
[0058] This tunneling oxide layer has good thickness uniformity, which is beneficial to reducing the proportion of stuck point prints of TOPCon cells and improving the yield of the cells.
[0059] The third aspect of the embodiments of the present invention provides a TOPCon cell, which includes the tunneling oxide layer described in the second aspect of the embodiments of the present invention.
[0060] In some embodiments of the present invention, the proportion of stuck points printing of the TOPCon cell ≤ 0.1%; non-limiting examples are 0%, 0.01%, 0.05% or 0.08%.
[0061] The fourth aspect of the embodiments of the present invention provides a method for preparing the TOPCon cell described in the third aspect of the embodiments of the present invention, including the following steps: performing pre-treatment, alkaline polishing treatment, PECVD oxidation treatment and post-treatment on the silicon wafer to be processed in sequence to obtain the TOPCon cell.
[0062] In some specific embodiments of the present invention, the thickness of the silicon wafer to be processed is 120 - 140 μm, non-limiting examples are 125 μm, 130 μm or 135 μm.
[0063] In some specific embodiments of the present invention, the size of the silicon wafer to be processed is (180 - 250) mm × (180 - 250) mm; in some examples of the present invention, the size of the silicon wafer to be processed is (182 - 210) mm × (182 - 210) mm; non-limiting example is 182.2 mm × 182.2 mm.
[0064] In some specific embodiments of the present invention, the resistivity of the silicon wafer to be processed is 0.5 - 1.5 Ω·cm; non-limiting example is 1.0 Ω·cm.
[0065] In some specific embodiments of the present invention, the silicon wafer to be processed is an n-type commercially available Czochralski (Cz) silicon wafer.
[0066] The general preparation process of the TOPCon cell includes: texturing, boron diffusion, laser, oxidation, alkaline polishing treatment, PE-Poly deposition (including tunneling oxide layer deposition and doped polysilicon layer deposition, in the embodiments of the present invention, the tunneling oxide layer is deposited by PECVD oxidation treatment, and the doped polysilicon layer is deposited by PECVD doping treatment), annealing, RCA cleaning, coating and screen printing, etc.
[0067] In some embodiments of the present invention, the pre-treatment includes texturing, boron diffusion, laser SE, oxidation; in some other embodiments of the present invention, the pre-treatment includes texturing, boron diffusion.
[0068] In some embodiments of the present invention, the post-treatment includes laser-assisted sintering treatment (LECO).
[0069] Adopting laser-assisted sintering treatment (LECO) in the post-treatment can improve the contact between the metal electrode and the silicon wafer, and cooperate with the alkaline polishing oxide layer and PECVD oxide layer with a specific structure of the present invention to improve the electrical performance of the cell, thereby obtaining a TOPCon cell with better comprehensive performance.
[0070] In some embodiments of the present invention, the post-treatment includes PECVD doping treatment, annealing, RCA cleaning, coating, and screen printing; in some other embodiments of the present invention, the post-treatment includes PECVD doping treatment, annealing, RCA cleaning, coating, screen printing, and LECO (laser-assisted sintering).
[0071] In some embodiments of the present invention, the method for preparing a TOPCon cell includes the following steps: successively performing texturing, boron diffusion, laser SE, oxidation, alkaline polishing treatment, PECVD oxidation treatment, PECVD doping treatment, annealing, RCA cleaning, coating, and screen printing on the silicon wafer to be treated; in some other embodiments of the present invention, the method for preparing a TOPCon cell includes the following steps: successively performing texturing, boron diffusion, alkaline polishing treatment, PECVD oxidation treatment, PECVD doping treatment, annealing, RCA cleaning, coating, screen printing, and LECO (laser-assisted sintering) on the silicon wafer to be treated.
[0072] In some specific embodiments of the present invention, the annealing is carried out in a protective gas atmosphere; the protective gas atmosphere includes but is not limited to nitrogen and helium.
[0073] In some specific embodiments of the present invention, the annealing temperature is 850 - 950 °C; non-limiting examples are 880 °C, 900 °C, or 920 °C.
[0074] In some specific embodiments of the present invention, the annealing time is 20 - 30 min; non-limiting examples are 22 min, 25 min, or 28 min.
[0075] The doped phosphorus atoms can be activated through the annealing process.
[0076] The present invention is mainly aimed at improving the performance of the back surface structure of TOPCon cells, and the stuck point print is one of the common EL defects of the back surface structure of TOPCon cells. To solve this defect problem, it is necessary to first analyze the causes of this defect. Through tracking tests, the present invention finds that the key step causing the stuck point print in TOPCon cells is the preparation process of the tunneling oxide layer.
[0077] In some examples of the present invention, the method for preparing a TOPCon cell includes the following steps: successively performing texturing, boron diffusion, laser SE, oxidation, alkaline polishing treatment, PE-Poly deposition (including PECVD oxidation treatment and PECVD doping treatment), annealing, RCA cleaning, coating, and screen printing on the silicon wafer to be treated; the tracking tests for analyzing the causes of the stuck point print in this process include electroluminescence (EL) imaging, electrical performance testing, and comparative experiment testing, which are specifically as follows:
[0078] (1) Electroluminescence (EL) imaging: Figure 2It is the EL image of the sticking point printing on the back surface of the TOPCon cell in some embodiments. Figure 3 It is the distribution map of the sticking points of the graphite boat in some embodiments. Figure 2 In [reference], the sticking point printing shows a crescent-shaped white and bright appearance at 3 positions, which Figure 3 completely coincides with the sticking point positions of the graphite boat in [reference]. The defective sticking point printing mainly shows 3 types on the production line: single-type sticking point printing (only the sticking point position is bright, without other defects), black-edge type sticking point printing (the sticking point position is bright and the edge of the cell is blackened), and dark-chip type sticking point printing (the sticking point position is bright and the whole surface of the cell is blackened). Among them, the first two types account for the vast majority.
[0079] (2) Electrical performance test: Control the PE-Poly deposition process and its subsequent processes to be consistent, test several cells in the same graphite boat, screen out the cells with sticking point printing according to the EL imaging, and randomly select 3 cells with sticking point printing (denoted as sticking point printing 1-3) for electrical performance test, and compare the electrical performance with the remaining samples without sticking point printing (denoted as without sticking point printing). The electrical performance data of the cells with and without sticking point printing are shown in Table 1. Eta is the efficiency of the cell, Uoc is the open-circuit voltage, Isc is the short-circuit current, FF is the fill factor, Rs is the series resistance, Rsh is the parallel resistance, and IRev2 is the reverse current.
[0080] Table 1 Electrical performance data of cells with and without sticking point printing
[0081] Group Eta / % Uoc / V Isc / A FF / % Rs / Ω Rsh / Ω IRev2 / A No stuck stamp 25.96 0.722 13.738 86.46 0.00136 4646 0.0885 Stuck stamp 1 25.26 0.724 13.765 83.77 0.00172 5024 0.0654 Stuck stamp 2 24.59 0.721 13.744 81.99 0.00201 4498 0.0916 Stuck stamp 3 25.32 0.722 13.728 84.41 0.00146 5093 0.1551
[0082] As can be seen from Table 1, the efficiency of the cells in the sticking point printing 1-3 groups is between 24.59% and 25.26%, which is 0.64%-1.37% lower than that of the normal cells in the group without sticking point printing. Among them, there is no obvious difference in the open-circuit voltage and short-circuit current between the two, and the difference is mainly reflected in the significant decrease in the fill factor FF of the sticking point printing 1-3 groups. The fill factor of the sticking point printing 1-3 groups is 81.99%-84.41%, which is 2.05%-4.47% lower than that of the group without sticking point printing. Further test analysis shows that the abnormal series resistance is one of the factors leading to the low fill factor of the sticking point printing 1-3 groups. As can be seen from Table 1, the series resistance of the group without sticking point printing is 0.00136 Ω, while the series resistance of the sticking point printing 1-3 groups is between 0.00146 and 0.00201 Ω, all higher than that of the group without sticking point printing.
[0083] Furthermore, the electrical performance test also includes the external quantum efficiency (EQE) test: Take the cells with sticking point printing, and conduct the external quantum efficiency (EQE) test on the sticking point printing area and the non-sticking point printing area. The results are as Figure 4As shown. The external quantum efficiency of the card point print area in the medium and long wave range of 800-1100nm is significantly lower than that in the normal area. Since long-wave light has the characteristic of strong diffraction ability, it is easy to pass through the surface of the battery and reach the back of the battery to be absorbed. Therefore, due to the poor long-wave response of the EQE in the card point print area, the card point print will be generated on the back of the battery.
[0084] (3) Comparative experimental test: Test and analyze the key processes that produce the card point print. The processes where the back of the cell contacts the graphite boat card point include PE-Poly deposition and back silicon nitride. The experiment is designed to rotate the silicon wafer 90° after the PE-Poly deposition process and then transfer it to the back film. The card point positions of the two processes are staggered, and the overlap of the battery EL map is compared. Finally, the card point print is locked in the PE-Poly deposition process. The specific process of the PE-Poly deposition process is as follows: first, the laughing gas reacts with the silicon substrate to generate a 0.2-1.2nm tunneling oxide layer SiOx, then silane, hydrogen and phosphine react to generate a doped amorphous silicon doping layer, and finally silane and laughing gas generate a silicon oxide mask layer. The mask layer will eventually be corroded in the RCA process, so the process that produces the card point print is locked in the tunneling oxide layer deposition and the doped polysilicon layer deposition.
[0085] Repeated tracking revealed that the cells with a high proportion of stuck point printing were caused by the PE-Poly deposition process, which was carried out in the PECVD furnace tube equipment. According to the tracking test of two PECVD furnace tube equipment (the proportion of stuck point printing of cells produced by furnace tube A was high, and the proportion of stuck point printing of cells produced by furnace tube B was not), the film layer comparison verification experiment was designed: furnace tube A (the proportion of stuck point printing of cells produced was high) and furnace tube B (the proportion of stuck point printing of cells produced) jumped out of the boat after each deposition of the tunnel oxide layer, and the doped polysilicon layer was deposited after the furnace tubes were exchanged. The results of repeated multiple times showed that the tunnel oxide layer deposited in furnace tube A (the proportion of stuck point printing of cells produced) had stuck point printing no matter which device was used to deposit the doped polysilicon layer, while the tunnel oxide layer deposited in furnace tube B (the proportion of stuck point printing of cells produced) had no stuck point printing no matter which device was used to deposit the doped polysilicon layer, so it can be concluded that the key process for producing stuck point printing is the tunnel oxide layer deposition.
[0086] The thickness and state of the tunneling oxide layer are the result of the combined effect of the alkali-polished oxide layer formed after alkali polishing treatment and the PECVD oxide layer formed by PECVD oxidation treatment in the PE-Poly deposition process. Therefore, in addition to paying attention to the influence of the furnace tube hardware state on the tunneling oxide layer, we must also pay attention to the stability of the alkali-polished oxide layer formed by alkali polishing treatment.
[0087] The following is a further description with reference to specific embodiments and comparative examples.
[0088] Example 1
[0089] A preparation method of TOPCon battery, comprising the following steps:
[0090] (1) Sequentially perform texturing, boron diffusion, laser SE, and oxidation: conventional preparation process.
[0091] (2) Alkaline polishing treatment: including the processes of alkaline polishing, post - cleaning, and pickling treatment in sequence. After the post - cleaning process is completed, a primitive oxide layer will be formed on the back surface of the silicon wafer. Then, pickling treatment is carried out using a reagent containing hydrochloric acid to form an alkaline - polished oxide layer.
[0092] (3) PE - Poly deposition (including PECVD oxidation treatment and PECVD doping treatment in sequence. Through PECVD oxidation treatment, a PECVD oxide layer is formed, and through PECVD doping treatment, a doped polysilicon layer is formed): carried out using a tube - type PECVD equipment produced by Shenzhen Jiejiawei New Energy Equipment Co., Ltd. Deposit the PECVD oxide layer to form a PECVD oxide layer with a thickness of 0.2 - 1.2 nm, and deposit an in - situ doped polysilicon layer (n+-a - Si:H) with a thickness of about 100 nm. Among them, the deposition time of the PECVD oxide layer is 95 s, the power is 10000 W, the gas flow rate is 10000 sccm, and the pressure is 1800 mttor.
[0093] (4) Annealing: perform high - temperature annealing at 900 °C for 25 min in a nitrogen atmosphere to activate the doped phosphorus atoms.
[0094] (5) Sequentially perform RCA cleaning, coating, and screen printing: conventional preparation process.
[0095] Comparative Example 1
[0096] A preparation method of TOPCon battery, different from Example 1 in that in step (2), pickling treatment is carried out using a reagent containing hydrofluoric acid, and other steps are the same as those in Example 1.
[0097] Performance test
[0098] (1) Test on the growth rate of the alkaline - polished oxide layer
[0099] Take out the silicon wafers obtained by the two different pickling treatment methods in step (2) of Example 1 and Comparative Example 1. The silicon wafers after pickling treatment will undergo natural oxidation when exposed to air. Use a full - spectrum ellipsometer to monitor the thickness of the alkaline - polished oxide layer, and compare the growth rates of the alkaline - polished oxide layers of the two silicon wafers. Figure 5The test results of the thickness of the alkali-polished oxide layer every 20 minutes under different pickling methods, where SiOx-HCL represents the thickness of the alkali-polished oxide layer corresponding to pickling with hydrochloric acid, and SiOx-HF represents the thickness of the alkali-polished oxide layer corresponding to pickling with hydrofluoric acid. From Figure 5 It can be seen that the initial thickness after pickling with hydrofluoric acid is 0.53 nm, and the initial thickness after pickling with hydrochloric acid is 1.25 nm. This is because hydrofluoric acid will react with the original oxide layer, resulting in a thinner alkali-polished oxide layer, while hydrochloric acid does not react with the original oxide layer and retains a thicker alkali-polished oxide layer. Within 80 minutes of exposure to air, the film thickness production trends and rates of SiOx-HCL and SiOx-HF are close. SiOx-HCL shows an obvious inflection point at the 80th minute, the growth of the alkali-polished oxide layer slows down, and the film thickness stabilizes at 1.52 nm, while the film thickness growth rate of SiOx-HF does not show a slowing trend. The data shows that the stability of SiOx-HCL is better than that of SiOx-HF, and it is less affected by the changes in temperature and humidity in the workshop environment.
[0100] (2) Stuck point printing ratio test
[0101] Set production lines using two different pickling methods of Example 1 and Comparative Example 1, monitor and test the stuck point printing ratios of the batteries obtained on different production days. In the specific process, PE-Poly deposition is carried out after pickling, and it is not placed in the air for further oxidation. Figure 6 It is the stuck point printing trend chart of the batteries obtained by different pickling methods. From Figure 6 It can be seen that when the alkali polishing uses the hydrochloric acid route, the stuck point printing ratio of the battery is basically stable below 0.1%, and the stuck point printing ratio of the hydrofluoric acid route fluctuates greatly in the range of 2% to 23%.
[0102] Example 2
[0103] A preparation method of a TOPCon battery, comprising the following steps:
[0104] (1) Successively carry out texturing, boron diffusion, laser, and oxidation: conventional preparation processes.
[0105] (2) Alkali polishing treatment: including the successive processes of alkali polishing, post-cleaning, and pickling treatment. After the post-cleaning process is completed, a primitive oxide layer will be formed on the back surface of the silicon wafer. Then, pickling, water washing, and drying are carried out using a reagent containing hydrochloric acid to obtain the alkali-polished oxide layer. The specific thickness of the alkali-polished oxide layer is shown in Table 2.
[0106] (3) PE-Poly Deposition (including sequential PECVD oxidation treatment and PECVD doping treatment, forming a PECVD oxide layer through PECVD oxidation treatment and a doped polysilicon layer through PECVD doping treatment): Conducted using a tube PECVD equipment produced by Shenzhen Jiejiawei New Energy Equipment Co., Ltd., depositing a PECVD oxide layer to form a tunneling oxide layer (SiOx), and depositing an in-situ doped polysilicon layer (n+-a-Si:H) with a thickness of approximately 100 nm. Among them, the time, power, gas flow rate, and pressure of the PECVD oxidation treatment are shown in Table 2.
[0107] (4) Annealing: Conducted a high-temperature annealing at 900 °C for 25 min in a nitrogen atmosphere to activate the doped phosphorus atoms.
[0108] (5) Sequentially perform RCA cleaning, coating, and screen printing: Conventional preparation process.
[0109] Example 3 and Comparative Examples 2 - 3
[0110] A method for preparing a TOPCon cell, which is different from Example 2 in that the time of the PECVD oxidation treatment is different from that of Example 2, as specifically shown in Table 2.
[0111] Comparative Examples 4 - 5
[0112] A method for preparing a TOPCon cell, which is different from Example 2 in that the power of the PECVD oxidation treatment is different from that of Example 2, as specifically shown in Table 2.
[0113] Performance Testing
[0114] Test the stamping proportion of the TOPCon cells prepared in Examples 2 - 3 and Comparative Examples 2 - 5, and the results are shown in Table 2.
[0115] Table 2 Cell preparation parameters and stamping proportion of Examples 2 - 3 and Comparative Examples 2 - 5
[0116]
[0117] As can be seen from Table 2, under the condition that the alkali-etched oxide layer is relatively stable, in Examples 2-3, the PE-poly deposition process matches the appropriate time and power for depositing the PECVD oxide layer, and no stuck point marks will be generated in the obtained cells. In Comparative Example 2 and Comparative Example 3, the tunneling oxide layer thickness was increased by increasing the time for depositing the PECVD oxide layer. In Comparative Example 2, the time was increased by 10 s, and the stuck point mark ratio increased to 0.46%. In Comparative Example 3, the time was increased by 20 s, and the stuck point mark ratio increased to 1.9%, showing a positive correlation trend. In Comparative Example 4 and Comparative Example 5, the tunneling oxide layer thickness was increased by increasing the power for depositing the PECVD oxide layer. In Comparative Example 4, the power was increased by 25%, and the stuck point mark ratio increased to 31.46%. In Comparative Example 5, the power was increased by 50%, and the stuck point mark ratio increased to 65.81%, showing a strong positive correlation trend.
[0118] From the above, it can be seen that by controlling the time and power for depositing the PECVD oxide layer, it is beneficial to control the thickness of the PECVD oxide layer, thereby effectively reducing the stuck point mark ratio. In addition, by controlling the gas flow rate and pressure for depositing the PECVD oxide layer, the thickness of the PECVD oxide layer can also be regulated, thereby further reducing the generation of stuck point marks.
[0119] The total thickness of the tunneling oxide layer is composed of the thickness of the alkali-etched oxide layer formed by alkali etching treatment and the thickness of the PECVD oxide layer formed by PECVD oxidation treatment. When the total thickness of the tunneling oxide layer remains unchanged, when the alkali-etched oxide layer becomes thicker, in the PE-poly deposition process, by reducing the time for PECVD oxidation treatment or reducing the power of PECVD oxidation treatment, etc., the thickness of the PECVD oxide layer can be reduced. From Figure 5 it can be seen that after alkali polishing, the hydrochloric acid pickling route generates a thicker alkali-etched oxide layer than the hydrofluoric acid pickling route. Therefore, when the total thickness of the tunneling oxide layer remains unchanged, the thickness of the PECVD oxide layer formed by PECVD oxidation treatment through the hydrochloric acid pickling route is thinner than that through the hydrofluoric acid route. And if the proportion of the PECVD oxide layer thickness is larger, the difference in the tunneling oxide layer thickness between the stuck point position and the non-stuck point position is also larger, which is more likely to cause the generation of stuck point marks. Therefore, adopting the hydrochloric acid pickling route to retain the alkali-etched oxide layer on the interface and at the same time reduce the thickness of the PECVD oxide layer formed by PECVD oxidation treatment can effectively reduce the stuck point mark ratio and improve the EL stuck point mark problem in the battery manufacturing process.
[0120] Example 4
[0121] A preparation method of a TOPCon battery, which is different from that of Example 1. The preparation processes in this example are in sequence: texturing, boron diffusion, alkaline polishing treatment, Poly-Si deposition, annealing, RCA cleaning, coating, screen printing, and LECO (laser-assisted sintering), wherein the texturing, boron diffusion, alkaline polishing treatment, Poly-Si deposition, annealing, RCA cleaning, coating, and screen printing processes are the same as those in Example 1.
[0122] Example 4 optimizes the preparation process of the TOPCon battery on the basis of Example 1, which is beneficial to obtaining a TOPCon battery with better performance.
[0123] The embodiments of the present invention adopt hydrochloric acid pickling combined with PECVD oxidation treatment under specific process conditions, which can effectively reduce the proportion of stuck points. In the long-term production process of Example 1, the proportion of stuck points can be stably controlled below 0.1%, the proportion of stuck points in Example 2 can be reduced to 0%, and the proportion of stuck points in Example 3 can be reduced to 0.02%. It can be seen that the method of the embodiments of the present invention has good production stability and high battery yield. Moreover, the TOPCon battery obtained in the embodiment not only has a low proportion of stuck points, but also has good electrical properties, especially high battery efficiency, fill factor, and external quantum efficiency.
[0124] In summary, the present invention controls the thickness of the alkaline polishing oxide layer and its ratio to the thickness of the PECVD oxide layer through alkaline polishing treatment and PECVD oxidation treatment, and can form a tunneling oxide layer with good uniformity, which is beneficial to reducing the influence of graphite boat stuck points on silicon wafers, and further obtaining a TOPCon battery with a low proportion of stuck points.
Claims
1. A preparation method for the tunneling oxide layer of a TOPCon battery, characterized in that, Including the following steps: The pretreated silicon wafer is successively subjected to alkali polishing treatment and PECVD oxidation treatment to obtain the tunneling oxide layer; wherein, an alkali polishing oxide layer is formed after the alkali polishing treatment, and a PECVD oxide layer is formed after the PECVD oxidation treatment. The ratio of the average thickness of the alkali polishing oxide layer to the PECVD oxide layer is 1:(0.01 - 0.5); the average thickness of the alkali polishing oxide layer ≥ 1 nm.
2. The preparation method according to claim 1, characterized in that, The average thickness of the alkali polishing oxide layer is 1 - 2.4 nm; and / or, the average thickness of the PECVD oxide layer is 0.01 - 1.5 nm; and / or, the total thickness of the tunneling oxide layer is 1 - 3 nm.
3. The preparation method according to claim 1, characterized in that, The process of the alkali polishing treatment includes pickling treatment, and the reagent used in the pickling treatment does not react with silicon oxide.
4. The preparation method according to claim 3, wherein The reagent used in the pickling treatment does not contain hydrofluoric acid; Preferably, the reagent used in the pickling treatment contains at least one of hydrochloric acid, acetic acid or hypochlorous acid.
5. The preparation method according to claim 3, characterized in that, The silicon wafer obtained after the pickling treatment is placed in the air for oxidation for 0 - 100 min.
6. The preparation method according to claim 1, characterized in that, The deposition time used in the PECVD oxidation treatment is 50 - 200 s; and / or, the radio frequency power used in the PECVD oxidation treatment is 5000 - 20000 W; and / or, the gas flow rate used in the PECVD oxidation treatment is 5000 - 20000 sccm; and / or, the pressure used in the PECVD oxidation treatment is 800 - 2500 mTorr.
7. A tunneling oxide layer prepared by the preparation method according to any one of claims 1 - 6.
8. A TOPCon battery, characterized in that, Including the tunneling oxide layer according to claim 7.
9. A method for preparing a TOPCon battery according to claim 8, characterized in that, Including the following steps: The silicon wafer to be treated is successively subjected to pretreatment, alkali polishing treatment, PECVD oxidation treatment and post-treatment to obtain the TOPCon battery.
10. The preparation method according to claim 9, characterized in that, The post-treatment includes laser-assisted sintering treatment.