Preparation method of HBC battery and HBC battery
The laser oxidation process in HBC cell manufacturing addresses the high cost and efficiency limitations of photolithography by using oxide layers as masks, enhancing production efficiency and passivation while improving light absorption and reducing shading losses.
Patent Information
- Application Number
- CN202410037363.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-10
- Publication Date
- 2025-07-15
AI Technical Summary
In the existing HBC battery preparation process, the photoresist mask process is expensive and is not suitable for large-scale production, and the HJT battery current is low.
The laser oxidation process is used to form an oxide layer on the surface of the doped layer as a patterned mask, and the preparation process is optimized in combination with the etching process to reduce costs.
The photoelectric conversion efficiency of HBC cells is improved, the preparation process cost is reduced, and the damage to the passivation layer is reduced through laser oxidation process.
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Figure CN120322052A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of solar energy, and particularly relates to a preparation method of an HBC cell and an HBC cell. Background Art
[0002] Heterojunction cells (HJT) have the advantages of high open-circuit voltage (Voc) and high fill factor (FF), but the low current is an obstacle to further improving the efficiency. The main reasons are as follows: 1. Absorption of light by the front transparent conductive film (TCO); 2. Absorption of light by the front amorphous silicon film; 3. Shading loss of the front grid lines. The future development of heterojunction cells must be in the direction of low current.
[0003] Back contact cells (IBC) are a battery technology that integrates all the front and back electrodes on the back of the cell. It has the specific characteristic of no light shading on the front, and the high current is its significant advantage.
[0004] The HJT+IBC stacking technology is the key development direction of future HJT technology, which is called the HJT-IBC cell, also known as the HBC cell. In the preparation process of the HBC cell, the key lies in the formation of the patterned mask. In the existing HBC cell preparation process, a photoresist mask is used, that is, a layer of photoresist is first formed on the cell, and then patterning is carried out through photolithography technology. The process cost of the photoresist mask is high and it is not suitable for large-scale production.
[0005] Therefore, in view of the above technical problems, it is necessary to provide a preparation method of an HBC cell and an HBC cell. Summary of the Invention
[0006] In view of this, the purpose of the present invention is to provide a preparation method of an HBC cell and an HBC cell to optimize the preparation process and reduce the process cost.
[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:
[0008] A preparation method of an HBC cell, the preparation method comprising the following steps:
[0009] Provide a silicon wafer, including a first surface and a second surface arranged opposite to each other, the second surface including a first region, a second region and an isolation region, the isolation region being located between the first region and the second region;
[0010] Deposit a first passivation layer and a first doping layer on the second surface in sequence;
[0011] Deposit a third passivation layer and a third doping layer on the first surface in sequence;
[0012] Form a first oxide layer on the first doped layer in the first region and a third oxide layer on the third doped layer respectively through a laser oxidation process;
[0013] Using the first oxide layer as a mask, remove the first passivation layer and the first doped layer on the second region and the isolation region;
[0014] Deposit a second passivation layer and a second doped layer on the second surface in sequence;
[0015] Form a second oxide layer on the second doped layer in the second region through a laser oxidation process;
[0016] Using the second oxide layer as a mask and the first oxide layer as a blocking layer, remove the second passivation layer and the second doped layer on the first region, and part of the second passivation layer and the second doped layer on the isolation region;
[0017] Remove the third oxide layer on the first surface, and the first oxide layer and the second oxide layer on the second surface;
[0018] Prepare an electrically isolated first electrode structure and second electrode structure on the first region and the second region respectively.
[0019] In one embodiment, the laser oxidation process is carried out in an oxygen-containing atmosphere, the laser wavelength is 320 nm to 380 nm, the power is 3 W to 10 W, the pulse width is 10 ns to 50 ns, the duty cycle is 30% to 80%, and the scribing speed is 1 m / s to 10 m / s.
[0020] In one embodiment, the oxygen-containing atmosphere includes one or more of air, oxygen, and water vapor.
[0021] In one embodiment, the first doped layer is an amorphous silicon layer or a microcrystalline silicon layer, and the first oxide layer is a SiO X layer; and / or,
[0022] the second doped layer is an amorphous silicon layer or a microcrystalline silicon layer, and the second oxide layer is a SiO X layer; and / or,
[0023] the third doped layer is an amorphous silicon layer or a microcrystalline silicon layer, and the third oxide layer is a SiO X layer.
[0024] In one embodiment, the thickness of the first oxide layer is 1 nm to 10 nm, the thickness of the first doped layer before the laser oxidation process is 15 nm to 45 nm, and the thickness of the first doped layer after removing the first oxide layer is 10 nm to 40 nm; and / or,
[0025] The thickness of the second oxide layer is 1 nm to 10 nm, the thickness of the second doped layer before the laser oxidation process is 15 nm to 35 nm, and the thickness of the second doped layer after removing the second oxide layer is 10 nm to 30 nm; and / or,
[0026] The thickness of the third oxide layer is 1 nm to 10 nm, the thickness of the third doped layer before the laser oxidation process is 15 nm to 35 nm, and the thickness of the first doped layer after removing the first oxide layer is 10 nm to 30 nm.
[0027] In one embodiment, the first passivation layer is an intrinsic amorphous silicon layer; and / or,
[0028] The thickness of the first passivation layer is 5 nm to 10 nm; and / or,
[0029] The second passivation layer is an intrinsic amorphous silicon layer; and / or,
[0030] The thickness of the second passivation layer is 5 nm to 10 nm; and / or,
[0031] The third passivation layer is an intrinsic amorphous silicon layer; and / or,
[0032] The thickness of the third passivation layer is 5 nm to 10 nm; and / or,
[0033] The silicon wafer is a doped silicon wafer; and / or,
[0034] The doping type of the first doped layer is opposite to that of the silicon wafer, and the doping concentration is 1E17 cm -3 ~1E20 cm -3 ; and / or,
[0035] The doping type of the second doped layer is the same as that of the silicon wafer, and the doping concentration is 1E17 cm -3 ~1E22 cm -3 ; and / or,
[0036] The doping type of the third doped layer is the same as that of the silicon wafer, and the doping concentration is 1E17 cm -3 ~1E22 cm -3 .
[0037] In one embodiment, the preparation method further includes:
[0038] Forming a first surface and / or a second surface with a pyramid texture structure through an alkaline texturing process; and / or,
[0039] Removing the first passivation layer and the first doped layer on the second region through an alkaline etching process; and / or,
[0040] Removing the second passivation layer and the second doping layer on the first region through an alkali etching process; and / or,
[0041] Removing the third oxide layer on the first surface and the first oxide layer and the second oxide layer on the second surface through an acid etching process; and / or,
[0042] Preparing an antireflection layer on the third doping layer, the antireflection layer including one or a combination of a TCO layer, a SiN X layer, a SiN X O Y layer.
[0043] In one embodiment, the preparation of the first electrode structure and the second electrode structure includes:
[0044] Preparing a TCO layer on the second surface of the silicon wafer;
[0045] Removing the TCO layer, the second doping layer and the second passivation layer on the isolation region through a laser removal process to form an isolation groove extending to the second surface of the silicon wafer, and a first TCO layer and a second TCO layer located on both sides of the isolation layer are respectively formed on the first doping layer and the second doping layer;
[0046] Preparing a first electrode in electrical contact with the first TCO layer on the first TCO layer, and preparing a second electrode in electrical contact with the second TCO layer on the second TCO layer.
[0047] In one embodiment, in the laser removal process, the laser wavelength is 482 nm to 582 nm or 582 nm to 682 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 30 W, the duty ratio is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s.
[0048] The technical solution provided by another embodiment of the present invention is as follows:
[0049] An HBC battery is prepared by the above preparation method, and is characterized in that the HBC battery includes:
[0050] A silicon wafer, including a first surface and a second surface arranged opposite to each other, the second surface including a first region, a second region and an isolation region, and the isolation region is located between the first region and the second region;
[0051] A heterostructure, including a first passivation layer and a first doping layer stacked on the first region;
[0052] A first electrode structure, located on the first doping layer in the heterostructure;
[0053] A first passivation structure, including a second passivation layer and a second doping layer stacked on the second region;
[0054] The second electrode structure is located on the second doped layer in the first passivation structure;
[0055] The second passivation structure includes a third passivation layer and a third doped layer stacked on the first surface;
[0056] The isolation structure includes an isolation groove located on the isolation region and extending to the second surface of the silicon wafer. The heterostructure, the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated by the isolation groove.
[0057] The present invention has the following beneficial effects:
[0058] The HBC cell of the present invention uses a laser oxidation process to form an oxide layer on the surface of the doped layer, and uses this oxide layer as a patterning mask, optimizing the cell manufacturing process and reducing the process cost;
[0059] The laser oxidation process has high processing precision, and combined with the etching process, it can greatly reduce the damage to the passivation layer and ensure the passivation effect;
[0060] The HBC cell combines the advantages of HJT cells and IBC cells. Passivation structures are used on both the front and back to reduce the surface recombination rate, and the passivation effect is good, which can significantly improve the photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0062] Figure 1 It is a schematic structural diagram of an HBC cell in a specific embodiment of the present invention;
[0063] Figures 2a to 2k It is a process flow chart for manufacturing an HBC cell in a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0064] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0065] In the present invention, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply indicates that the first feature has a lower horizontal height than the second feature.
[0066] The present invention discloses a method for preparing an HBC cell, comprising the following steps:
[0067] Providing a silicon wafer, comprising a first surface and a second surface disposed opposite to each other, the second surface comprising a first region, a second region and an isolation region, the isolation region being located between the first region and the second region;
[0068] Successively depositing a first passivation layer and a first doping layer on the second surface;
[0069] Successively depositing a third passivation layer and a third doping layer on the first surface;
[0070] Forming a first oxide layer on the first doping layer in the first region and a third oxide layer on the third doping layer respectively through a laser oxidation process;
[0071] Using the first oxide layer as a mask, removing the first passivation layer and the first doping layer on the second region and the isolation region;
[0072] Successively depositing a second passivation layer and a second doping layer on the second surface;
[0073] Forming a second oxide layer on the second doping layer in the second region through a laser oxidation process;
[0074] Using the second oxide layer as a mask and the first oxide layer as a blocking layer, removing the second passivation layer and the second doping layer on the first region and part of the second passivation layer and the second doping layer on the isolation region;
[0075] Removing the third oxide layer on the first surface, and the first oxide layer and the second oxide layer on the second surface;
[0076] Respectively preparing an electrically isolated first electrode structure and a second electrode structure on the first region and the second region.
[0077] The present invention also discloses an HBC cell, comprising:
[0078] A silicon wafer, comprising a first surface and a second surface disposed opposite to each other, the second surface comprising a first region, a second region and an isolation region, the isolation region being located between the first region and the second region;
[0079] A heterostructure, including a first passivation layer and a first doping layer stacked on a first region;
[0080] A first electrode structure, located on the first doping layer in the heterostructure;
[0081] A first passivation structure, including a second passivation layer and a second doping layer stacked on a second region;
[0082] A second electrode structure, located on the second doping layer in the first passivation structure;
[0083] A second passivation structure, including a third passivation layer and a third doping layer stacked on a first surface;
[0084] An isolation groove extending to the second surface of the silicon wafer is formed on the isolation region, and the heterostructure and the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated through the isolation groove.
[0085] The present invention will be further described below in conjunction with specific embodiments.
[0086] Refer Figure 1 As shown, the HBC battery in a specific embodiment of the present invention includes:
[0087] A silicon wafer 10, the silicon wafer is a doped silicon wafer, including a first surface S1 and a second surface arranged oppositely, the second surface includes a first region S21, a second region S22 and an isolation region S23, the isolation region S23 is located between the first region S21 and the second region S22, and the area of the first region S21 is larger than the area of the second region S22;
[0088] A heterostructure, including a first passivation layer 21 and a first doping layer 22 stacked on the first region S21, and the doping type of the first doping layer 22 is opposite to the doping type of the silicon wafer 10;
[0089] A first electrode structure, located on the first doping layer 22 in the heterostructure;
[0090] A first passivation structure, including a second passivation layer 31 and a second doping layer 32 stacked on the second region S22, and the doping type of the second doping layer 32 is the same as the doping type of the silicon wafer 10;
[0091] A second electrode structure, located on the second doping layer 32 in the first passivation structure;
[0092] A second passivation structure, located on the first surface of the silicon wafer;
[0093] The isolation structure includes an isolation groove 70 located on the isolation region S23 and extending to the second surface of the silicon wafer. The heterostructure, the first passivation structure, the first electrode structure, and the second electrode structure are all electrically isolated through the isolation groove 70.
[0094] Exemplarily, in this embodiment, the silicon wafer 10 is taken as an N-type silicon wafer (i.e., N-type doping) for illustration. The doping type of the first doping layer 22 is opposite to that of the silicon wafer 10 and is P-type doping (such as boron doping, etc.). The doping type of the second doping layer 32 is the same as that of the silicon wafer 10 and is N-type doping (such as phosphorus doping, etc.).
[0095] In this embodiment, the first region S21 is a PN junction region. The area of the first region S21 is 70% - 95% of the area of the second surface. Preferably, the area of the first region S21 is 80% - 85% of the area of the second surface.
[0096] Further, in the heterostructure of this embodiment, the first passivation layer 21 is an intrinsic amorphous silicon layer with a thickness of 5 nm - 10 nm. The first doping layer 22 is a P-type doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 10 nm - 40 nm and a doping concentration of 1E17 cm -3 ~1E20 cm -3 。
[0097] In this embodiment, the second region S22 is a back surface field passivation region. Preferably, in the first passivation structure, the second passivation layer 31 is an intrinsic amorphous silicon layer with a thickness of 5 nm - 10 nm. The second doping layer 32 is an N-type doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 10 nm - 30 nm and a doping concentration of 1E17 cm -3 ~1E22 cm -3 。
[0098] In addition, the first electrode structure in this embodiment includes a first TCO layer 51 located on the first doping layer 22 and a first electrode 61 in electrical contact with the first TCO layer 51. The second electrode structure includes a second TCO layer 52 located on the second doping layer 32 and a second electrode 62 in electrical contact with the second TCO layer 52.
[0099] Specifically, the TCO (transparent conductive oxide) layer can be one or more of ITO, AZO, IWO, etc. The first electrode 61 and the second electrode 62 are metal grid electrodes, and their materials can be Ag or Ag / Cu alloy.
[0100] In the third region S23 of this embodiment, isolation grooves 70 are formed. By providing the isolation grooves, the epitaxial layers on the first region S21 and the second region S22 can be isolated, avoiding short circuits between the two regions. Specifically, the first passivation layer 21 and the second passivation layer 31, the first doping layer 22 and the second doping layer 32, and the first TCO layer 51 and the second TCO layer 52 are all electrically isolated through the isolation grooves 70. The depth of the isolation grooves (the distance from the first TCO layer 51 to the bottom of the grooves) is 0.1 μm to 6 μm, and the width is 20 μm to 100 μm.
[0101] Further, an insulating layer (not shown) is formed in all or part of the regions within the isolation grooves 70. By providing the insulating layer, the isolation effect can be further improved. In this embodiment, the isolation grooves 70 extend to the surface of the silicon wafer, and an extremely thin (about 1 nm thick) natural oxide layer (i.e., silicon oxide layer) is formed on the bottom wall and side walls of the isolation grooves.
[0102] In this embodiment, the first surface S1 is a front passivation region, and the second passivation structure thereon includes a third passivation layer 41 and a third doping layer 42 stacked on the first surface S1. Among them, the third passivation layer 41 is an intrinsic amorphous silicon layer with a thickness of 5 nm to 10 nm; the third doping layer 42 is an amorphous silicon layer or a microcrystalline silicon layer with a thickness of 10 nm to 30 nm, and the doping type is the same as that of the silicon wafer 10, which is N-type doping, and the doping concentration is 1E17 cm -3 ~1E22 cm -3 .
[0103] Further, an antireflection layer 53 is stacked on the third doping layer 42. The antireflection layer 53 includes one or a combination of a TCO layer, a SiN X layer, a SiN X O Y layer, etc., and is preferably a TCO layer.
[0104] Exemplarily, the first surface S1, the first region S21, and the second region S22 in this embodiment are all pyramid-structured matte surfaces, and the light trapping effect is improved through the pyramid matte surface structure. In other embodiments, the first surface S1, the first region S21, and the second region S22 can also be polished surfaces, which will not be elaborated here.
[0105] Both the front and back surfaces of the HBC cell of the present invention adopt a passivation structure to reduce the surface recombination rate. Using an amorphous silicon layer has a good passivation effect and can significantly improve the photoelectric conversion efficiency. The photoelectric conversion efficiency can be increased by at least 0.3% compared with that of a conventional BC cell.
[0106] Refer Figures 2a to 2k As shown, the manufacturing method of the HBC cell in a specific embodiment of the present invention includes the following steps:
[0107] 1. Refer Figure 2aAs shown, a silicon wafer 10 is provided. The silicon wafer is an N-type silicon wafer, including a first surface S1 and a second surface which are oppositely arranged. The second surface includes a first region S21, a second region S22 and an isolation region S23. The isolation region S23 is located between the first region S21 and the second region S22, and the area of the first region S21 is larger than the area of the second region S22.
[0108] In this embodiment, the first surface S1 of the silicon wafer is a front passivation region, the first region S21 in the second surface is a PN junction region, the second region S22 is a back surface field passivation region, and the first region S21 and the second region S22 are isolated by the isolation region 23. Preferably, the area of the first region S21 is 70% - 95% of the area of the second surface.
[0109] Exemplarily, in this embodiment, first, through an alkaline (such as NaOH solution) texturing process, a pyramid texture structure is formed on the first surface and the second surface of the silicon wafer 10 for light trapping, and the pyramid size is 0.5μm - 5μm.
[0110] 2. Refer Figure 2b As shown, through a double-sided PECVD (Plasma Enhanced Chemical Vapor Deposition) process, a first passivation layer 21 and a first doping layer 22 are sequentially deposited on the second surface, and at the same time, a third passivation layer 41 and a third doping layer 42 are sequentially deposited on the first surface S1.
[0111] Exemplarily, the first passivation layer 21 is an intrinsic amorphous silicon layer with a thickness of 5nm - 10nm, the first doping layer 22 is a P-type doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 15nm - 45nm, and the doping concentration is 1E17cm -3 ~1E20cm -3 ; the third passivation layer 41 is an intrinsic amorphous silicon layer with a thickness of 5nm - 10nm, the third doping layer 42 is an N-type doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 15nm - 35nm, and the doping concentration is 1E17cm -3 ~1E22cm -3 .
[0112] 3. Refer Figure 2c As shown, through a laser oxidation process, a first oxide layer 81 is formed on the first doping layer 22 in the first region S21, and a third oxide layer 83 is formed on the third doping layer 42.
[0113] Among them, the laser oxidation process is carried out in an oxygen-containing atmosphere. The laser wavelength is 320nm - 380nm, the power is 3W - 10W, the pulse width is 10ns - 50ns, the duty cycle is 30% - 80%, and the scribing speed is 1m / s - 10m / s; the oxygen-containing atmosphere includes one or more of air, oxygen, water vapor, etc. Preferably, the oxygen-containing atmosphere in this embodiment is air.
[0114] In this embodiment, the overall surface oxidation treatment of the front side and the local oxidation treatment of the back side can be achieved by controlling the laser oxidation process, so as to oxidize partial regions on the surfaces of the first doping layer 22 and the third doping layer 42 to form a first oxide layer 81 and a third oxide layer 83, that is, a SiO X (silicon oxide) layer. By controlling the laser oxidation process parameters, the thickness of the SiO X layer can be controlled to be 1 nm to 10 nm.
[0115] 4. As shown in Figure 2d , using the first oxide layer 81 as a mask, the first passivation layer 21 and the first doping layer 22 on the second region S22 and the isolation region S23 are removed.
[0116] In this step, the removal of the first passivation layer 21 and the first doping layer 22 can be achieved by an alkali etching process or a laser removal process, etc.
[0117] Exemplarily, in this embodiment, the alkali etching process is taken as an example for illustration. A NaOH solution with a mass fraction of 1% to 3.2% is used for etching at 80 °C. Using the first oxide layer 81 and the third oxide layer 83 as masks for the back side and the front side respectively, the first passivation layer 21 and the first doping layer 22 on the second region S22 and the isolation region S23 are removed, and at the same time, a pyramid texture structure is formed on the second region S22 and the isolation region S23.
[0118] Among them, the alkali etching / alkali texturing process is a conventional processing technology in the art, and will not be elaborated in detail here.
[0119] 5. As shown in Figure 2e , through a single-sided PECVD process, a second passivation layer 31 and a second doping layer 32 are sequentially deposited on the second region S22, the isolation region S23, and the first mask 81.
[0120] Exemplarily, the second passivation layer 31 is an intrinsic amorphous silicon layer with a thickness of 5 nm to 10 nm, and the second doping layer 32 is an N-type doped amorphous silicon layer or microcrystalline silicon layer with a thickness of 15 nm to 35 nm and a doping concentration of 1E17 cm -3 ~1E22 cm -3 .
[0121] 6. As shown in Figure 2f , a second oxide layer 82 is formed on the second doping layer 32 in the second region S22 through a laser oxidation process.
[0122] Among them, the laser oxidation process is carried out in an oxygen-containing atmosphere. The laser wavelength is 320 nm to 380 nm, the power is 3 W to 10 W, the pulse width is 10 ns to 50 ns, the duty cycle is 30% to 80%, and the scribing speed is 1 m / s to 10 m / s; the oxygen-containing atmosphere includes one or more of air, oxygen, water vapor, etc. Preferably, the oxygen-containing atmosphere in this embodiment is air.
[0123] In this embodiment, local oxidation treatment of the back surface can be achieved by controlling the laser oxidation process, so as to oxidize a partial area on the surface of the second doping layer 32 to form a second oxide layer 82, that is, a SiO X (silicon oxide) layer. By controlling the laser oxidation process parameters, the thickness of the SiO X layer can be controlled to be 1 nm to 10 nm.
[0124] 7. As shown in Figure 2g , using the second oxide layer 82 as a mask and the first oxide layer 81 as a barrier layer, the second passivation layer 31 and the second doping layer 32 on the first region S21, and part of the second passivation layer 31 and the second doping layer 32 on the isolation region S23 are removed.
[0125] In this step, the removal of the second passivation layer 31 and the second doping layer 32 can be carried out by an alkali etching process or a laser removal process, etc.
[0126] Exemplarily, in this embodiment, the alkali etching process is taken as an example for illustration. A NaOH solution with a mass fraction of 1% to 3.2% is used for etching at 80 °C. Using the second oxide layer 82 and the third oxide layer 83 as masks for the back surface and the front surface respectively, and the first oxide layer 81 as a barrier layer, the second passivation layer 31 and the second doping layer 32 on the first region S21, and part of the second passivation layer 31 and the second doping layer 32 on the isolation region S23 are removed.
[0127] Among them, the alkali etching / alkali texturing process is a conventional processing technology in the art, and will not be elaborated in detail here.
[0128] 8. As shown in Figure 2h , the third oxide layer 83 on the first surface S1, and the first oxide layer 81 and the second oxide layer 82 on the second surface are removed.
[0129] Exemplarily, in this embodiment, the removal of the oxide layer is carried out by an acid etching process. The acid solution can be an HF acid solution, or a mixed solution of HF acid and hydrochloric acid, etc. All the oxide layers on the back surface and the front surface are removed in the same step of the acid etching process.
[0130] 9. A first electrode structure is prepared on the first doping layer 22, a second electrode structure is prepared on the second doping layer 32, and an antireflection layer 53 is prepared on the third doping layer 42.
[0131] Exemplarily, the preparation of the first electrode structure and the second electrode structure in this embodiment is specifically as follows:
[0132] Refer Figure 2i As shown, a TCO layer (transparent conductive layer) 50 is prepared on the entire second surface of the silicon wafer. The material of the TCO layer 50 may include one or more of ITO, IZO, VTTO, etc.;
[0133] Refer Figure 2j As shown, the TCO layer, the second doping layer 32, and the second passivation layer 31 on the isolation region S23 are removed by a laser process to form an isolation groove 70 extending to the second surface of the silicon wafer. The laser wavelength in this step of the laser process is 482 nm to 582 nm or 582 nm to 682 nm, the pulse width is 10 ns to 50 ns, the power is 5 W to 30 W, the duty cycle is 30% to 80%, and the scribing speed is 15 m / s to 25 m / s. The laser processing depth (i.e., the isolation groove depth) is controlled to be 0.1 μm to 6 μm and the width is 20 μm to 100 μm by the above process parameters, so as to form electrically isolated first TCO layer 51 and second TCO layer 52 on the first doping layer 22 and the second doping layer 32 respectively;
[0134] Refer Figure 2k As shown, a first electrode 61 in electrical contact with the first TCO layer 51 is prepared on the first TCO layer 51, and a second electrode 62 in electrical contact with the second TCO layer 52 is prepared on the second TCO layer 52.
[0135] Preferably, the metal electrode (the first electrode 61 or the second electrode 62) is prepared by screen printing using a conductive paste. The conductive paste uses a low-temperature silver paste or a silver-copper paste, and the curing temperature is 180°C to 220°C.
[0136] Refer Figure 2i As shown, the antireflection layer 53 in this embodiment uses a TCO layer, and the preparation of the antireflection layer 53 is carried out in the same process as the preparation of the back TCO layer.
[0137] In other embodiments, the antireflection layer may also use a SiN X layer, a SiN X O Y layer, or a combination of one or more of them. In this case, the antireflection layer requires a separate deposition process, but the antireflection effect of the SiN X layer and the SiN X O Y layer is better than that of the TCO layer.
[0138] From the above technical solutions, it can be seen that the present invention has the following beneficial effects:
[0139] The HBC cell of the present invention forms an oxide layer on the surface of the doped layer by means of a laser oxidation process, and uses this oxide layer as a patterning mask, optimizing the cell preparation process and reducing the process cost;
[0140] The laser oxidation process has a high processing precision, and in combination with the etching process, it can greatly reduce the damage to the passivation layer, ensuring the passivation effect;
[0141] The HBC cell combines the advantages of the HJT cell and the IBC cell. A passivation structure is adopted on both the front and the back to reduce the surface recombination rate, and the passivation effect is good, which can significantly improve the photoelectric conversion efficiency.
[0142] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.
[0143] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A method for preparing an HBC battery, characterized in that, The preparation method includes the following steps: Provide a silicon wafer, including a first surface and a second surface disposed opposite to each other. The second surface includes a first region, a second region, and an isolation region, and the isolation region is located between the first region and the second region; Deposit a first passivation layer and a first doping layer on the second surface in sequence; Deposit a third passivation layer and a third doping layer on the first surface in sequence; Form a first oxide layer on the first doping layer in the first region and a third oxide layer on the third doping layer respectively through a laser oxidation process; Using the first oxide layer as a mask, remove the first passivation layer and the first doping layer on the second region and the isolation region; Deposit a second passivation layer and a second doping layer on the second surface in sequence; Form a second oxide layer on the second doping layer in the second region through a laser oxidation process; Using the second oxide layer as a mask and the first oxide layer as a blocking layer, remove the second passivation layer and the second doping layer on the first region, and part of the second passivation layer and the second doping layer on the isolation region; Remove the third oxide layer on the first surface, and the first oxide layer and the second oxide layer on the second surface; Prepare electrically isolated first electrode structures and second electrode structures on the first region and the second region respectively.
2. The preparation method according to claim 1, characterized in that, The laser oxidation process is carried out in an oxygen-containing atmosphere. The laser wavelength is 320nm - 380nm, the power is 3W - 10W, the pulse width is 10ns - 50ns, the duty cycle is 30% - 80%, and the scribing speed is 1m / s - 10m / s.
3. The preparation method according to claim 2, characterized in that, The oxygen-containing atmosphere includes one or more of air, oxygen, and water vapor.
4. The preparation method according to claim 1 or 2, characterized in that The first doped layer is an amorphous silicon layer or a microcrystalline silicon layer, and the first oxide layer is a SiO X layer; and / or, The second doped layer is an amorphous silicon layer or a microcrystalline silicon layer, and the second oxide layer is a SiO X layer; and / or, The third doped layer is an amorphous silicon layer or a microcrystalline silicon layer, and the third oxide layer is a SiO X layer.
5. The preparation method according to claim 4, characterized in that, The thickness of the first oxide layer is 1nm - 10nm, the thickness of the first doping layer before the laser oxidation process is 15nm - 45nm, and the thickness of the first doping layer after removing the first oxide layer is 10nm - 40nm; and / or, The thickness of the second oxide layer is 1nm - 10nm, the thickness of the second doping layer before the laser oxidation process is 15nm - 35nm, and the thickness of the second doping layer after removing the second oxide layer is 10nm - 30nm; and / or, The thickness of the third oxide layer is 1nm - 10nm, the thickness of the third doping layer before the laser oxidation process is 15nm - 35nm, and the thickness of the first doping layer after removing the first oxide layer is 10nm - 30nm.
6. The preparation method according to claim 1, characterized in that, The first passivation layer is an intrinsic amorphous silicon layer; and / or, The thickness of the first passivation layer is 5nm - 10nm; and / or, The second passivation layer is an intrinsic amorphous silicon layer; and / or, The thickness of the second passivation layer is 5nm - 10nm; and / or, The third passivation layer is an intrinsic amorphous silicon layer; and / or, The thickness of the third passivation layer is 5nm - 10nm; and / or, The silicon wafer is a doped silicon wafer; and / or, The doping type of the first doping layer is opposite to that of the silicon wafer, and the doping concentration is 1E17 cm -3 ~1E20 cm -3 ; and / or, The doping type of the second doping layer is the same as that of the silicon wafer, and the doping concentration is 1E17 cm -3 ~1E22 cm -3 ; and / or, The doping type of the third doping layer is the same as that of the silicon wafer, and the doping concentration is 1E17 cm -3 ~1E22 cm -3 .
7. The preparation method according to claim 1, wherein The preparation method further includes: Form a first surface and / or a second surface with a pyramid-shaped textured structure through an alkaline texturing process; and / or, Remove the first passivation layer and the first doping layer on the second region through an alkaline etching process; and / or, Remove the second passivation layer and the second doping layer on the first region through an alkaline etching process; and / or, Removing the third oxide layer on the first surface and the first and second oxide layers on the second surface by an acid etching process; and / or, An antireflection layer is prepared on the third doping layer, and the antireflection layer includes one or a combination of a TCO layer, a SiN X layer, a SiN X O Y layer, etc.
8. The preparation method according to claim 1, characterized in that, The preparation of the first electrode structure and the second electrode structure includes: Preparing a TCO layer on the second surface of the silicon wafer; Removing the TCO layer, the second doping layer, and the second passivation layer on the isolation region by a laser removal process to form an isolation groove extending to the second surface of the silicon wafer, and a first TCO layer and a second TCO layer are respectively formed on the first doping layer and the second doping layer on both sides of the isolation layer; Preparing a first electrode in electrical contact with the first TCO layer on the first TCO layer, and preparing a second electrode in electrical contact with the second TCO layer on the second TCO layer.
9. The preparation method according to claim 8, characterized in that, In the laser removal process, the laser wavelength is 482nm - 582nm or 582nm - 682nm, the pulse width is 10ns - 50ns, the power is 5W - 30W, the duty cycle is 30% - 80%, and the scribing speed is 15m / s - 25m / s.
10. An HBC cell, prepared by the preparation method according to any one of claims 1 to 9, characterized in that, The HBC cell includes: A silicon wafer, including a first surface and a second surface arranged opposite to each other, the second surface including a first region, a second region, and an isolation region, and the isolation region is located between the first region and the second region; A heterostructure, including a first passivation layer and a first doping layer stacked on the first region; A first electrode structure, located on the first doping layer in the heterostructure; A first passivation structure, including a second passivation layer and a second doping layer stacked on the second region; A second electrode structure, located on the second doping layer in the first passivation structure; A second passivation structure, including a third passivation layer and a third doping layer stacked on the first surface; An isolation structure, including an isolation groove located on the isolation region and extending to the second surface of the silicon wafer, and the heterostructure and the first passivation structure, and the first electrode structure and the second electrode structure are electrically isolated through the isolation groove.