Light emitting device and display apparatus having same

Abstract

A light emitting device according to one embodiment of the present invention comprises: a light emitting region; an insulating pattern disposed in the light emitting region and including at least one recessed portion and a protruding portion surrounding the recessed portion; a first electrode disposed on the insulating pattern and overlapping a first region of the recessed portion and a protruding portion adjacent to the first region; a second electrode disposed on the insulating pattern to be separated from the first electrode by a predetermined distance in the first direction, and overlapping a second region of the recessed portion and a protruding portion adjacent to the second region; and a light emitting diode disposed inside the recessed portion and electrically connected between the first electrode and the second electrode.

Description

[0001] This application is a divisional application of Application No. 201980077016.3, titled "Light-emitting Device and Display Device Having the Same", filed with the State Intellectual Property Office of China on May 20, 2019. Technical Field

[0002] Various embodiments of the present disclosure relate to a light-emitting device and a display device including the light-emitting device. Background Art

[0003] Recently, technologies for manufacturing ultra-small light-emitting diodes using materials having a reliable inorganic crystal structure and for manufacturing light-emitting devices using the light-emitting diodes have been developed. For example, a technology for manufacturing ultra-small light-emitting diodes having a small size corresponding to a range from the nanoscale to the micrometer scale and for forming a light source of a light-emitting device using the ultra-small light-emitting diodes has been developed. Such a light-emitting device can be provided in various electronic devices such as a display device and a lighting device. Summary of the Invention

[0004] Technical Problem Various embodiments of the present disclosure relate to a light-emitting device including a light-emitting diode and a display device including the light-emitting device.

[0005] Technical Solution A light-emitting device according to the present disclosure may include: a light-emitting region; an insulating pattern disposed in the light-emitting region and including at least one recess and a protrusion configured to surround the recess; a first electrode disposed on the insulating pattern and configured to overlap a first region of the recess and the protrusion in the periphery of the first region; a second electrode disposed on the insulating pattern and spaced apart from the first electrode by a predetermined distance in a first direction and configured to overlap a second region of the recess and the protrusion in the periphery of the second region; and a light-emitting diode disposed in the recess and electrically connected between the first electrode and the second electrode.

[0006] In an embodiment, the recess may include an inclined surface having an inclination within a predetermined angular range in a peripheral region adjacent to the protrusion.

[0007] In an embodiment, each of the first electrode and the second electrode may include a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

[0008] In an embodiment, the recess may have a circular shape, an elliptical shape, a polygonal shape, or a combination thereof in a plan view.

[0009] In an embodiment, the recess may include an opening.

[0010] In an embodiment, the recess may have a width greater than the length of the light emitting diode in a first direction.

[0011] In an embodiment, the recess may have the same width in a first direction and a second direction perpendicular to the first direction.

[0012] In an embodiment, the light emitting diode may include a rod-shaped light emitting diode, and the rod-shaped light emitting diode includes a first end and a second end disposed at opposite ends thereof in a longitudinal direction.

[0013] In an embodiment, the light emitting device may further include: a first contact electrode disposed on a first end of the light emitting diode and an area of the first electrode, and configured to electrically connect the first end to the first electrode; and a second contact electrode disposed on a second end of the light emitting diode and an area of the second electrode, and configured to electrically connect the second end to the second electrode.

[0014] In an embodiment, the light emitting device may further include a first insulating layer disposed between the light emitting diode and the first electrode and the second electrode, and configured to expose the area of each of the first electrode and the second electrode.

[0015] In an embodiment, the light emitting device may further include a reflective electrode disposed on the first insulating layer at a position adjacent to the light emitting diode, and including an opening corresponding to the light emitting diode.

[0016] In an embodiment, each of the first electrode and the second electrode may extend in a second direction intersecting the first direction, and the reflective electrode may include at least one first direction pattern extending in the first direction to intersect the first electrode and the second electrode.

[0017] In an embodiment, the insulating layer pattern may include a plurality of recesses dispersed at a predetermined interval. At least one light emitting diode may be disposed in each of the plurality of recesses.

[0018] A display device according to an embodiment of the present disclosure may include: a display area; and pixels disposed in the display area and including a light emitting area. The pixel may include: an insulating pattern disposed in the light emitting area and including at least one recess and a protrusion configured to surround the recess; a first electrode disposed on the insulating pattern and configured to overlap a first area of the recess and the protrusion in the periphery of the first area; a second electrode disposed on the insulating pattern and spaced apart from the first electrode by a predetermined distance in a first direction, and configured to overlap a second area of the recess and the protrusion in the periphery of the second area; and a light emitting diode disposed in the recess and electrically connected between the first electrode and the second electrode.

[0019] In an embodiment, the recess may include an inclined surface having an inclination within a predetermined angular range in a peripheral region adjacent to the protrusion. Each of the first electrode and the second electrode may include a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

[0020] In an embodiment, the recess may have a circular shape, an oval shape, a polygonal shape, or a combination thereof in a plan view.

[0021] In an embodiment, the recess may include an opening.

[0022] In an embodiment, the recess may have a width greater than a length of the light-emitting diode in a first direction.

[0023] In an embodiment, the pixel may include at least one of the following: a first insulating layer disposed between the light-emitting diode and the first electrode and the second electrode, and including an opening formed to expose a region of each of the first electrode and the second electrode; and a reflective electrode disposed on the first insulating layer at a position adjacent to the light-emitting diode, and including an opening corresponding to the light-emitting diode.

[0024] In an embodiment, the insulating pattern may include a plurality of recesses dispersed at a predetermined interval in a light-emitting region. At least one light-emitting diode may be disposed in each of the plurality of recesses.

[0025] Advantageous Effects In a light-emitting device according to various embodiments of the present disclosure and a display device including the light-emitting device, the efficiency of light emitted from each light-emitting region can be improved, and the degree of alignment of the light-emitting diodes can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a and Figure 1b are a perspective view and a cross-sectional view, respectively, showing a light-emitting diode according to an embodiment of the present disclosure.

[0027] Figure 2a and Figure 2b are a perspective view and a cross-sectional view, respectively, showing a light-emitting diode according to an embodiment of the present disclosure.

[0028] Figure 3a and Figure 3b are a perspective view and a cross-sectional view, respectively, showing a light-emitting diode according to an embodiment of the present disclosure.

[0029] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0030] Figures 5a to 5cThese are circuit diagrams showing light-emitting devices according to embodiments of the present disclosure, and different embodiments of active pixels including the light-emitting devices are shown, for example.

[0031] Figure 6a and Figure 6b These are plan views showing light-emitting devices according to embodiments of the present disclosure, and different embodiments of pixels including light source units formed by the light-emitting devices are shown, for example.

[0032] Figure 7 is a plan view showing an insulating pattern according to an embodiment of Figure 6a and Figure 6b

[0033] Figure 8a and Figure 8b These are cross-sectional views showing light-emitting devices according to embodiments of the present disclosure, and different embodiments of cross-sections corresponding to line I-I' of Figure 6b are shown, for example.

[0034] Figure 9 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and an embodiment of a cross-section corresponding to line II-II' of Figure 6b is shown.

[0035] Figure 10 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and an embodiment of a cross-section corresponding to line III-III' of Figure 6b is shown.

[0036] Figure 11 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and an embodiment of a pixel including a light source unit formed by the light-emitting device is shown.

[0037] Figure 12 is a plan view showing an insulating pattern according to an embodiment of Figure 11

[0038] Figure 13a and Figure 13b These are cross-sectional views showing light-emitting devices according to embodiments of the present disclosure, and different embodiments of cross-sections corresponding to line IV-IV' of Figure 11 are shown, for example.

[0039] Figure 14 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and an embodiment of a cross-section corresponding to line V-V' of Figure 11 is shown.

[0040] Figure 15is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a cross-section corresponding to the line VI-VI' of Figure 11 The embodiments of the cross-section corresponding to the line VI-VI' of

[0041] Figure 16 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel including a light source unit formed by the light-emitting device.

[0042] Figure 17 is a plan view showing an insulating pattern according to an embodiment of Figure 16 The insulating pattern according to the embodiment of

[0043] Figure 18 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, modifications related to the insulating patterns of Figure 16 and Figure 17 The modifications related to the insulating patterns of

[0044] Figure 19 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel including a light source unit formed by the light-emitting device.

[0045] Figure 20 is a plan view showing an insulating pattern according to an embodiment of Figure 19 The insulating pattern according to the embodiment of

[0046] Figure 21 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, modifications related to the insulating patterns of Figure 19 and Figure 20 The modifications related to the insulating patterns of

[0047] Figure 22 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel including a light source unit formed by the light-emitting device.

[0048] Figure 23 is a plan view showing a reflective electrode according to an embodiment of Figure 22 The reflective electrode according to the embodiment of

[0049] Figure 24 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a cross-section corresponding to the line VII-VII' of Figure 22 The embodiments of the cross-section corresponding to the line VII-VII' of Detailed Description

[0050] Since the embodiments of the present disclosure can be variously modified in many different forms, various embodiments of the present disclosure will now be described in detail with reference to the specific examples shown in the drawings. However, the present disclosure is not limited to the following embodiments and can be modified in various forms.

[0051] Some elements that are not directly related to the features of the present disclosure in the drawings may be omitted to clearly explain the present disclosure. In addition, the dimensions, ratios, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that throughout the drawings, the same reference numerals are used to denote the same or similar elements, and repeated descriptions will be omitted.

[0052] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprising", "including", "having", etc. are used in the present disclosure, it indicates the presence of the stated features, wholes, steps, operations, elements, components, and / or combinations thereof, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. In addition, when a first component or part is disposed on a second component or part, the first component or part may not only be directly on the second component or part, but also a third component or part may be interposed between the first component or part and the second component or part. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they may be changed to opposite positions or directions according to the perspective or direction.

[0053] Embodiments of the present disclosure and the required details are described with reference to the drawings to describe the present disclosure in detail, such that those of ordinary skill in the art to which the present disclosure pertains can easily practice the present disclosure. In addition, as long as it is not specifically mentioned in the sentence, the singular form may include the plural form.

[0054] Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a and Figure 3b are a perspective view and a cross-sectional view showing a light-emitting diode LD according to an embodiment of the present disclosure. Although Figures 1a to 3b shows a cylindrical rod-shaped light-emitting diode LD, the type and / or shape of the light-emitting diode LD according to the present disclosure are not limited thereto.

[0055] Referring to Figure 1a and Figure 1b , a light-emitting diode LD according to an embodiment of the present disclosure may include a first-conductive-type semiconductor layer (also referred to as "first semiconductor layer") 11, a second-conductive-type semiconductor layer (also referred to as "second semiconductor layer") 13, and an active layer 12 disposed between the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13. For example, the light-emitting diode LD may be constituted by a stack formed by sequentially stacking the first-conductive-type semiconductor layer 11, the active layer 12, and the second-conductive-type semiconductor layer 13.

[0056] In an embodiment, the light-emitting diode LD may be provided in the form of a bar extending in one direction. If the direction along which the light-emitting diode LD extends is defined as the longitudinal direction, the light-emitting diode LD may have a first end and a second end with respect to the longitudinal direction.

[0057] In an embodiment, one of the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13 may be provided on the first end of the light-emitting diode LD, and the other of the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13 may be provided on the second end of the light-emitting diode LD.

[0058] In an embodiment, the light-emitting diode LD may be a rod-shaped light-emitting diode manufactured in the form of a rod. In the present disclosure, the term "rod-shaped" includes rod-like shapes such as cylindrical and prismatic shapes and strip shapes (i.e., having an aspect ratio greater than 1) extending in the longitudinal direction, and the cross-sectional shape thereof is not limited to a specific shape. For example, the length L of the light-emitting diode LD may be greater than its diameter D (or the width of its cross-section).

[0059] In an embodiment, the light-emitting diode LD may have a small size corresponding to a range from a nanoscale size to a microscale size, for example, a diameter D and / or a length L in the range from the nanoscale to the microscale. However, in the present disclosure, the size of the light-emitting diode LD is not limited thereto. For example, the size of the light-emitting diode LD may be changed in various ways according to the design conditions of various devices (e.g., display devices) that each employ the light-emitting diode LD as a light source.

[0060] The first-conductive-type semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first-conductive-type semiconductor layer 11 may include an n-type semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first-conductive dopant such as Si, Ge, or Sn. However, the material for forming the first-conductive-type semiconductor layer 11 is not limited thereto, and the first-conductive-type semiconductor layer 11 may be formed of various other materials.

[0061] The active layer 12 may be provided on the first-conductive-type semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0062] If an electric field of a predetermined voltage or higher is applied to opposite ends of the light-emitting diode LD, the light-emitting diode LD emits light through the combination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting diode LD can be controlled based on the foregoing principle, the light-emitting diode LD can be used as a light source for various light-emitting devices and pixels of a display device.

[0063] The second-conductive-type semiconductor layer 13 may be provided on the active layer 12 and include a semiconductor layer of a type different from that of the first-conductive-type semiconductor layer 11. For example, the second-conductive-type semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second-conductive-type semiconductor layer 13 may include a p-type semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second-conductive dopant such as Mg. However, the material for forming the second-conductive-type semiconductor layer 13 is not limited thereto, and the second-conductive-type semiconductor layer 13 may be formed of various other materials.

[0064] In an embodiment, the light-emitting diode LD may further include an insulating film INF provided on the surface of the light-emitting diode LD. In an embodiment, the insulating film INF may be formed on the surface of the light-emitting diode LD to surround at least the outer peripheral surface of the active layer 12. In addition, the insulating film INF may also surround regions of each of the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light-emitting diode LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first-conductive-type semiconductor layer 11 and the second-conductive-type semiconductor layer 13 provided at the respective opposite ends with respect to the longitudinal direction of the light-emitting diode LD. For example, two bottom surfaces of a cylinder (in Figure 1a and Figure 1b the top surface and the bottom surface of the light-emitting diode LD) may be exposed instead of covering the two bottom surfaces.

[0065] In an embodiment, the insulating film INF may include at least one insulating material such as SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto. In other words, the material for forming the insulating film INF is not limited to a specific material, and the insulating film INF may be formed of various known insulating materials.

[0066] In an embodiment, the light-emitting diode LD may further include additional components other than the first-conductive-type semiconductor layer 11, the active layer 12, the second-conductive-type semiconductor layer 13, and / or the insulating film INF. For example, the light-emitting diode LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer provided on one end of the first-conductive-type semiconductor layer 11, the active layer 12, and / or the second-conductive-type semiconductor layer 13.

[0067] For example, as Figure 2a and Figure 2b shown, the light-emitting diode LD may further include at least one electrode layer 14 provided on one end of the second-conductive-type semiconductor layer 13. In an embodiment, as Figure 3a and Figure 3b shown, the light-emitting diode LD may further include at least one electrode layer 15 provided on one end of the first-conductive-type semiconductor layer 11.

[0068] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, their oxides or alloys, and ITO, IZO, ITZO may be used alone or in combination with each other. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or semi-transparent. Thus, the light generated from the light-emitting diode LD may be emitted from the light-emitting diode LD after passing through the electrode layers 14 and 15.

[0069] In an embodiment, the insulating film INF may at least partially surround the outer peripheral surfaces of the electrode layers 14 and 15, or may not surround the outer peripheral surfaces. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to allow the opposite ends of the light-emitting diode LD having different polarities to be exposed, for example, to allow at least one region of each of the electrode layers 14 and 15 to be exposed. Optionally, in an embodiment, the insulating film INF may not be provided.

[0070] If the insulating film INF is provided on the surface of the light-emitting diode LD (specifically, on the surface of the active layer 12), then a short circuit between the active layer 12 and at least one electrode (for example, at least one of the contact electrodes connected to the opposite ends of the light-emitting diode LD) not shown can be prevented. Thus, the electrical stability of the light-emitting diode LD can be ensured.

[0071] In addition, due to the insulating film INF formed on the surface of the light-emitting diode LD, the occurrence of defects on the surface of the light-emitting diode LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting diode LD. Additionally, if the insulating film INF is formed on each light-emitting diode LD, even when multiple light-emitting diodes LD are arranged adjacent to each other, it is possible to prevent the light-emitting diodes LD from being short-circuited undesirably.

[0072] In an embodiment of the present disclosure, the light-emitting diode LD can be manufactured through a surface treatment process. For example, each light-emitting diode LD can be surface-treated such that when multiple light-emitting diodes LD are mixed with a fluid solution and then supplied to each light-emitting region (e.g., the light-emitting region of each pixel), the light-emitting diodes LD can be evenly dispersed rather than unevenly aggregated in the solution. For example, the surface of the light-emitting diode LD can be coated with a predetermined material.

[0073] The light-emitting device including the above-described light-emitting diode LD can be used in various devices including display devices that require a light source. For example, at least one ultra-small light-emitting diode LD (e.g., multiple ultra-small light-emitting diodes LD each having a size ranging from the nanoscale to the microscale) can be disposed in each pixel region of the display panel to form a light source (or a light source unit) for the corresponding pixel. In addition, the application field of the light-emitting diode LD according to the present disclosure is not limited to display devices. For example, the light-emitting diode LD can also be used in various devices such as lighting devices that require a light source.

[0074] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 shows the display device (specifically, the display panel PNL provided in the display device) as an example of a device that can use the light-emitting diode LD described with reference to Figures 1a to 3b as a light source. For example, each pixel PXL of the display panel PNL can include a light-emitting device. The light-emitting device can include at least one light-emitting diode LD.

[0075] For illustrative purposes, Figure 4 the structure of the display panel PNL according to the embodiment is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (e.g., at least one of a scan driver and a data driver) and / or multiple lines can be further provided on the display panel PNL.

[0076] Referring to Figure 4, a display panel PNL according to an embodiment of the present disclosure may include a substrate layer BSL and a plurality of pixels PXL disposed on the substrate layer BSL. Specifically, the display panel PNL and the substrate layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed in the display area DA on the substrate layer BSL.

[0077] In an embodiment, the display area DA may be disposed in a central area of the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of the display panel PNL so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0078] The substrate layer BSL may form a substrate of the display panel PNL. In an embodiment, the substrate layer BSL may be a rigid or flexible substrate or film, and there is no specific limitation on its material or property. For example, the substrate layer BSL may be a rigid substrate made of glass or strengthened glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and there is no specific limitation on its material and / or property.

[0079] In addition, the substrate layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the substrate layer BSL may be a transparent substrate, a translucent substrate, an opaque substrate, or a reflective substrate.

[0080] One area on the substrate layer BSL is defined as the display area DA where the pixels PXL are disposed, and another area thereof is defined as the non-display area NDA. For example, the substrate layer BSL may include a display area DA and a non-display area NDA. The display area DA includes a plurality of pixel areas in which the corresponding pixels PXL are formed, and the non-display area NDA is disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0081] In an embodiment, the pixels PXL may be distributed and arranged in the display area DA. In an embodiment, the pixels PXL may be arranged in a stripe or PENTILE ® arrangement structure in the display area DA. However, the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in the display area DA in various known arrangement manners.

[0082] Each pixel PXL may include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a power voltage (e.g., a first power voltage and a second power voltage). For example, according to Figures 1a to 3bThe light-emitting diode LD in any one of the embodiments. For example, each pixel PXL may include at least one light-emitting diode LD having a small size ranging from nanometers to micrometers. For example, each pixel PXL may include a plurality of rod-shaped light-emitting diodes connected in parallel between a pixel electrode and / or a power line. The plurality of rod-shaped light-emitting diodes may form a light-emitting device (e.g., a light source or a light source unit of each pixel PXL) of each pixel PXL.

[0083] In an embodiment, each pixel PXL may be formed of an active pixel. However, the type, structure, and / or driving scheme of the pixel PXL applicable to the display device according to the present disclosure are not particularly limited. For example, each pixel PXL may have the same structure as the pixels of various known passive light-emitting display devices or active light-emitting display devices.

[0084] Figures 5a to 5c is a circuit diagram showing a light-emitting device according to an embodiment of the present disclosure, and shows different embodiments of an active pixel PXL including the light-emitting device, for example. In an embodiment, Figures 5a to 5c Each pixel PXL shown in may be any one of the pixels PXL provided in Figure 4 the display panel PNL. The pixels PXL may have substantially the same or similar structures.

[0085] Referring to Figure 5a , a pixel PXL according to an embodiment of the present disclosure may include a light source unit LSU configured to generate light having a luminance corresponding to a data signal and a pixel circuit PXC configured to drive the light source unit LSU. The light source unit LSU may form a light-emitting device according to an embodiment of the present disclosure.

[0086] In an embodiment, the light source unit LSU may include a plurality of light-emitting diodes LD electrically connected between a first power supply VDD and a second power supply VSS. In an embodiment, the light-emitting diodes LD may be connected in parallel with each other, but the present disclosure is not limited thereto. For example, in an embodiment, the plurality of light-emitting diodes LD may be connected between the first power supply VDD and the second power supply VSS in a series / parallel combination structure.

[0087] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light-emitting diode LD can emit light. For example, the first power supply VDD may be set as a high-potential power supply, and the second power supply VSS may be set as a low-potential power supply. Here, at least during the light-emitting period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to be equal to or greater than the threshold voltage of the light-emitting diode LD.

[0088] Although Figure 5aAn embodiment is shown in which the light-emitting diodes LD of the light source unit LSU forming each pixel PXL are connected in parallel to each other in the same direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, but the present disclosure is not limited thereto. For example, in an embodiment, some of the light-emitting diodes LD may be connected to each other in a first direction (e.g., the forward direction) between the first power supply VDD and the second power supply VSS, while other light-emitting diodes LD may be connected to each other in a second direction (e.g., the reverse direction). Alternatively, in an embodiment, at least one pixel PXL may include only a single light-emitting diode LD (e.g., a single effective light-emitting diode connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0089] In an embodiment, the first ends of the light-emitting diodes LD forming each light source unit LSU may be commonly connected to the pixel circuit PXC through the first electrode of the light source unit LSU (also referred to as the "first pixel electrode" or "first alignment electrode"), and may be connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1. The second ends of the light-emitting diodes LD may be commonly connected to the second power supply VSS through the second electrode of the light source unit LSU (also referred to as the "second pixel electrode" or "second alignment electrode") and the second power line PL2.

[0090] Each light source unit LSU may emit light having a brightness corresponding to the driving current supplied thereto through the corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0091] The pixel circuit PXC may be connected to the scan line Si and the data line Dj corresponding to the pixel PXL. For example, if the pixel PXL is disposed in the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0092] The first transistor (also referred to as the "driving transistor") T1 is connected between the first power supply VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control the driving current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0093] A second transistor (also referred to as a "switching transistor") T2 can be connected between a data line Dj and a first node N1. The gate electrode of the second transistor T2 is connected to a scan line Si. When a scan signal that supplies a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj.

[0094] During each frame period, data signals corresponding to the frame are supplied to the data line Dj. The data signals are transmitted via the second transistor T2 to the first node N1. Accordingly, a voltage corresponding to the data signals is charged into the storage capacitor Cst.

[0095] One electrode of the storage capacitor Cst is connected to a first power supply VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signals to be supplied to the first node N1 during each frame period.

[0096] Although in Figure 5a , the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, the present disclosure is not limited thereto. In other words, either the first transistor T1 or the second transistor T2 can be an N-type transistor.

[0097] For example, as shown in Figure 5b , both the first transistor T1 and the second transistor T2 can be formed of N-type transistors. Except for the fact that the connection positions of some circuit elements change according to the change in the type of transistors, Figure 5b the structure and operation of the pixel PXL shown in Figure 5a are substantially similar to the structure and operation of the pixel PXL in Figure 5b . Accordingly, the detailed description of the pixel PXL in

[0098] The structure of the pixel circuit PXC is not limited to the embodiments shown in Figure 5a and Figure 5b . In other words, the pixel circuit PXC can be formed of known pixel circuits that can have various structures and / or operate through various driving schemes. For example, the pixel circuit PXC can be constructed in the same manner as the embodiments shown in Figure 5c .

[0099] Referring to Figure 5c, the pixel circuit PXC can be connected not only to the scan line Si corresponding to the horizontal row, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL set in the i-th row of the display area DA can also be connected to the (i - 1)-th scan line Si-1 and / or the (i + 1)-th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to a third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC can include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0100] The first transistor T1 is connected between the first power supply VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the drive current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0101] The second transistor T2 is connected between the data line Dj and one electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal with a gate-conducting voltage is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj to the said one electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj can be transmitted to the first transistor T1.

[0102] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal with a gate-conducting voltage is supplied from the scan line Si, the third transistor T3 can be turned on to electrically connect the first transistor T1 in the form of a diode.

[0103] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the (i - 1)-th scan line Si-1. When a scan signal with a gate-conducting voltage is supplied to the (i - 1)-th scan line Si-1, the fourth transistor T4 can be turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint can be equal to or less than the minimum voltage of the data signal.

[0104] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 can be turned off when an emission control signal with a gate cut-off voltage (e.g., a high voltage) is supplied to the emission control line Ei, and can be turned on in other cases.

[0105] The sixth transistor T6 is connected between the first transistor T1 and the second node N2 connected to the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 can be turned off when an emission control signal with a gate cut-off voltage is supplied to the emission control line Ei, and can be turned on in other cases.

[0106] The seventh transistor T7 is connected between the second node N2 and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage, for example, connected to the (i + 1)-th scan line Si+1. When a scan signal with a gate conduction voltage is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 can be turned on so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light source unit LSU.

[0107] The storage capacitor Cst can be connected between the first power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0108] Although the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit PXC in Figure 5c have been shown to be formed of P-type transistors, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 can be an N-type transistor.

[0109] The structure of the pixel PXL to which the present disclosure can be applied is not limited to Figures 5a to 5c the embodiment shown therein, and each pixel PXL can have various known structures. For example, the pixel circuit PXC included in each pixel PXL can be formed of a known pixel circuit that can have various structures and / or operate through various driving schemes. In the embodiments of the present disclosure, each pixel PXL can be constructed in a passive light-emitting display device or the like. In this case, the pixel circuit PXC can be omitted, and each of the first pixel electrode and the second pixel electrode of the light source unit LSU can be directly connected to the scan line Si, the data line Dj, the power line, and / or the control line.

[0110] Figure 6a and Figure 6bThese are all plan views showing a light-emitting device according to an embodiment of the present disclosure, and for example, different embodiments of a pixel PXL including a light source unit LSU formed by the light-emitting device are shown. In an embodiment, the pixel PXL can be any one of the pixels PXL shown in Figures 5a to 5c but the present disclosure is not limited thereto. Figure 7 is a plan view showing an insulating pattern INP according to an embodiment of Figure 6a and Figure 6b .

[0111] Although for illustrative purposes, Figure 6a and Figure 6b only show the display element layer on which the light source unit LSU is provided, each pixel PXL may also selectively include circuit elements configured to control the light source unit LSU (for example, at least one circuit element for forming Figures 5a to 5c of the pixel circuit PXC). In addition, in an embodiment, Figure 6a and Figure 6b show an embodiment in which the light source unit LSU is connected to a predetermined power line (for example, the first power line PL1 and / or the second power line PL2), circuit elements (for example, at least one circuit element forming the pixel circuit PXC), and / or signal lines (for example, the scan line Si and / or the data line Dj) through the first contact hole CH1 and the second contact hole CH2, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrode ELT1 and the second electrode ELT2 provided in the light-emitting device may be directly connected to a predetermined power line and / or signal line without passing through a contact hole and / or an intermediate line.

[0112] Referring to Figures 6a to 7 , a light-emitting device according to an embodiment of the present disclosure and a pixel PXL including the light-emitting device may include a predetermined light-emitting region EMA, at least one first electrode ELT1 and at least one second electrode ELT2 provided in the light-emitting region EMA, and at least one light-emitting diode LD connected between the first electrode ELT1 and the second electrode ELT2. For example, the pixel PXL may include a plurality of light-emitting diodes LD connected in series and / or in parallel with each other between the first electrode ELT1 and the second electrode ELT2. In addition, the pixel PXL may further include an insulating pattern INP provided in the light-emitting region EMA and disposed to overlap the first electrode ELT1 and the second electrode ELT2. In an embodiment, the insulating pattern INP may be provided under the first electrode ELT1, the second electrode ELT2, and the light-emitting diode LD.

[0113] In addition, the pixel PXL may optionally include at least one first contact electrode CNE1 disposed to overlap each first electrode ELT1 and / or at least one second contact electrode CNE2 disposed to overlap each second electrode ELT2. For example, as Figure 6a shown, the pixel PXL according to an embodiment may not include the first contact electrode CNE1 and the second contact electrode CNE2. In this case, the light-emitting diode LD may be directly connected to the first electrode ELT1 and the second electrode ELT2. As Figure 6b shown, the pixel PXL according to an embodiment may include the first contact electrode CNE1 and the second contact electrode CNE2. In this case, the light-emitting diode LD may be connected to the first electrode ELT1 and the second electrode ELT2 through the first contact electrode CNE1 and the second contact electrode CNE2, or directly connected to the first contact electrode CNE1 and the second contact electrode CNE2 and the first electrode ELT1 and the second electrode ELT2.

[0114] The light-emitting area EMA may be an area where the light-emitting diode LD (specifically, the effective light-emitting diode effectively connected between the first electrode ELT1 and the second electrode ELT2) of the light source unit LSU forming the pixel PXL is disposed. The light-emitting area EMA may be surrounded by a light-shielding bank or a reflective bank (also referred to as a "pixel defining layer") not shown.

[0115] The insulating pattern INP may include at least one recess RCS and a protrusion PTS protruding from the recess RCS. For example, the insulating pattern INP may include a plurality of recesses RCS dispersed at a predetermined interval in the light-emitting area EMA in the first direction DR1 and the second direction DR2. In an embodiment, the recesses RCS may be uniformly dispersed in the light-emitting area EMA. For example, the recesses RCS may be uniformly distributed at a predetermined interval in the first direction DR1 and / or the second direction DR2. In an embodiment, the plurality of recesses RCS may be non-uniformly dispersed in the insulating pattern INP.

[0116] In an embodiment, each recessed RCS may be disposed in a region including an area formed between a first electrode ELT1 and a second electrode ELT2. Further, when at least one light emitting diode LD is oriented in a first direction DR1 (e.g., a horizontal direction) intersecting the first electrode ELT1 and the second electrode ELT2 and connected between a pair of corresponding first electrode ELT1 and second electrode ELT2, each recessed RCS may have a first width W1 greater than the length of each light emitting diode LD in at least the first direction DR1. Further, in an embodiment, each recessed RCS may have a second width W2 equal to the first width W1 in a second direction DR2 (e.g., a vertical direction) intersecting the first direction DR1 (e.g., perpendicular to the first direction DR1). For example, each recessed RCS may have a circular shape in a plan view. However, the shape of the recessed RCS may be changed in various ways. For example, in a plan view, each recessed RCS may have a circular shape, an oval shape, a polygonal shape, or a combination thereof.

[0117] The surface of the insulating pattern INP may have an uneven profile due to the recessed RCS and the protrusions PTS. The first electrode ELT1, the second electrode ELT2, and the light emitting diode LD may be disposed on the insulating pattern INP.

[0118] The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other and arranged such that at least a part of them faces each other. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed on a substrate layer ( Figure 4 BSL) on which the insulating pattern INP is disposed, and may be arranged in parallel at positions spaced apart from each other by a predetermined distance in the first direction DR1. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed in the light emitting area EMA at positions spaced apart from each other by a predetermined distance in the first direction DR1, and each electrode may have a strip shape extending in a second direction DR2 intersecting (perpendicular to) the first direction DR1. However, the present disclosure is not limited thereto, and the shape and / or relative arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0119] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, each first electrode ELT1 may include at least one reflective electrode layer, and selectively further include at least one transparent electrode layer and / or a conductive cover layer. Similarly, each second electrode ELT2 may include at least one reflective electrode layer, and selectively further include at least one transparent electrode layer and / or a conductive cover layer.

[0120] In an embodiment, the first electrode ELT1 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., the first power line PL1), and / or a signal line (e.g., the scan line Si, the data line Dj, or a predetermined control line) through the first connection electrode CNL1 and the first contact hole CH1. For example, the first electrode ELT1 may be electrically connected to a predetermined circuit element disposed therebelow through the first connection electrode CNL1 and the first contact hole CH1. Optionally, in an embodiment, the first electrode ELT1 may be directly connected to a predetermined power line or signal line without passing through the first connection electrode CNL1, the first contact hole CH1, and / or the circuit element. In this case, the first electrode ELT1 may be integrally or non-integrally connected to the predetermined power line or signal line.

[0121] In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions. For example, when the first connection electrode CNL1 extends in the first direction DR1, the first electrode ELT1 may extend in a second direction DR2 intersecting the first direction DR1.

[0122] In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be integrally connected to each other. For example, the first electrode ELT1 may branch from the first connection electrode CNL1 in at least one way. In the case where the first electrode ELT1 and the first connection electrode CNL1 are integrally connected to each other, the first connection electrode CNL1 may be regarded as a region of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be separately formed and electrically connected to each other through at least one contact hole or via hole, etc.

[0123] In an embodiment, the second electrode ELT2 may be electrically connected to a predetermined circuit element (e.g., at least one transistor forming the pixel circuit PXC), a power line (e.g., the second power line PL2), and / or a signal line (e.g., the scan line Si, the data line Dj, or a predetermined control line) through the second connection electrode CNL2 and the second contact hole CH2. For example, the second electrode ELT2 may be electrically connected to the second power line PL2 disposed therebelow through the second connection electrode CNL2 and the second contact hole CH2. Optionally, in an embodiment, the second electrode ELT2 may be directly connected to a predetermined power line or signal line without passing through the second connection electrode CNL2 and / or the second contact hole CH2. In this case, the second electrode ELT2 may be integrally or non-integrally connected to the predetermined power line or signal line.

[0124] In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions. For example, when the second connection electrode CNL2 extends in a first direction DR1, the second electrode ELT2 may extend in a second direction DR2 intersecting the first direction DR1.

[0125] In an embodiment, the second electrode ELT2 may be integrally connected to the second connection electrode CNL2. For example, the second electrode ELT2 may branch from the second connection electrode CNL2 in at least one manner. In the case where the second electrode ELT2 and the second connection electrode CNL2 are integrally connected to each other, the second connection electrode CNL2 may be regarded as a region of the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may be separately formed and electrically connected to each other through at least one contact hole or via hole, etc.

[0126] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed on the insulating pattern INP and are disposed to overlap different regions of at least one recess RCS formed in the insulating pattern INP. For example, each first electrode ELT1 may overlap a first region AR1 of at least one recess RCS among a plurality of recesses RCS formed in the insulating pattern INP and protrusions PTS in the periphery of the first region AR1. Each second electrode ELT2 may overlap a second region AR2 of at least one recess RCS and protrusions PTS in the periphery of the second region AR2. In an embodiment, each second region AR2 may be a region facing away from the corresponding first region AR1. For example, each recess RCS may include a first region AR1 and a second region AR2, the first region AR1 overlapping the first electrode ELT1, and the second region AR2 being disposed at a position opposite to the first region AR1 and overlapping the second electrode ELT2 corresponding to the first electrode ELT1.

[0127] Both the first electrode ELT1 and the second electrode ELT2 may have uneven portions corresponding to the shape of the insulating pattern INP. For example, both the first electrode ELT1 and the second electrode ELT2 may be recessed downward in a region corresponding to the recess RCS of the insulating pattern INP and protrude upward in a region corresponding to the protrusions PTS of the insulating pattern INP. Both the first electrode ELT1 and the second electrode ELT2 may have an inclined surface or a curved surface corresponding to the contour of the insulating pattern INP in a boundary region between the recess RCS and the protrusions PTS of the insulating pattern INP.

[0128] At least one light-emitting diode LD may be disposed in each light-emitting area EMA in which an insulating pattern INP and a first electrode ELT1 and a second electrode ELT2 are disposed. For example, in each recess RCS, at least one light-emitting diode LD may be disposed. For example, at least one light-emitting diode LD may be disposed in the recess RCS such that at least one light-emitting diode LD is surrounded by any one of the recesses RCS.

[0129] In an embodiment, when the insulating pattern INP includes a plurality of recesses RCS, at least one light-emitting diode LD may be disposed in each of the recesses RCS. However, the present disclosure is not limited thereto. For example, in an embodiment, at least one light-emitting diode LD may be disposed only in some of the plurality of recesses RCS.

[0130] Each light-emitting diode LD may be electrically connected between a corresponding first electrode ELT1 and a second electrode ELT2. For example, each light-emitting diode LD may be a rod-shaped light-emitting diode having a longitudinal direction. In addition, the light-emitting diode LD may include a first end EP1 and a second end EP2. The first end EP1 is disposed at one end of the light-emitting diode LD in the longitudinal direction and is electrically connected to the first electrode ELT1, and the second end EP2 is disposed at the other end of the light-emitting diode LD in the longitudinal direction and is electrically connected to the second electrode ELT2. For example, in an area where the corresponding first electrode ELT1 and second electrode ELT2 are disposed to face each other (for example, in each recess RCS), each light-emitting diode LD may be arranged in a horizontal direction between the first electrode ELT1 and the second electrode ELT2 along a first direction DR1.

[0131] Although Figure 6a and Figure 6b it is shown that the light-emitting diodes LD are uniformly oriented in any one direction (for example, in the first direction DR1), the present disclosure is not limited thereto. For example, at least one of the light-emitting diodes LD may be oriented in a diagonal direction between the first electrode ELT1 and the second electrode ELT2. Alternatively, although not shown in Figure 6a and Figure 6b at least one ineffective light-emitting diode that is not fully connected between the first electrode ELT1 and the second electrode ELT2 may be further disposed in each light-emitting area EMA and / or the peripheral area of the light-emitting area EMA.

[0132] In an embodiment, each light-emitting diode LD may be a light-emitting diode made of a material having an inorganic crystal structure and having an ultra-small size (for example, in the range from the nanoscale to the microscale). For example, as Figures 1a to 3bAs shown, each light-emitting diode LD may be an ultra-small rod-shaped light-emitting diode having a diameter D and / or a length L ranging from the nanometer scale to the micrometer scale. However, the size of the light-emitting diode LD may be changed in various ways according to the design conditions of each light-emitting device (e.g., pixel PXL), etc.

[0133] In an embodiment, a first end EP1 of the light-emitting diode LD (e.g., an effective light-emitting diode completely connected between the first electrode ELT1 and the second electrode ELT2) may be electrically connected to the first electrode ELT1 via the first contact electrode CNE1. A second end EP2 of the light-emitting diode LD may be connected to the second electrode ELT2 via the second contact electrode CNE2. In an embodiment, at least one of the first end EP1 and the second end EP2 of each light-emitting diode LD may be in direct contact with the first electrode ELT1 and / or the second electrode ELT2 and may be electrically connected to the first electrode ELT1 and / or the second electrode ELT2.

[0134] In an embodiment, the light-emitting diode LD may be prepared in a diffusion form in a predetermined solution and then supplied to the light-emitting area EMA by an inkjet scheme or the like. For example, the light-emitting diode LD may be mixed with a volatile solvent and supplied to each light-emitting area EMA. Here, if a predetermined alignment voltage (or alignment signal) is applied to the first electrode ELT1 and the second electrode ELT2, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light-emitting diode LD may be aligned between the first electrode ELT1 and the second electrode ELT2. After the light-emitting diode LD has been aligned, the solvent may be removed by a volatilization scheme or other scheme. In this way, the light-emitting diode LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 may be respectively formed on opposite ends (i.e., the first end EP1 and the second end EP2) of the light-emitting diode LD. Therefore, the light-emitting diode LD may be more reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0135] In an embodiment, the first contact electrode CNE1 may be formed on at least one area of the first end EP1 of the light-emitting diode LD and the first electrode ELT1, whereby the first end EP1 of the light-emitting diode LD may be electrically connected to the first electrode ELT1. Similarly, the second contact electrode CNE2 may be formed on at least one area of the second end EP2 of the light-emitting diode LD and the second electrode ELT2, whereby the second end EP2 of the light-emitting diode LD may be electrically connected to the second electrode ELT2. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 fix the first end EP1 and the second end EP2 of each light-emitting diode LD, so that the light-emitting diode LD may be prevented from being removed from its aligned position.

[0136] If a first end EP1 of a light-emitting diode LD is connected to a first power supply VDD via a first electrode ELT1 and / or a pixel circuit PXC or the like, and a second end EP2 of the light-emitting diode LD is connected to a second power supply VSS via a second electrode ELT2 and / or a second power line PL2 or the like, at least one light-emitting diode LD connected in the forward direction between the first electrode ELT1 and the second electrode ELT2 can emit light with a brightness corresponding to a driving current supplied from the pixel circuit PXC or the like. Accordingly, the pixel PXL can emit light.

[0137] Figure 8a and Figure 8b are cross-sectional views showing a light-emitting device according to an embodiment of the present disclosure, and, for example, show different embodiments of a cross-section corresponding to a line I-I’ of Figure 6b . Figure 9 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and, for example, shows an embodiment of a cross-section corresponding to a line II-II’ of Figure 6b .

[0138] Referring to Figures 6a to 9 , a light-emitting device according to an embodiment of the present disclosure (for example, a pixel PXL including a light source unit LSU formed of a light-emitting device) may include a substrate layer BSL, an insulating pattern INP, a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, at least one light-emitting diode LD, a second insulating layer INS2, a first contact electrode CNE1 and a second contact electrode CNE2, and a third insulating layer INS3. In an embodiment, the light-emitting device may further selectively include a pixel circuit layer PCL between the substrate layer BSL and the insulating pattern INP.

[0139] The pixel circuit layer PCL may include at least one circuit element (for example, at least one transistor and / or capacitor) forming the pixel circuit PXC, and at least one power line and / or signal line or the like. Here, in a case where the light-emitting device is directly connected to a first power line PL1 and a second power line PL2 (or a predetermined signal line), the pixel circuit layer PCL may be omitted.

[0140] The insulating pattern INP may include an insulating material including an inorganic material or an organic material. For example, the insulating pattern INP may include at least one inorganic layer including various known inorganic insulating materials such as SiN x or SiO x . Optionally, the insulating pattern INP may include at least one organic layer and / or a photoresist layer including various known organic insulating materials, or may form a single-layer insulator or a multi-layer insulator including a combination of an organic material / inorganic material. In an embodiment of the present disclosure, the constituent materials in the insulating pattern INP may be changed in various ways.

[0141] In an embodiment, the insulating pattern INP may be used as a reflector. For example, the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2 disposed thereon may be used as reflectors for guiding the light emitted from each light emitting diode LD in a desired direction, thereby improving the optical efficiency of the pixel PXL.

[0142] In an embodiment, the insulating pattern INP may include at least one recess RCS in which a light emitting diode LD or the like is disposed and a protrusion PTS surrounding the recess RCS. The recess RCS may include an inclined surface having an inclination within a predetermined angle (θ) range in a peripheral region BOR adjacent to the protrusion PTS. In an embodiment, the insulating pattern INP may include a recess RCS having an angle (θ) ranging from 40° to 50°. In this case, the light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting diode LD can be guided to travel in the forward direction (e.g., toward the front surface of the display panel PNL). Therefore, the optical efficiency of each light emitting device and the pixel PXL including the light emitting device can be improved.

[0143] However, the present disclosure is not limited to the foregoing structure, and the shape of the insulating pattern INP can be changed in various ways. For example, in an embodiment of the present disclosure, the inclination range of the inclined surface can be changed, or the recess RCS can be formed by making the insulating pattern INP recessed such that at least one region of the insulating pattern INP has a smooth curved surface.

[0144] In an embodiment, in order to form a curvature on the surface of the insulating pattern INP, during the process of forming the insulating pattern INP, the insulating pattern INP can be patterned at different heights in a region by at least two mask processes, or the insulating pattern INP can be patterned at different heights in a region by a single mask process using a halftone mask. In this way, the recess RCS and the protrusion PTS can be formed in the surface of the insulating pattern INP. In other words, there is no specific limitation on the process of forming the insulating pattern INP, and it can be changed in various ways according to the embodiment.

[0145] In an embodiment, the height difference between the recess RCS and the protrusion PTS can be set to a value sufficient to accommodate each light emitting diode LD in the recess RCS. In this case, the insulating pattern INP can surround all sides of the light emitting diode LD disposed in the recess RCS.

[0146] The first electrode ELT1 and the second electrode ELT2 may be disposed on the insulating pattern INP at positions spaced apart from each other. In an embodiment, as Figure 6a and Figure 6bAs shown, the first electrode ELT1 and the second electrode ELT2 can be formed of strip-shaped electrodes that are parallel to each other at positions spaced apart from each other by a predetermined distance in the first direction DR1. In this case, the manufacturing process can be easily performed. Here, the shapes of the first electrode ELT1 and the second electrode ELT2 can be changed in various ways according to the embodiments.

[0147] Each of the first electrode ELT1 and the second electrode ELT2 can include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 can include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof), a conductive oxide (such as ITO, IZO, ZnO, or ITZO), and a conductive polymer (such as PEDOT); however, each of the first electrode ELT1 and the second electrode ELT2 is not limited thereto.

[0148] Each of the first electrode ELT1 and the second electrode ELT2 can have a single-layer structure or a multi-layer structure. For example, each of the first electrode ELT1 and the second electrode ELT2 can include at least one reflective electrode layer. Each of the first electrode ELT1 and the second electrode ELT2 can also selectively include at least one of at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0149] In an embodiment, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 can be formed of a conductive material having a constant reflectivity. For example, the reflective electrode layer can include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their alloys; however, the present disclosure is not limited thereto. In other words, the reflective electrode layer can be formed of various reflective conductive materials. Each of the first electrode ELT1 and the second electrode ELT2 including the reflective electrode layer can enable the light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light-emitting diodes LD to travel in the direction of the displayed image (e.g., in the forward direction). Specifically, if the first electrode ELT1 and the second electrode ELT2 have an inclined surface or a curved surface corresponding to the shape of the insulating pattern INP and are disposed to face the first end EP1 and the second end EP2 of the light-emitting diodes LD, the light emitted from the first end EP1 and the second end EP2 of each of the light-emitting diodes LD can be reflected by the first electrode ELT1 and the second electrode ELT2 and thus further reliably travel in the forward direction of the display panel PNL (e.g., in the upward direction of the substrate layer BSL). Therefore, the efficiency of the light emitted from the light-emitting diodes LD can be improved.

[0150] In addition, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO, or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. Thus, if both the first electrode ELT1 and the second electrode ELT2 are formed of a multi-layer structure of two or more layers, the voltage drop caused by signal delay (RC delay) can be minimized. Therefore, a desired voltage can be effectively transmitted to the light-emitting diode LD.

[0151] In addition, if each of the first electrode ELT1 and the second electrode ELT2 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layers of the first electrode ELT1 and the second electrode ELT2 can be prevented from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive cover layer may be selectively included in the first electrode ELT1 and the second electrode ELT2 and may be omitted according to the embodiment. In addition, the conductive cover layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or may be considered as a separate component provided on the first electrode ELT1 and the second electrode ELT2.

[0152] In an embodiment, the first electrode ELT1 and the second electrode ELT2 corresponding to each other may be arranged to face each other, and at least one recess RCS is provided therebetween. In addition, the first electrode ELT1 and the second electrode ELT2 may be provided on the insulating pattern INP such that the first electrode ELT1 and the second electrode ELT2 overlap different regions of the recess RCS.

[0153] Both the first electrode ELT1 and the second electrode ELT2 may have a curvature corresponding to the surface profile of the insulating pattern INP. For example, the first electrode ELT1 and the second electrode ELT2 may respectively include a first bending portion BP1 and a second bending portion BP2 having a curved shape at the upper end and the lower end of the inclined surfaces of the connection recess RCS and the protrusion PTS of the insulating pattern INP. In an embodiment, the first bending portion BP1 formed on the first electrode ELT1 may have a shape symmetric to the shape of the second bending portion BP2 formed on the second electrode ELT2. Thus, if the first electrode ELT1 and the second electrode ELT2 respectively include the first bending portion BP1 and the second bending portion BP2, in the step of aligning the light-emitting diode LD, the electric field generated between the first electrode ELT1 and the second electrode ELT2 may be further concentrated on the first bending portion BP1 and the second bending portion BP2. Therefore, the number of light-emitting diodes LD moving into and / or around the recess RCS can be increased, so that the light-emitting diodes LD can be aligned between the first electrode ELT1 and the second electrode ELT2. Therefore, the alignment efficiency of the light-emitting diodes LD can be improved.

[0154] The first insulating layer INS1 may be formed to cover an area of each of the first electrode ELT1 and the second electrode ELT2, and may include an opening to expose another area of each of the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first insulating layer INS1 may be mainly formed to cover the entire surfaces of the first electrode ELT1 and the second electrode ELT2. After supplying and aligning the light-emitting diodes LD on the first insulating layer INS1 (e.g., on the first insulating layer INS1 over the recess RCS), the first insulating layer INS1 may be patterned in the form of a separate pattern, in which, as Figure 8a shown, the first insulating layer INS1 is partially opened to expose the first electrode ELT1 and the second electrode ELT2 of the predetermined first contact portion CNT1 and the second contact portion CNT2, respectively, or as Figure 8b shown, the first insulating layer INS1 is partially disposed under the light-emitting diodes LD.

[0155] In other words, the first insulating layer INS1 may be disposed between the first electrode ELT1 and the second electrode ELT2 and the light-emitting diodes LD, and may expose an area of each of the first electrode ELT1 and the second electrode ELT2. After forming the first electrode ELT1 and the second electrode ELT2, the first insulating layer INS1 may be formed to cover the first electrode ELT1 and the second electrode ELT2, so as to prevent the first electrode ELT1 and the second electrode ELT2 from being damaged or to prevent metal precipitation in subsequent processes. In addition, the first insulating layer INS1 may stably support each light-emitting diode LD.

[0156] A plurality of light emitting diodes LD may be supplied onto each light emitting area EMA on which a first insulating layer INS1 is formed, and aligned on each light emitting area EMA on which the first insulating layer INS1 is formed. For example, the plurality of light emitting diodes LD may be supplied to each light emitting area EMA by an inkjet scheme, and at least some of the light emitting diodes LD may be aligned in the recess RCS.

[0157] For example, at least one light emitting diode LD may be disposed in each recess RCS. For example, the light emitting diode LD may be disposed above the first insulating layer INS1 on the recess RCS, and thus surrounded by the recess RCS of the insulating pattern INP and / or the inclined surfaces (or curved surfaces) of the first electrode ELT1 and the second electrode ELT2 disposed on the recess RCS. In other words, in an embodiment, the recess RCS of the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2 may surround all sidewalls of the light emitting diode LD. Therefore, the light emitted from the light emitting diode LD may be reflected by the recess RCS of the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2, and travel in the forward direction of the light emitting device and the display device including the light emitting device (e.g., toward the front surface on which an image is displayed).

[0158] Specifically, among the light emitting diodes LD disposed in the recess RCS, a first end EP1 of the light emitting diode LD oriented in a first direction DR1 including a predetermined error angle range may be disposed to face an inclined surface (or curved surface) formed on the first electrode ELT1 through the insulating pattern INP. In addition, a second end EP2 of the light emitting diode LD may be disposed to face an inclined surface (or curved surface) formed on the second electrode ELT2 through the insulating pattern INP. Each light emitting diode LD may emit light through the first end EP1 and the second end EPT2. Therefore, the light emitted from the light emitting diode LD may travel more reliably in the forward direction (e.g., in Figures 8a to 9 the upward direction of the base layer BSL in the cross-sectional view). In addition, even when at least one light emitting diode LD disposed in each light emitting area EMA is disposed in a diagonal direction or the like between the first electrode ELT1 and the second electrode ELT2, if the light emitting diode LD is disposed in the recess RCS, the light emitted from the light emitting diode LD may also travel more reliably in the forward direction. According to an embodiment of the present disclosure, the amount of light emitted from the light emitting diode LD traveling in a desired direction may be increased. Therefore, the efficiency of the light emitted from each light emitting area EMA may be improved.

[0159] The second insulating layer INS2 may be disposed on the light-emitting diode LD (specifically, at least one light-emitting diode LD aligned between the first electrode ELT1 and the second electrode ELT2), and may expose the first end EP1 and the second end EP2 of the light-emitting diode LD. For example, the second insulating layer INS2 may be disposed only partially on top of a region of the light-emitting diode LD without covering the first end EP1 and the second end EP2 of the light-emitting diode LD. The second insulating layer INS2 may be formed as an independent pattern on each light-emitting region EMA; however, the present disclosure is not limited thereto.

[0160] As Figure 8a and Figure 8b shown in, if there is a space between the first insulating layer INS1 and the light-emitting diode LD before the second insulating layer INS2 is formed, the space may be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. For example, in the case where the first insulating layer INS1 is formed of at least one inorganic insulating layer, the first insulating layer INS1 may be formed to be recessed along the contour of the bottom surface between the first electrode ELT1 and the second electrode ELT2. In the case where the light-emitting diodes LD, each having a length greater than the width of the recess formed in the first insulating layer INS1, are horizontally disposed on the first insulating layer INS1, a space may be formed between the light-emitting diodes LD and the first insulating layer INS1. The space may be filled with the insulating material for forming the second insulating layer INS2 in a subsequent process step (e.g., in the process step of forming the second insulating layer INS2 on the light-emitting diode LD). Thus, if the second insulating layer INS2 flows under the light-emitting diode LD and is filled into the space under the light-emitting diode LD, the light-emitting diode LD may be more stably supported.

[0161] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first electrode ELT1 and the second electrode ELT2 and the first end EP1 and the second end EP2 of the light-emitting diode LD. In an embodiment, as Figure 8a shown in, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer. In this case, although the first contact electrode CNE1 and the second contact electrode CNE2 are formed of the same conductive material through the same process, the present disclosure is not limited thereto.

[0162] In an embodiment, as Figure 8bAs shown, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on different layers. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed by different processes using the same conductive material or different conductive materials. When the first contact electrode CNE1 and the second contact electrode CNE2 are disposed on different layers, at least one insulating layer (e.g., the fourth insulating layer INS4) can be formed on the contact electrode (e.g., the first contact electrode CNE1) disposed on the lower layer.

[0163] The first contact electrode CNE1 and the second contact electrode CNE2 can electrically connect the first end EP1 and the second end EP2 of the light-emitting diode LD to the first electrode ELT1 and the second electrode ELT2, respectively.

[0164] For example, the first contact electrode CNE1 can be disposed on each first electrode ELT1 to contact the first electrode ELT1. For example, the first contact electrode CNE1 can be disposed on an area (e.g., the first contact portion CNT1) of the first electrode ELT1 that is not covered by the first insulating layer INS1, such that the first contact electrode CNE1 contacts the first electrode ELT1. In addition, the first contact electrode CNE1 can be disposed on the first end EP1 of at least one light-emitting diode LD adjacent to the first electrode ELT1, e.g., on the respective first ends EP1 of a plurality of light-emitting diodes LD, such that the first contact electrode CNE1 can contact the first end EP1. In other words, the first contact electrode CNE1 can be arranged to cover at least one area of the respective first end EP1 of the light-emitting diode LD and the corresponding first electrode ELT1. Therefore, the respective first ends EP1 of the light-emitting diodes LD can be electrically connected to the first electrode ELT1.

[0165] Similarly, the second contact electrode CNE2 can be disposed on each second electrode ELT2 to contact the second electrode ELT2. For example, the second contact electrode CNE2 can be disposed on an area (e.g., the second contact portion CNT2) of the second electrode ELT2 that is not covered by the first insulating layer INS1, such that the second contact electrode CNE2 contacts the second electrode ELT2. In addition, the second contact electrode CNE2 can be disposed on the second end EP2 of at least one light-emitting diode LD adjacent to the second electrode ELT2, e.g., on the respective second ends EP2 of a plurality of light-emitting diodes LD, such that the second contact electrode CNE2 can contact the second end EP2. In other words, the second contact electrode CNE2 can be arranged to cover at least one area of the respective second end EP2 of the light-emitting diode LD and the corresponding second electrode ELT2. Therefore, the respective second ends EP2 of the light-emitting diodes LD can be electrically connected to the second electrode ELT2.

[0166] In the case where the first contact electrode CNE1 and the second contact electrode CNE2 are not provided as shown in the embodiment such as Figure 6a , the first end EP1 and the second end EP2 of the light-emitting diode LD can be in direct contact with the first electrode ELT1 and the second electrode ELT2. In this case, the first insulating layer INS1 may not be disposed between the first end EP1 and the second end EP2 of the light-emitting diode LD and the first electrode ELT1 and the second electrode ELT2 of the light-emitting diode LD.

[0167] The third insulating layer INS3 may be formed and / or disposed on one surface of the substrate layer BSL on which the insulating pattern INP, the first electrode ELT1 and the second electrode ELT2, the light-emitting diode LD, and the first contact electrode CNE1 and the second contact electrode CNE2 are formed, such that the third insulating layer INS3 can cover the first electrode ELT1 and the second electrode ELT2, the light-emitting diode LD, and the first contact electrode CNE1 and the second contact electrode CNE2. In an embodiment, the third insulating layer INS3 may include a thin film encapsulation layer including at least one inorganic layer and / or organic layer.

[0168] In an embodiment, each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may have a single-layer structure or a multi-layer structure and include at least one inorganic insulating material and / or organic insulating material. For example, each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include various known organic insulating materials / inorganic insulating materials including SiN x , and the constituent materials of each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 are not particularly limited. The first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may include the same insulating material.

[0169] Figure 10 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and for example, shows an embodiment of a cross-section corresponding to the line III-III’ of Figure 6b . In an embodiment, Figure 10 shows some circuit elements and / or lines provided in the pixel circuit layer PCL and the connection structure between the pixel circuit layer PCL and the display element layer DPL provided above the pixel circuit layer PCL (for example, a layer on which a light-emitting diode LD forming a light source unit LSU is provided). In Figure 10In the following, the same reference numerals are used to denote components similar or identical to those of the embodiments of Figures 6a to 9 and a further description thereof will be omitted.

[0170] Referring to Figures 6a to 10 , a light-emitting device according to an embodiment of the present disclosure may include a pixel circuit layer PCL disposed between a substrate layer BSL and a display element layer DPL. For example, the pixel circuit layer PCL may be formed on a surface of the substrate layer BSL, and the display element layer DPL may be formed on a surface of the substrate layer BSL on which the pixel circuit layer PCL is formed.

[0171] The pixel circuit layer PCL may include a pixel circuit for controlling the display element layer DPL (e.g., Figures 5a to 5c any one of the pixel circuits PXC shown in Figure 5a ) and / or lines connected to the pixel circuit PXC. For example, the pixel circuit layer PCL may include Figures 5a to 5c a first transistor T1 and a second transistor T2 shown in

[0172] . The pixel circuit layer PCL may further include

[0173] a storage capacitor Cst shown in

[0174] and various signal lines (e.g., a scan line Si and a data line Dj) connected to each pixel circuit PXC, and various power lines (e.g., a first power line PL1 and a second power line PL2) connected to the pixel circuit PXC and / or a light source unit LSU.

[0175] The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multi-layer having two or more layers. In the case where the buffer layer BFL has a multi-layer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0175] Each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, and a first transistor electrode ET1 and a second transistor electrode ET2. Although Figure 10 An embodiment is shown in which each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in an embodiment, the first transistor electrode ET1 and / or the second transistor electrode ET2 in at least one transistor provided in each pixel region may be integrally formed with the corresponding semiconductor layer SCL.

[0176] The semiconductor layer SCL may be provided on the buffer layer BFL. For example, the semiconductor layer SCL may be provided between the gate insulating layer GI and the substrate layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode ET1, a second region in contact with each second transistor electrode ET2, and a channel region provided between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0177] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with a predetermined impurity.

[0178] The gate electrode GE may be provided on the semiconductor layer SCL, and the gate insulating layer GI is disposed between the gate electrode GE and the semiconductor layer SCL. For example, the gate electrode GE may be provided between the gate insulating layer GI and the interlayer insulating layer ILD, and may overlap at least one region of the semiconductor layer SCL.

[0179] The first transistor electrode ET1 and the second transistor electrode ET2 may be provided above each semiconductor layer SCL and the corresponding gate electrode GE, and at least one interlayer insulating layer ILD is disposed between the first transistor electrode ET1 and the second transistor electrode ET2 and each semiconductor layer SCL and the corresponding gate electrode GE. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be provided between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be connected to the first region and the second region of each semiconductor layer SCL through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD, respectively.

[0180] In an embodiment, at least one transistor provided in the pixel circuit PXC may be connected to any one of the pixel electrodes. For example, any one of a first transistor electrode ET1 and a second transistor electrode ET2 of the first transistor T1 may be electrically connected to a first electrode ELT1 and / or a first connection electrode CNL1 of a light source unit LSU provided on the passivation layer PSV through a first contact hole CH1 penetrating the passivation layer PSV.

[0181] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be provided on the same layer as an electrode of each circuit element forming the pixel circuit PXC. For example, a second power line PL2 for supplying a voltage of a second power supply VSS may be provided on the same layer as gate electrodes GE of the first transistor T1 and the second transistor T2, and is electrically connected to a second electrode ELT2 and / or a second connection electrode CNL2 of the light source unit LSU provided on the passivation layer PSV through both a bridging pattern BRP provided on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2 and at least one second contact hole CH2 penetrating the passivation layer PSV. However, the structure and / or position, etc. of the second power line PL2 may be changed in various ways.

[0182] In an embodiment, the display element layer DPL may include a light source unit LSU for each pixel PXL. For example, the display element layer DPL may include at least one first electrode ELT1, at least one second electrode ELT2, and at least one light emitting diode LD electrically connected between the first electrode ELT1 and the second electrode ELT2. Additionally, the display element layer DPL may further include, for example, at least one conductive layer and / or insulating layer.

[0183] For example, the display element layer DPL may include an insulating pattern INP provided in each light emitting area EMA, at least one pair of a first electrode ELT1 and a second electrode ELT2 provided on the insulating pattern INP, and a plurality of light emitting diodes LD provided between the first electrode ELT1 and the second electrode ELT2, and may further selectively include a first contact electrode CNE1 and a second contact electrode CNE2 provided above a first end EP1 and a second end EP2 of each light emitting diode LD. Furthermore, the display element layer DPL may include a first insulating layer INS1, a second insulating layer INS2, and a third insulating layer INS3 provided in sequence, and may further selectively include Figure 8b the fourth insulating layer INS4 shown in. Since the structure of the display element layer DPL has been described in detail with reference to Figures 6a to 9 it, a detailed description thereof will be omitted.

[0184] According to Figures 6a to 10An embodiment includes an insulating pattern INP including at least one recessed RCS (e.g., a plurality of recessed RCSs) disposed below a first electrode ELT1 and a second electrode ELT2. At least one light-emitting diode LD is disposed in at least one of the plurality of recessed RCSs. A first end EP1 and a second end EP2 of the light-emitting diode LD may be electrically connected to the first electrode ELT1 and the second electrode ELT2, respectively. Sidewalls of the light-emitting diode LD including the first end EP1 and the second end EP2 may be surrounded by the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2. Accordingly, the efficiency of light emitted from each light-emitting area EMA may be improved.

[0185] Since the insulating pattern INP includes the recessed RCSs, when the solvent supplied to the light-emitting area EMA together with the light-emitting diode LD during the process of supplying the light-emitting diode LD is removed, the light-emitting diode LD may be more concentratedly disposed in the recessed RCSs of the insulating pattern INP. Accordingly, the light-emitting diode LD may be more easily disposed in a desired area.

[0186] In addition, according to Figures 6a to 10 an embodiment, the first electrode ELT1 and the second electrode ELT2 may include a first bending portion BP1 and a second bending portion BP2 corresponding to the shape of the insulating pattern INP in areas corresponding to each recessed RCS. Thus, if the first electrode ELT1 and the second electrode ELT2 include the first bending portion BP1 and the second bending portion BP2, when the light-emitting diode LD is supplied to each light-emitting area EMA and an alignment electric field for the light-emitting diode LD is formed by applying a predetermined alignment voltage to the first electrode ELT1 and the second electrode ELT2, the electric field may be significantly concentrated around the first bending portion BP1 and the second bending portion BP2. Accordingly, the alignment efficiency of the light-emitting diode LD may be improved. In other words, in an embodiment of the present disclosure, a larger number of light-emitting diodes LD may be more effectively aligned at a desired position. Accordingly, the alignment rate of the light-emitting diode LD may be improved.

[0187] Figure 11 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel PXL including a light source unit LSU formed by the light-emitting device. Figure 12 is showing according to Figure 11 a plan view of an insulating pattern INP according to an embodiment. Figure 13a and Figure 13b are both cross-sectional views showing a light-emitting device according to an embodiment of the present disclosure, and show, for example, different embodiments of a cross-section corresponding to line IV-IV' of Figure 11 the light-emitting device. Figure 14 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, corresponding to Figure 11An embodiment of a cross-section corresponding to the line V-V'. Figure 15 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a cross-section corresponding to the Figure 11 line VI-VI'. In Figures 11 to 15 the embodiment, the same reference numerals are used to denote components that are the same as or similar to the components of the Figures 6a to 10 embodiment, and a detailed description thereof will be omitted.

[0188] Referring to Figures 11 to 15 , the insulating pattern INP may include at least one opening OPN. For example, the insulating pattern INP may include a plurality of openings OPN corresponding to the respective recesses RCS.

[0189] For example, as shown in Figures 11 to 15 , each recess RCS according to the Figures 6a to 10 embodiment may be modified to include an opening OPN. For example, each recess RCS may include an opening OPN by making the bottom surface of the recess RCS open.

[0190] In the foregoing embodiment, the sidewalls of the light-emitting diode LD connected between the first electrode ELT1 and the second electrode ELT2 may also be surrounded by the insulating pattern INP and the first electrode ELT1 and the second electrode ELT2. Accordingly, the efficiency of light emitted from each light-emitting region EMA can be improved.

[0191] In addition, since the insulating pattern INP includes openings OPN corresponding to the recesses RCS, the light-emitting diodes LD can be more concentratedly disposed in each recess RCS, and the alignment efficiency of the light-emitting diodes LD can be further improved. Accordingly, the alignment rate of the light-emitting diodes LD can be improved.

[0192] Figure 16 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel PXL including a light source unit LSU formed by the light-emitting device. Figure 17 is a plan view showing an insulating pattern INP' according to an embodiment of Figure 16 . Figure 18 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, modifications related to the insulating pattern INP' of Figure 16 and Figure 17 . In the description of the Figures 16 to 18 embodiment, the same reference numerals will be used to denote components that are similar to or the same as the components of the previous embodiment, and a detailed description thereof will be omitted.

[0193] Referring to Figures 16 to 18, the insulating pattern INP’ may include a rectangular recess RCS’. For example, the insulating pattern INP’ may include a plurality of recesses RCS’ each having a square shape. In an embodiment, at least one recess RCS’ may selectively include an opening OPN’. In an embodiment, each opening OPN’ may have a shape corresponding to each recess RCS’. For example, the opening OPN’ may have a size corresponding to each recess RCS’ and have a square shape.

[0194] Figure 19 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and for example, shows an embodiment of a pixel PXL including a light source unit LSU formed by the light-emitting device. Figure 20 is a plan view showing an insulating pattern INP” according to an embodiment of Figure 19 . Figure 21 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and for example, shows a modification related to the insulating pattern INP’’ of Figure 19 and Figure 20 . In the description of the embodiment of Figures 19 to 21 , the same reference numerals will be used to denote components similar or identical to those of the previous embodiment, and their detailed description will be omitted.

[0195] Referring to Figures 19 to 21 , the insulating pattern INP’’ may include a recess RCS’’ having a rhombus shape. For example, the insulating pattern INP’’ may include a plurality of recesses RCS’’ each having a rhombus shape. In an embodiment, at least one recess RCS’’ may selectively include an opening OPN’’. In an embodiment, each opening OPN’’ may have a shape corresponding to each recess RCS’’. For example, the opening OPN’’ may have a size corresponding to each recess RCS’’ and have a rhombus shape.

[0196] As Figures 6a to 21As shown in the embodiments, the shape of each recess RCS, RCS', RCS'' and / or each opening OPN, OPN', OPN'' can be changed in various ways. For example, each recess RCS, RCS', RCS'' and / or each opening OPN, OPN', OPN'' can have a circular shape, a square shape or a rhombus shape. For example, each recess RCS, RCS', RCS'' and / or each opening OPN, OPN', OPN'' can have other shapes. For example, in the embodiments of the present disclosure, each recess RCS, RCS', RCS'' and / or each opening OPN, OPN', OPN'' can have an elliptical shape or a polygonal shape other than a square shape or a rhombus shape. Optionally, in the embodiments of the present disclosure, each recess RCS, RCS', RCS'' and / or each opening OPN, OPN', OPN'' can have a combination of a circular shape or an elliptical shape and a polygonal shape, for example, a shape including a combination of a linear edge and a curved edge.

[0197] In addition, the size of each recess RCS, RCS', RCS'' and / or each opening OPN, OPN', OPN'' can be changed in various ways. For example, the size of each recess RCS, RCS', RCS'' and / or each opening OPN, OPN', OPN'' can be changed in various ways according to the size, structure, etc. of each light-emitting region EMA, the first electrode ELT1 and the second electrode ELT2 and / or the light-emitting diode LD.

[0198] Figure 22 is a plan view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a pixel PXL including a light source unit LSU formed by the light-emitting device. Figure 23 is shown according to Figure 22 a plan view of the reflective electrode REF of the embodiment. Figure 24 is a cross-sectional view showing a light-emitting device according to an embodiment of the present disclosure, and shows, for example, an embodiment of a cross-section corresponding to the line VII-VII' of Figure 22 . In Figures 22 to 24 the description of the embodiment, the same reference numerals are used to denote components similar or identical to those of the above embodiments (for example, Figures 6a to 10 the embodiments), and their detailed descriptions will be omitted.

[0199] Referring to Figures 22 to 24 , a light-emitting device according to an embodiment of the present disclosure and a pixel PXL including the light-emitting device may further include a reflective electrode (or reflective pattern layer) REF disposed around the light-emitting diode LD.

[0200] In an embodiment, the reflective electrode REF may be disposed on the first insulating layer INS1 at a position adjacent to the light-emitting diode LD and include an opening OPNr corresponding to the light-emitting diode LD. For example, the reflective electrode REF may include at least one opening OPNr that partially overlaps with at least one recessed RCS portion.

[0201] For example, the reflective electrode REF may include at least one first-direction pattern PAT1 extending in a direction intersecting the first electrode ELT1 and the second electrode ELT2. For example, the reflective electrode REF may include a plurality of first-direction patterns PAT1 extending in a first direction DR1 perpendicular to the first electrode ELT1 and the second electrode ELT2 and arranged parallel to each other. The reflective electrode REF may include a second-direction pattern PAT2 connecting the first-direction patterns PAT1 to each other. In an embodiment, the first-direction pattern PAT1 and the second-direction pattern PAT2 may be integrally connected to each other, but the present disclosure is not limited thereto.

[0202] In an embodiment, the reflective electrode REF may be electrically isolated from the first electrode ELT1, the second electrode ELT2, and the light-emitting diode LD. To this end, a fifth insulating layer INS5 may be disposed on the reflective electrode REF. The reflective electrode REF may be floated to maintain electrical isolation and may be connected to a predetermined reference power source.

[0203] According to Figures 22 to 24 an embodiment of, an additional reflective electrode REF is formed around the light-emitting diode LD, so that the reflectivity of the light emitted from the light-emitting diode LD can be improved. For example, with respect to the second direction DR2, the reflectivity of the light emitted from the light-emitting diode LD can also be improved. Therefore, the efficiency of the light emitted from each light-emitting area EMA can be further improved.

[0204] Although the scope of the present disclosure has been described through detailed embodiments, it should be noted that the above embodiments are only descriptive and should not be considered restrictive. Those skilled in the art should understand that various changes, substitutions, and alterations can be made herein without departing from the scope of the present disclosure defined by the claims.

[0205] The scope of the present disclosure is not limited by the detailed description of the present disclosure and should be defined by the appended claims. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present disclosure.

Claims

1. A light-emitting device, the light-emitting device comprising: A light-emitting region; An insulating pattern disposed in the light-emitting region and including a first surface and at least one recess recessed from the first surface; A first electrode disposed on the insulating pattern and configured to overlap a first region of the recess and the first surface at the periphery of the first region; A second electrode disposed on the insulating pattern and spaced apart from the first electrode by a predetermined distance in a first direction, and configured to overlap a second region of the recess and the first surface at the periphery of the second region; A first insulating layer disposed in the recess and covering a part of the first electrode and a part of the second electrode; A light-emitting diode in the recess and disposed on the first insulating layer, and electrically connected between the first electrode and the second electrode; And A first contact electrode and a second contact electrode disposed on the first insulating layer.

2. The light-emitting device according to claim 1, wherein The recess includes an inclined surface having an inclination within a predetermined angular range.

3. The light-emitting device according to claim 2, wherein, Each of the first electrode and the second electrode includes a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

4. The light-emitting device according to claim 1, wherein, The recess has a circular shape, an elliptical shape, a polygonal shape, or a combination thereof in a plan view.

5. The light-emitting device according to claim 1, wherein, The recess includes an opening.

6. The light-emitting device according to claim 1, wherein, The recess has a width greater than the length of the light-emitting diode in the first direction.

7. The light-emitting device according to claim 1, wherein, The recess has the same width in the first direction and a second direction perpendicular to the first direction.

8. The light-emitting device according to claim 1, wherein, The light-emitting diode includes a rod-shaped light-emitting diode, and the rod-shaped light-emitting diode includes a first end and a second end disposed at opposite ends in a longitudinal direction.

9. The light-emitting device according to claim 8, wherein, The first contact electrode is disposed on the first end of the light-emitting diode and a region of the first electrode, and is configured to electrically connect the first end to the first electrode; And The second contact electrode is disposed on the second end of the light-emitting diode and a region of the second electrode, and is configured to electrically connect the second end to the second electrode.

10. The light-emitting device according to claim 9, wherein, The first insulating layer is disposed between the light-emitting diode and the first electrode and the second electrode, and is configured to expose the region of each of the first electrode and the second electrode.

11. The light-emitting device according to claim 10, the light-emitting device further comprising a reflective electrode disposed on the first insulating layer at a position adjacent to the light-emitting diode and including an opening corresponding to the light-emitting diode.

12. The light-emitting device according to claim 11, Among them, Each of the first electrode and the second electrode extends in a second direction intersecting the first direction, and Wherein, the reflective electrode includes at least one first-direction pattern extending in the first direction to intersect the first electrode and the second electrode.

13. The light-emitting device according to claim 1, Among them, The insulating pattern includes a plurality of recesses dispersed at a predetermined interval, and Wherein, at least one light-emitting diode is disposed in each of the plurality of recesses.

14. A display device, the display device comprising: A display area; And Pixels, disposed in the display area and including a light-emitting area, Wherein, the pixel includes: an insulating pattern disposed in the light-emitting area and including a first surface and at least one recess recessed from the first surface; a first electrode disposed on the insulating pattern and configured to overlap a first area of the recess and the first surface around the first area; a second electrode disposed on the insulating pattern and spaced apart from the first electrode by a predetermined distance in a first direction and configured to overlap a second area of the recess and the first surface around the second area; a first insulating layer disposed in the recess and covering a part of the first electrode and a part of the second electrode; a light-emitting diode disposed in the recess and on the first insulating layer and electrically connected between the first electrode and the second electrode; and a first contact electrode and a second contact electrode disposed on the first insulating layer.

15. The display device according to claim 14, Among them, The recess includes an inclined surface having an inclination within a predetermined angular range, and Wherein, each of the first electrode and the second electrode includes a bent portion having a bent shape at each of an upper end and a lower end of the inclined surface.

16. The display device according to claim 14, wherein The recess has a circular shape, an elliptical shape, a polygonal shape or a combination thereof in a plan view.

17. The display device according to claim 14, wherein, The recess includes an opening.

18. The display device according to claim 14, wherein, The recess has a width greater than the length of the light-emitting diode in the first direction.

19. The display device according to claim 14, wherein, The pixel further includes: A reflective electrode disposed at a position adjacent to the light-emitting diode and on the first insulating layer and including an opening corresponding to the light-emitting diode, and The first insulating layer is disposed between the light-emitting diode and the first electrode and the second electrode and includes an opening formed to expose an area of each of the first electrode and the second electrode.

20. The display device according to claim 14, Among them, The insulating pattern includes a plurality of recesses dispersed at a predetermined interval in the light-emitting area, and Wherein, at least one light-emitting diode is disposed in each of the plurality of recesses.

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