Circuit board defect detection method and system based on multi-band impedance matching

Abstract

This application discloses a method and system for detecting circuit board defects based on multi-band impedance matching, relating to the field of circuit board quality inspection technology. The method includes: determining the corresponding test bias voltage of a reconfigurable impedance matching network at multiple test frequencies based on a frequency bias voltage relationship table; applying a test bias voltage matching the test frequency to each adjustable element for each test frequency, and injecting an RF signal into the circuit board under test to acquire the corresponding reflection coefficient through a test probe; reconstructing a three-dimensional scattering image inside the circuit board based on a multi-frequency sparse dictionary and compressed sensing algorithm; calculating the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and combining the spatial information of each circuit physical layer to obtain the hierarchical anomaly score of the corresponding circuit physical layer, thereby screening at least one abnormal circuit physical layer. Thus, by using signal feature reconstruction instead of high-precision physical imaging, hierarchical spatial identification of circuit board defects is achieved.

Description

Technical Field

[0001] This application relates to the field of circuit board quality inspection technology, and in particular to a method and system for detecting circuit board defects based on multi-band impedance matching. Background Technology

[0002] With the large-scale deployment of 5G, millimeter-wave radar, and vehicle-mounted millimeter-wave communication terminals, printed circuit boards (PCBs) are developing towards high-density interconnect (HDI), multi-layer blind and buried vias, and fine line width and spacing, which greatly improves the RF, power, and signal integrity performance of the board. However, this also brings severe challenges to the detection of hidden defects in PCBs (such as micro-hole cracks, dielectric peeling, and conductor short circuits).

[0003] Currently, commonly used PCB defect detection methods mainly include Automated Optical Inspection (AOI), Automated X-ray Inspection (AXI), and In-Circuit Test (ICT). However, when dealing with hidden defects in PCBs, there are often blind spots in the detection, making it difficult to accurately reflect changes in electrical performance.

[0004] Specifically, AOI identifies surface solder joint defects or component misalignment through image comparison, but it is powerless against hidden defects such as internal interlayer short circuits and microcracks; AXI can see through multilayer structures, but its equipment is expensive and it is difficult to distinguish signal integrity defects caused by minute impedance mismatches; ICT verifies circuit connectivity and component parameters by contacting test points with probes, but it relies on pre-designed test points, cannot cover high-density interconnect areas (such as the bottom of BGA packages), and the pressure of the probe contact may damage precision circuits.

[0005] In recent years, some studies have attempted to indirectly detect defects by analyzing the impedance characteristics of circuit boards. For example, a single-frequency signal is injected into the circuit board and the reflection coefficient is measured; impedance mismatch is then used to determine whether an open circuit or short circuit exists. However, the impedance response at a single frequency is only sensitive to specific types of defects (e.g., low frequencies are sensitive to macroscopic defects, while high frequencies are sensitive to microscopic defects), making it difficult to meet the detection needs of multiple types of defects simultaneously. Summary of the Invention

[0006] This application provides a method, system, storage medium, computer program product, and electronic device for detecting circuit board defects based on multi-band impedance matching, in order to at least solve the problem of insufficient ability to identify hidden defects when detecting high-density interconnected and multi-layered circuit boards in the current related technologies.

[0007] In a first aspect, embodiments of this application provide a circuit board defect detection method based on multi-band impedance matching, comprising: determining the corresponding test bias voltage of a reconfigurable impedance matching network at multiple test frequencies according to a frequency bias voltage relationship table; the reconfigurable impedance matching network includes multiple adjustable elements coupled to a test probe, and the frequency bias voltage relationship table includes the relationship between multiple pre-calibrated frequency points and bias voltages for a defect-free circuit board; for each test frequency point, applying a test bias voltage matching the test frequency point to each adjustable element to achieve impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency point, and injecting radio frequency signals into the circuit board under test to acquire the corresponding reflection coefficients through the test probes; analyzing the reflection coefficients corresponding to each test frequency point based on a multi-frequency sparse dictionary and compressed sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board; calculating the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and obtaining the hierarchical anomaly score of the corresponding circuit physical layer in combination with the spatial information of each circuit physical layer to screen at least one abnormal circuit physical layer.

[0008] Secondly, embodiments of this application provide a circuit board defect detection system based on multi-band impedance matching, comprising: a reconfigurable bias determination unit, configured to determine the corresponding test bias voltage of a reconfigurable impedance matching network at multiple test frequencies according to a frequency band bias voltage relationship table; the reconfigurable impedance matching network includes multiple adjustable elements coupled to test probes, and the frequency band bias voltage relationship table includes the relationship between multiple pre-calibrated frequency points and bias voltages for a defect-free circuit board; and a bias impedance matching unit, configured to apply a test bias voltage matching the test frequency to each of the adjustable elements for each of the test frequencies. The system achieves impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency points, and injects radio frequency signals into the circuit board under test to collect the corresponding reflection coefficients through the test probes; a three-dimensional scattering reconstruction unit is used to analyze the reflection coefficients corresponding to each of the test frequency points based on a multi-frequency sparse dictionary and compressed sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board; an anomaly layer identification unit is used to calculate the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and combine the spatial information of each circuit physical layer to obtain the hierarchical anomaly score of the corresponding circuit physical layer to screen at least one abnormal circuit physical layer.

[0009] Thirdly, an electronic device is provided, comprising: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the steps of the circuit board defect detection method based on multi-band impedance matching according to any embodiment of the present application.

[0010] Fourthly, embodiments of this application provide a storage medium storing a computer program thereon, characterized in that, when the program is executed by a processor, it implements the steps of the circuit board defect detection method based on multi-band impedance matching according to any embodiment of this application.

[0011] Fifthly, embodiments of this application provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the circuit board defect detection method based on multi-band impedance matching according to any embodiment of this application.

[0012] The circuit board defect detection method and system based on multi-band impedance matching provided in this application can achieve at least the following technical effects:

[0013] (1) By applying matching bias voltages at three or more test frequencies (low, medium, and high), the system can utilize the high sensitivity of low-frequency signals to macroscopic defects such as large open circuits and dielectric layer peeling, and the high-frequency signals to sensitively capture microscopic discontinuities such as microcracks in through-holes and short circuits between different layers, significantly enhancing compatibility compared to single-frequency detection. Furthermore, by combining a multi-frequency sparse dictionary with a compressed sensing algorithm, high-fidelity reconstruction of signal characteristics for multiple types of defects is achieved without increasing the number of test points, effectively avoiding detection blind spots caused by frequency bias.

[0014] (2) By setting up a reconfigurable impedance matching network, which can dynamically adjust the reactive components according to the pre-calibrated "frequency-bias voltage" relationship, the PCB under test can be in the optimal impedance matching state at each frequency. This significantly improves the RF signal injection efficiency and the signal-to-noise ratio of reflection coefficient measurement, enabling stable and distinguishable reflection signals to be obtained even in high-density interconnects or the bottom region of BGA, and greatly suppressing measurement errors caused by mismatch.

[0015] (3) Based on the set of reflection coefficients at each frequency point and the multi-frequency sparse reconstruction algorithm, the three-dimensional scattering distribution image inside the PCB is directly reconstructed, which helps to quantitatively identify the specific geometric shape of defects and breaks the limitation of traditional two-dimensional projection detection for deep defects. In addition, by calculating the negative log-likelihood distribution of the three-dimensional scattering image and combining it with the spatial information of each physical layer, anomaly scores can be output for each layer (copper foil, dielectric layer, blind and buried via layers, etc.), enabling spatial identification of the layer where the defect is located, realizing high-precision diagnosis of the detection system and targeted maintenance suggestions for the PCB production line.

[0016] This technical solution utilizes signal feature reconstruction to replace high-precision physical imaging, effectively reducing reliance on high-end imaging equipment. Simultaneously, the testing process is non-contact, avoiding mechanical damage to the circuit structure and possessing excellent automation capabilities, making it suitable for online inspection on circuit board production lines. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating an example of a circuit board defect detection method based on multi-band impedance matching according to an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of the structural connection of an example reconfigurable impedance matching network according to an embodiment of this application is shown;

[0020] Figure 3 A flowchart illustrating an example of generating a frequency band bias voltage relationship table according to an embodiment of this application is shown.

[0021] Figure 4 A flowchart illustrating an example of a circuit board defect detection method based on multi-band impedance matching according to an embodiment of this application is shown.

[0022] Figure 5 A schematic diagram illustrating the effect of an example of a circuit board defect type according to an embodiment of this application is shown.

[0023] Figure 6 A structural block diagram of an example of a circuit board defect detection system based on multi-band impedance matching according to an embodiment of this application is shown;

[0024] Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that the conductive path and dielectric material of a PCB determine its impedance characteristics at different frequencies. Any defects in the manufacturing process (such as poor soldering, cracks, open circuits, short circuits, uneven dielectric layer thickness, etc.) may cause local impedance changes. Therefore, by accurately measuring the impedance of a circuit board through impedance detection technology, it is possible to effectively determine whether there are structural or electrical abnormalities.

[0027] Currently, common impedance testing techniques are TDR (Time Domain Reflectometry) and TFDR (Transform-domain / Frequency-domain Reflectometry), which are widely used to detect faults and defects in high-frequency transmission lines, including PCBs.

[0028] However, TDR / TFDR is a single-frequency detection technology. The detection system typically injects electromagnetic pulses into the PCB within a fixed 1GHz to 5GHz frequency band and determines anomalies in transmission lines and vias by measuring the pulse reflection waveform. However, this single-frequency pulse signal faces a "resolution-penetration" conflict in practical applications: while high-frequency pulses have shorter rise times, enabling high-resolution imaging of sub-millimeter and even micrometer-level cracks, the high-frequency signal attenuates severely in multilayer HDI boards, leading to reduced reflected echo amplitude and a decreased signal-to-noise ratio. Conversely, while low-frequency pulses have less attenuation and deeper penetration, covering hidden defects such as inner-layer peeling and voids, their resolution is insufficient to detect micro-via cracks and fine dielectric delamination. Furthermore, the impedance matching network of TDR / TFDR detection systems often uses fixed LC device combinations or manually pluggable matching modules, making online dynamic optimization impossible for different board types and test frequency bands.

[0029] It should be understood that the above description of the relevant technologies is intended only to help the public better understand the inventive spirit and motivation of this application, and is not intended to limit this application. Furthermore, the technical solutions described in the above-mentioned relevant technologies are not prior art, and may also be undisclosed technical solutions, such as those under research or in the laboratory stage.

[0030] The technical solutions in this application, including the collection, storage, use, processing, transmission, provision, and disclosure of users' personal information, comply with relevant laws and regulations and do not violate public order and good morals.

[0031] Figure 1 A flowchart illustrating an example of a circuit board defect detection method based on multi-band impedance matching according to an embodiment of this application is shown.

[0032] Regarding the execution subject of the method in this application embodiment, it can be any controller or processor with computing or processing capabilities. Specifically, it can be implemented by a PCB online quality inspection system platform. Through the organic integration of multi-frequency impedance matching, sparse reconstruction, and hierarchical quantitative analysis, it not only fills the blind spots of AOI / AXI / ICT methods in the detection of hidden defects, but also provides a high-precision, low-cost PCB online quality inspection solution for high-density interconnects and multilayer blind and buried via boards.

[0033] In some examples, it can be integrated into an electronic device or terminal through software, hardware, or a combination of both, and the type of terminal or electronic device can be diverse, such as mobile phones, tablets, or desktop computers, etc.

[0034] like Figure 1 As shown, in step S110, the corresponding test bias voltage of the reconfigurable impedance matching network at multiple test frequency points is determined according to the frequency band bias voltage relationship table.

[0035] Here, the reconfigurable impedance matching network includes multiple adjustable elements coupled to the test probes, and the frequency band bias voltage relationship table contains the relationship between multiple pre-calibrated frequency points and bias voltages for a defect-free circuit board. In some implementations, the frequency band bias voltage relationship table can be completed during the system pre-calibration phase, the purpose of which is to record the required bias voltages for impedance matching at different RF test frequencies under defect-free conditions of the circuit board under test. The method for obtaining the frequency band bias voltage relationship table can be varied, such as being provided by a third-party manufacturer, or it can be pre-calibrated based on a defect-free circuit board sample under test; this is not limited here.

[0036] For example, during the system pre-calibration stage, at multiple preset radio frequency points, the control voltage at the minimum value of the optimal reflection coefficient is collected by adjusting the bias voltage of adjustable components (such as voltage-controlled capacitors, varactor diodes, micromechanical switches, etc.), and then the optimal matching bias voltage obtained at each frequency point is stored in a relationship table to form a frequency band bias voltage relationship table.

[0037] Therefore, by pre-calibrating and establishing a high-precision bias voltage-frequency mapping relationship, fast and accurate impedance matching settings can be achieved. At the same time, the adjustable components can be linked with the test frequency to improve the system's adaptability in multi-frequency detection.

[0038] In step S120, for each test frequency, a test bias voltage matching the test frequency is applied to each adjustable element to achieve impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency, and an RF signal is injected into the circuit board under test to collect the corresponding reflection coefficient through the test probe.

[0039] Here, based on the bias voltage value obtained from the impedance matching, the system applies voltages to multiple adjustable components to achieve conjugate matching between the equivalent input impedance of the entire impedance matching network and the port impedance of the circuit board under test (PCB) at that frequency. This ensures that test energy can be injected into the PCB to the maximum extent. After impedance matching is completed, the system injects an RF signal at the corresponding test frequency into the PCB. Simultaneously, the system acquires the signal reflected from inside the PCB through a vector network analysis module or a reflection coefficient detection module, storing it as a complex reflection coefficient. The amplitude and phase of the reflection coefficient contain the electromagnetic response characteristics of the PCB at that frequency.

[0040] In some implementations, the MCU can index the current frequency point f from the EEPROM. i The corresponding optimal bias vector And through a multi-channel DAC The signal is converted into an analog voltage signal and output to the bias amplifier module to amplify the DAC output to the operating range of the adjustable element (PIN diode or variable capacitor). Finally, the bias of each amplified channel is applied to the corresponding element of the matching network through a low-leakage multiplexing array.

[0041] In addition, the system includes a Vector Network Analyzer (VNA), which is equipped with an RF signal generator and a vector receiver to handle the signal transmission in f. i A continuous wave is output. The MCU controls the high-speed switching of the RF path from the VNA to the test probe via SPI. The test probe integrates a directional coupler at its probe end, one path injecting the signal into the PCB and the other coupling the reflected signal to a vector receiver. The vector receiver measures the reflection coefficient and outputs a complex value Γ(f). i )=|Γ|e j∠Γ Therefore, high energy injection and low reflection are ensured through precise impedance matching at multiple frequency points, which improves the system's response sensitivity to different structural defects, and provides rich characteristic information through multi-point frequency domain response recording.

[0042] Figure 2A schematic diagram of the structural connection of an example reconfigurable impedance matching network according to an embodiment of this application is shown.

[0043] A reconfigurable impedance matching network comprises multiple tunable elements coupled to test probes. In some examples, the tunable elements are arrays of PIN diodes, each of which is either RF-on or RF-off by applying a forward or reverse bias current. The PIN diode array is integrated in series or parallel within the main signal path or bypass branch of the reconfigurable impedance matching network. By controlling the conduction combination of different PIN diodes in the array through a test bias voltage, the equivalent inductance and / or equivalent capacitance of the corresponding branch is changed, thereby achieving impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency.

[0044] like Figure 2 As shown, the reconfigurable impedance matching network includes a series PIN diode array consisting of D1, D2 and D3, and a parallel PIN diode array consisting of D4 and D5.

[0045] In this embodiment, the test probe is connected to the input of an RF channel, which includes multiple PIN diodes (e.g., D1, D2, D3) connected in series to form the main signal transmission path. Each PIN diode can control its conduction state in the RF signal band according to the applied bias voltage. For example, when a forward bias current is applied, the PIN diode enters a low-impedance conduction state, while when a reverse bias is applied or there is no bias, the diode presents a high-impedance cutoff state.

[0046] Furthermore, multiple parallel branches of PIN diodes (e.g., D4 and D5), grounded and used as a bypass tuning network, are employed to adjust the local impedance characteristics near the node, thereby creating controllable resonance or impedance compensation behavior. Thus, through the combination of series and parallel diodes, the series branches primarily control the high-pass characteristics of the network, while the parallel branches primarily control the low-pass characteristics. Together, they achieve broadband flattened impedance matching, ensuring the matching network maintains low reflections throughout the entire test frequency band. This creates an RF path with "dynamically programmable impedance characteristics," allowing selective conduction of some PIN diodes to adjust the equivalent impedance parameters (including inductance and capacitance characteristics) of the signal path according to the test requirements at different frequencies.

[0047] In step S130, the reflection coefficients corresponding to each test frequency point are analyzed based on a multi-frequency sparse dictionary and compressed sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board.

[0048] Here, based on multi-frequency reflection coefficient data, the internal structure of the circuit board is modeled and visualized and reconstructed by using sparse signal processing and inversion imaging techniques.

[0049] In some implementations, the multi-frequency reflection coefficients are first mapped to the scattering model of the spatial structure, constructing an inverse problem relating frequency domain observations to the spatial scattering distribution. Then, using a pre-trained or pre-built multi-frequency sparse dictionary, the scattering distribution is represented as a superposition of a set of sparse basis functions, thus transforming the high-dimensional reconstruction problem into solving for sparse coefficients. Based on compressed sensing theory, the corresponding sparse scattering coefficients are recovered by minimizing observation errors and sparse regularization terms. Finally, the obtained sparse coefficients are mapped back to the three-dimensional spatial domain to obtain the electromagnetic scattering intensity distribution map of the circuit board at various physical levels, forming a three-dimensional visual image of the internal structure. Thus, the scattering image not only reflects the structural geometry but also implicitly contains field distribution anomalies caused by electromagnetic parameters (such as changes in dielectric constant and conductor gaps), significantly enhancing the ability to perceive non-structural defects.

[0050] In step S140, the negative log-likelihood distribution corresponding to the three-dimensional scattering image is calculated, and the hierarchical anomaly score of the corresponding circuit physical layer is obtained by combining the spatial information of each circuit physical layer, so as to screen at least one abnormal circuit physical layer.

[0051] In some implementations, the 3D scattering image is spatially layered into several partitions corresponding to the physical structure of the circuit board (such as signal layers, ground layers, power layers, dielectric layers, etc.). A probabilistic model is performed on the scattering intensity distribution within each layer, calculating its negative log-likelihood distribution relative to defect-free samples to measure the degree of deviation between the region and normal samples. Based on the probability deviation of each layer, its corresponding layer anomaly score is calculated, reflecting the probability of defects in that layer. The anomaly scores are thresholded or sorted to select one or more physical layers with the most anomalous characteristics. Finally, the suspected defective physical layer regions and their locations in 3D space are output for manual re-inspection or repair suggestions for automated PCB production lines.

[0052] Therefore, by using probabilistic statistical methods to assess the degree of scattering anomalies in different physical layers, spatial localization and layer-specific identification of defects can be achieved, effectively distinguishing defect responses in different physical structures and reducing the risk of misjudgment where surface layers conceal deep defects.

[0053] Figure 3 A flowchart illustrating an example of generating a frequency band bias voltage relationship table according to an embodiment of this application is shown.

[0054] like Figure 3 As shown, in step S310, a preset frequency point set and an initial bias voltage vector are obtained.

[0055] It should be noted that in the multi-band impedance matching detection framework, it is necessary to cover the key frequency bands that the PCB may affect the signal, and a series of typical communication or test frequencies (such as 0.7GHz, 2GHz, 5GHz, 9GHz, etc.) can be selected to form a set of preset frequency points. Each frequency point corresponds to a scenario in which electromagnetic waves interact most sensitively with the PCB dielectric and copper foil structure.

[0056] Furthermore, in order to achieve good impedance matching at these frequencies, the bias voltages of adjustable components (such as PIN diodes or variable capacitor arrays) must be systematically explored to construct an initial bias grid that covers the entire bias range.

[0057]

[0058]

[0059]

[0060] In the formula, f represents the preset frequency set. M This represents the Mth preset frequency point, where M represents the total number of preset frequency points. V represents the initial bias voltage vector at the i-th preset frequency point; N represents the number of adjustable elements in the reconfigurable impedance matching network, corresponding to the dimension of the bias voltage vector; min and V max These represent the lower and upper limits of the bias voltage for each adjustable element, respectively, with Δv representing the voltage step size; L bias This indicates the voltage range [V] min V max The total number of equal segments is used to construct a discrete candidate voltage value set.

[0061] It should be noted that the preset frequency set can cover multiple sampling frequencies with both low-frequency penetration and high-frequency resolution characteristics, and M=4 or more values ​​can be set to expand to more frequencies. Furthermore, [V min V max Depending on the specific device specifications, for example, the forward bias of a PIN diode can be selected from 0-20V, and the grid length L... bias A value of 5-10 can be set to balance search granularity and measurement cost. Here, a feasible initial bias is ensured at each key frequency point by using an initial bias voltage vector with comprehensive coverage.

[0062] In step S320, for each preset frequency point, a two-stage combined optimization is performed based on a defect-free circuit board to obtain the corresponding optimal bias voltage.

[0063] More specifically, the cost function is defined as:

[0064] J i (b)=w1|Γ(f i b)| 2 +w2(VSWR(f i b)-1) 2 Equation (4)

[0065]

[0066] In the formula, J i (b) indicates that at the i-th preset frequency point f i Below, the comprehensive cost function is calculated for the bias voltage vector b; w1 and w2 represent the weighting coefficients of the reflection coefficient amplitude term and the standing wave ratio deviation term, respectively, Γ(f i b) indicates at frequency point f i When a bias voltage vector b is applied, the complex reflection coefficient measured at the test probe, |Γ| represents the amplitude of the reflection coefficient, VSWR(f i b) indicates at frequency point f i The voltage standing wave ratio measured at the test probe when a bias voltage vector b is applied.

[0067] Here, a comprehensive cost function is designed to consider both the objectives of "minimizing reflection amplitude" and "flattening input impedance." On the one hand, a smaller amplitude means that the matching network can couple more RF energy into the PCB, improving the final signal strength. On the other hand, a standing wave ratio (SWR) as close to 1 as possible means smooth input impedance and minimal mismatch within a certain bandwidth, which is crucial for the stability of subsequent multi-band measurements. By weighting both objectives with w1 and w2, the matching optimization is transformed into a single-objective numerical minimization problem. It should be understood that w1 and w2 can be preset, for example, set after comparing the effects of simply minimizing reflection and the flattest SWR on detection sensitivity and imaging quality in offline experiments, and can also be treated equally (each accounting for 50%), or appropriately adjusted according to the PCB material and test objectives.

[0068] In the first stage, the cost function is fitted according to the Gaussian process surrogate model, the training set is initialized using the initial bias voltage vector, the bias voltage is sampled and iterated using the EI (Expected Improvement) function, and the approximate optimal bias matrix is ​​solved by Bayesian optimization.

[0069] For example, an EI function is expressed as follows:

[0070]

[0071] In the formula, EI(b) is the acquisition function used in Bayesian optimization to select the next bias voltage vector, and is used to measure the expected cost improvement on candidate b; J is the expectation operator, representing the expectation of the improved value under the Gaussian process surrogate model; i,min This represents the minimum cost value observed in the current training set.

[0072] For the t-th iteration, perform the following operation:

[0073] Maximize the EI function value from the current Gaussian process surrogate model to select the bias voltage vector b. (t) ,

[0074] Inject frequency f using a vector network analyzer i And in the bias voltage vector b (t) The complex reflection coefficient and voltage standing wave ratio are measured to iteratively calculate the corresponding J. i (b (t) ),

[0075] (b) (t) J i (b (t) Add to the training set to update the Gaussian process proxy model;

[0076] By repeating the iteration T1 times, an approximate optimal bias voltage vector is obtained.

[0077] Here, in the first stage of the global search, Bayesian optimization (BO) is used to efficiently explore the bias space. A Gaussian process surrogate model is established for the cost function. While ensuring a limited number of measurements, the expected improvement (EI) function balances exploration and utilization, quickly finding the low-value region of the cost function. Therefore, compared to a full grid scan, the BO algorithm can typically lock the candidate optimal region within 15 iterations (i.e., T1 can be 15), greatly improving efficiency. Furthermore, the surrogate model can utilize historical information in subsequent iterations to form a comprehensive understanding of the bias space, reducing redundant measurements.

[0078] In the second stage, the central difference method is used to solve for the approximate gradient of each bias component in the approximate optimal bias voltage vector.

[0079] It should be noted that the candidate biases obtained through the first-stage BO iteration are often close to the global optimum, but still require local fine-tuning to obtain more accurate extrema. Here, in the second stage, numerical accuracy can be improved with fewer additional measurements by estimating the central difference numerical gradient and combining it with gradient descent iteration.

[0080]

[0081] In the formula, The cost function is expressed as follows: The j-th bias component b j The partial derivative of γ, where γ represents the small voltage perturbation used for numerical differentiation; e j Let be the j-th unit vector in N-dimensional space, representing the bias component b only. j Add perturbation;

[0082] The approximate optimal bias voltage vector is iteratively updated based on the gradient descent step size:

[0083]

[0084] In the formula, b (t) Let η represent the bias voltage vector in the t-th gradient iteration, and let η represent the gradient descent step size. Represents the gradient vector Used to guide the direction of updates;

[0085] If two consecutive iterations satisfy |J i (b (t+1) )-J i (b (t) If | < δ, then let Where δ represents the convergence threshold. This represents the optimal bias voltage vector at the i-th frequency point.

[0086] Here, in the second stage, by using a central differential method to increase or decrease the bias voltage of each component, the partial derivative is approximated by measuring the difference in the cost function. Local fine-tuning further minimizes the error of the cost function value, reducing it to 10%. -4 This improves matching quality. Furthermore, a gradient strategy avoids the blindness of global search, reducing the impact of jitter and measurement noise.

[0087] Each optimal bias voltage vector is sequentially loaded into the matching network, and the voltage standing wave ratio (VSWR) is measured at the corresponding frequency. If there is a frequency in the measured VSWR that exceeds the preset VSWR threshold, it is confirmed that the frequency does not meet the flatness requirement and the process is reverted to the second stage of the frequency for local fine-tuning.

[0088] If the measured voltage standing wave ratio (VSWR) at each frequency point does not exceed the preset VSWR threshold, then the corresponding optimal bias voltage at each frequency point will be output.

[0089] It should be noted that the optimal offset at a single frequency does not necessarily guarantee smooth matching across frequency bands. Therefore, it is necessary to verify the matching status of all frequency points as a whole. By loading the optimal offset at each frequency point and measuring the standing wave ratio (VSWR), combined with fine-spectrum scanning of adjacent frequency bands, it can be ensured that the matching performance across the entire bandwidth meets the preset specifications.

[0090] For example, the VSWR threshold is set to 1.6, and anything exceeding this is considered uneven. Fine measurements are performed at intervals of 0.02 GHz at ±0.1 GHz of the frequency band boundary, and potential spikes are captured by fine-spectrum scanning. If a problem is found, fine-tuning is only required for that frequency point or local interval. Only a local backtracking is needed to avoid a complete rerun, thereby ensuring the reliability of the entire frequency band and preventing information loss or artifacts during multi-band reflection measurements.

[0091] In step S330, a frequency band bias voltage relationship table is generated based on each preset frequency point and the corresponding optimal bias voltage.

[0092] Here, after completing the optimal bias calibration and verification for all frequency points, these results are stored in a structured table to form a frequency band bias voltage relationship table. This table can be stored in the MCU's EEPROM using, for example, JSON, binary indexes, or a simple array. During online testing, the matching network can be configured immediately by quickly indexing the bias vector of the corresponding frequency point. For example, the MCU reads the bias of the corresponding frequency point, drives the DAC and amplifier circuits, and verifies the calibration. This eliminates the need for recalibration, significantly reducing test preparation time.

[0093] In production line applications, the same PCB model only needs to be calibrated offline once using a corresponding health board, and then it can be used for online testing of hundreds or thousands of boards. In addition, loading the bias and driving the matching network only takes a few hundred microseconds to a few milliseconds, meeting the production line cycle time requirements.

[0094] Regarding the details of reconstructing the three-dimensional scattering image in step S130, in some examples of embodiments of this application, during multi-frequency grid scanning, the complex reflection coefficients measured by the probe at each frequency point and each spatial location are samples of the scattering field inside the PCB. To organize these discrete samples into a mathematically processable form, each frequency point L is arranged in a "frequency priority, location secondary" order. samp The reflectance values ​​at each spatial location are arranged into a matrix of length M·L. samp The vector y.

[0095] Specifically, the test probe will be placed at each frequency point f i And at the kth spatial sampling point (x k ,y k The complex reflection coefficient Γ(x) measured at point ) k ,y k ,f i According to the measurement sequence number m=(i-1)L samp +k permutations generate the measurement vector y; where L samp This represents the total number of spatial sampling points at a single test frequency.

[0096] Here, the probe moves along a pre-planned grid path on the PCB surface, reaching each grid point (x). k ,y k The system automatically switches to the current frequency, records and caches the complex reflection coefficient once. Through a strict one-to-one mapping, it ensures that the m-th (i-1)L... of the vector y... samp +k precise corresponding frequency points f i With position (x) k ,y k The reflection coefficient is stored in complex form (amplitude and phase each occupy floating-point numbers), and double-precision floating-point numbers can be used to meet the numerical stability requirements of high-frequency phase expansion. Simultaneously, the MCU synchronously controls bias switching, probe positioning, and VNA measurement to ensure accurate recording of the temporal sequence of all elements within y.

[0097] Then, the interior of the circuit board is discretized into U voxels, and the center coordinates of the qth voxel are set to r. q The test probe position is Construct the measurement matrix Φ.

[0098] It should be noted that the measurement matrix Φ describes the physical mapping relationship between the "internal scattering field → external measurement"—it serves as a bridge between the three-dimensional voxel space and the measurement vector space. Under near-field metasurface probe coupling, each voxel contributes a certain amount of scattering to each measurement; this contribution can be viewed as the product of the voxel scattering intensity and a coupling coefficient. By arranging the coupling coefficients of all voxels and all measurement points into matrix Φ, the entire measurement process can be accurately expressed using a linear algebraic model.

[0099] Specifically, the elements in the measurement matrix are expressed by the following formula:

[0100]

[0101] In the formula, Φ m,q Let be the element in the m-th row and q-th column of the measurement matrix Φ, representing the linear coupling coefficient of the q-th voxel to the m-th measurement; The qth voxel at frequency f i Below, from the voxel center r q to probe position The electromagnetic Green's function; E inc (f i ,r q ) indicates that the test probe is at frequency point f i voxel r q The intensity of the incident field of the excitation, ΔV represents the volume of each voxel.

[0102] Regarding the explanation of equation (9), based on the dielectric properties and multilayer structure of the PCB, the Green's function can be pre-calculated using analytical theory or numerical methods for layered media and stored as a lookup table. This function includes the amplitude and phase changes caused by refraction, reflection, and absorption of electromagnetic waves at different media interfaces. Furthermore, the incident field E... inc Considering the probe's radiation mode and near-field effects, and using a near-field antenna model or pre-calibrated electric field distribution data to describe it, we can ensure that the product of the Green's function and the incident field accurately represents the first voxel excitation. The voxel volume ΔV can be set according to the spatial resolution or the 3D mesh size to maintain the physical consistency of the scattering integral.

[0103] By using Green's function and the incident field model, we ensure that the coupling relationship between Φ and the real PCB environment is highly consistent, avoiding the reconstruction deviation caused by the "black box" approximation. Furthermore, a high-quality Φ enables subsequent optimization to correctly distinguish the subtle differences between voxels, thereby improving the resolution and positioning accuracy of 3D imaging.

[0104] Furthermore, let x = Dα, where D is a multi-frequency sparse dictionary obtained by training the multi-frequency scattering samples collected offline on the healthy board and the defective board using the K-SVD algorithm. Each column is a dictionary atom, which sparsely represents the scattering characteristics of various defect voxels. α is the sparse representation coefficient of the three-dimensional scattering field under the dictionary D, with only a few elements being non-zero, corresponding to the sparse distribution of defect voxels.

[0105] It should be noted that the internal defect distribution of PCBs is often highly sparse, with most voxels representing homogeneous dielectric regions and only a few pointing to cracks, bubbles, or delamination interfaces. By learning a set of "atoms" from a large number of samples—these atoms represent the spatial and spectral patterns of typical defect scattering—arbitrarily complex sets of defect voxels can be reconstructed using a very small number of sparse coefficients. Through the compressed sensing recovery method described above, the defect field can be stably reconstructed even when the number of measurement points is much smaller than the number of voxels. Thus, with the help of a multi-frequency sparse dictionary, the sparse parameters have only a few dozen dimensions, while the original number of voxels may be tens of thousands, significantly reducing the dimensionality of the optimization problem. Furthermore, the multi-frequency sparse dictionary contains various defect patterns, enabling automatic adaptation to unknown morphologies of cracks, bubbles, or delamination.

[0106] Regarding the construction details of the multi-frequency sparse dictionary, in some examples of embodiments of this application, it is first necessary to collect both healthy board samples and defective board samples simultaneously. Specifically, healthy board samples can be normal scattering characteristics collected from healthy PCBs, while defective board samples can be scattering characteristics collected from defective circuit boards with various typical defects (such as micro-via cracks, interlayer delamination, dielectric voids, etc.).

[0107] Specifically, on each sample board, an optimized matching network and probe grid path are used to perform a fine-grid scan of the preset frequency point set one by one. The horizontal and vertical step sizes are set according to the PCB detail requirements (e.g., 0.5mm or finer), and at each grid point (x k ,y k The reflection coefficient Γ(x) is collected at point ) k ,y k ,f i For healthy boards, only "defect blank" confirmation is required; for defective boards, the location and morphology of internal defects in each board are three-dimensionally annotated using a miniature X-ray or OCM (optical confocal microscope) to obtain voxel-level true values ​​that correspond one-to-one with the scattering measurements.

[0108] Then, K-SVD dictionary training is performed using the aforementioned training samples, and the relevant details of K-SVD dictionary training in current related technologies can be referenced.

[0109] In some examples of embodiments of this application, cross-frequency joint training can be used. Specifically, principal component analysis (PCA) is used to extract the first K principal vectors K from the sample matrix, and this process is performed iteratively. Exemplarily, in each iterative iteration, for each training vector x... (s) Using the Orthogonal Matching Pursuit (OMP) algorithm in the current dictionary D (t) Next, solve for the sparse coefficients, and then for each dictionary atom d k (Column k) Extract all sample sets that use this atom in the sparse representation, calculate the residual matrix, and perform singular value decomposition (SVD). Concatenate all frequency point samples and train a large dictionary D at once to capture cross-frequency coupled atoms. Train dictionary D separately for each frequency point. i The dictionary is then merged into a joint dictionary using block diagonals or principal components. Training terminates when the change in the Frobenius norm before and after the dictionary update is below a threshold, or when the number of iterations reaches the upper limit (e.g., 100 times), and the final dictionary D is output.

[0110] Therefore, the sparse dictionary obtained through offline training can accurately reconstruct the multi-frequency scattering features of arbitrary defect voxels with a small number of atoms, significantly reducing the dimensionality and computational cost of online sparse solutions. Furthermore, through cross-frequency joint training, dictionary atoms can simultaneously encode low-frequency penetration and high-frequency resolution features, improving the ability to represent mixed defects (such as through-hole cracks accompanied by medium voids). Thus, the multi-frequency sparse dictionary constructed in this way can accurately reproduce the scattering features of various defect voxels and achieve efficient reconstruction with a small number of online measurements.

[0111] The optimal sparsity coefficient α is obtained by solving the compressed sensing optimization objective function. * To reconstruct a three-dimensional scattering image inside the circuit board.

[0112] Specifically, the objective function for compressed sensing optimization is expressed by the following equation:

[0113]

[0114] In the formula, represents the l2 least squares term; μ‖α‖1 represents the l1 sparse regularization term, and the weight μ>0 controls the degree of sparsity; Denotes the total variation regularity term. The gradient operator calculated for the 3D reconstructed voxel vector x, whose sum of magnitudes... λ is used to suppress noise and artifacts during reconstruction. TV To control the weights; λ represents the spectral smoothing regularization term, W is the spectral operator that smooths the reconstruction result in the frequency dimension, and λ is the frequency smoothing regularization term. FS >0 controls spectral consistency, ensuring the continuity of reconstructed voxels at different frequencies in the frequency domain.

[0115] Regarding the explanation of equation (10), μ is selected based on the measured SNR (μ is slightly increased for low SNR), λ TV It can be adjusted according to spatial resolution requirements, λ FS It can be fine-tuned according to the requirements of spectrum smoothness.

[0116] It should be noted that the core of compressed sensing lies in "a small number of measurements + sparse priors → accurate recovery," but a single L1 constraint cannot suppress spatial artifacts or guarantee multi-frequency consistency. Therefore, an L2 data fitting term is introduced into the objective function to ensure that the reconstructed values ​​are consistent with the actual measurements; an L1 sparsity term is introduced to enhance prior sparsity; a total variation regularization term is introduced to suppress spatial noise and enhance the continuity of the reconstructed volume; and a spectral smoothing regularization term is introduced to ensure that the same voxel behaves smoothly at different frequency points and avoids inconsistencies between frequency points.

[0117] Here, the optimization problem is broken down into four parts: data fitting, sparse thresholding, TV (Total Variation) subproblems, and spectral subproblems. These are solved alternately, with Lagrange multipliers updated iteratively until the error converges. Thus, by eliminating high-frequency noise through TV regularization, the defect voxel reconstruction error is more concentrated, leading to more accurate anomaly detection. Spectral smoothing regularization ensures that the reconstructed voxels form a consistent scattering intensity curve across the entire frequency band, facilitating subsequent multi-frequency fusion and model determination. Furthermore, data fitting and thresholding operations can be fully parallelized on the GPU, accelerating matrix multiplication and element-level processing to meet the timeliness requirements of online production line inspection.

[0118] Regarding the details of screening the physical layer of abnormal circuits in step S140, in some examples of embodiments of this application, the three-dimensional scattering image obtained through online reconstruction and arranged according to voxel indices q = 1, ..., U is used. Encoder network for input variational autoencoder:

[0119]

[0120] In the formula, Q φ (·) represents the encoder distribution, z represents the latent variable vector, and μ φ and Let these represent the mean vector and variance vector of the latent variables, respectively. The prior of the latent variables is assumed to be standard normal.

[0121] It should be noted that the original 3D scattering images have many dimensions and contain complex noise, hardware artifacts, and process differences, making it almost impossible to directly measure "anomalies" in high-dimensional space. The latent distribution learned by the encoder (parameterized as mean and variance vectors) condenses the main variation patterns of normal data, removes most of the noise and redundant features, and makes subsequent calculation of probability density and anomaly measurement feasible.

[0122] More specifically, in the unsupervised anomaly detection framework, a "normal data model" (i.e., unsupervised training using only healthy board data) is used to probabilistically evaluate the three-dimensional scattering field obtained from online reconstruction. Specifically, a VAE (variational autoencoder) is used to map the high-dimensional input to a low-dimensional latent spatial distribution through an encoder network, thereby realizing the expression of the probabilistic structure of the "normal scattering image".

[0123] Assuming the output likelihood of the decoder, i.e., the voxels are independent given the latent variables, then the following holds:

[0124]

[0125] In the formula, The conditional likelihood of the decoder is defined by the set of network parameters θ and is used to evaluate the reconstructed value given the latent variable z. The probability of.

[0126] The negative log-likelihood of each voxel q is defined as its reconstructed negative log-marginal likelihood:

[0127]

[0128] In the formula, NLL q Let represent the negative log-likelihood value of the q-th voxel. Indicates the encoder distribution The expected value is given by KL(·), which is the KL divergence between the encoder output distribution and the standard normal prior. Its value is evenly distributed among all voxels to ensure NLL aggregation consistency.

[0129] It should be noted that the negative ELBO (Evidence Lower Likelihood) value—that is, the negative log-likelihood (NLL)—intuitively measures the "unexpectedness" of a reconstructed image or a local area of ​​an image under a given "normal data model." To locate anomalies, the overall NLL is decomposed into each voxel by assuming conditional independence between voxels. Although this is an approximate assumption in this implementation, it is sufficiently precise in a multi-frequency scattering field because real defects are often limited to a few voxels, and the peak value of the NLL (Negative Log-Likelihood) under the independence assumption can still effectively highlight the anomalous region.

[0130] NLL of all voxels q Reorganization into A three-dimensional NLL volume diagram of equal size {NLL(q)|q=1…U}.

[0131] Based on the physical layer index ζ(q)∈{1,…,H} corresponding to each voxel q in the PCB design, the voxel set is divided into layer sets Ω. ζ ={q|ζ(q)=ζ},Ω ζ ζ represents the set of voxel indices for the ζ-th layer; ζ(q) is the physical layer mapping function, which assigns the voxel index q to the corresponding physical layer number; H represents the total number of physical layers on the circuit board.

[0132] Maximize the negative log-likelihood of all voxels in the ζ-th layer:

[0133]

[0134] In the formula, S ζ This represents the level anomaly score of the ζ-th level.

[0135] It should be noted that in PCB inspection, the most dangerous defects are often microcracks or blind via peeling that are extremely small in size but have a great impact. These point-like anomalies may only occupy one or two voxels. The in-layer mean will dilute this tiny peak value, while the maximum value aggregation ensures that any peak can trigger an alarm, thereby avoiding missed detection.

[0136] Here, by employing hierarchical maximum aggregation to capture peak NLL (Neural Limiting Law), rather than averaging or energy statistics, we can ensure that even minute anomalies in a small number of voxels can be located immediately, significantly improving the detection rate of microcracks and localized delamination. This enables the location of minute through-hole cracks (width < 50 μm) and minor interlaminar delaminations (area < 0.1 mm). 2 These are often overlooked in traditional single-frequency TDR or X-ray detection.

[0137] S ζ The layer anomaly threshold T obtained by offline statistical analysis of the ζ layer on the health board.ζ Compare, take

[0138] ζ * ={ζ|S ζ >T ζ} , Equation (15)

[0139] Output the set of layer indices ζ of the physical layer of the detected abnormal circuit. * .

[0140] Here, to distinguish between "occasional high values ​​of measurement noise" and "high values ​​caused by actual defects," we pre-performed extensive NLL statistics offline on the health board to obtain the maximum NLL distribution range for each layer under normal conditions, thereby setting a safety threshold. When online, if the peak value exceeds this threshold, the layer is considered abnormal. Therefore, by combining the health board statistical threshold to eliminate occasional noise spikes, and then using hierarchical alarms to cluster regions, we avoid false positives from single-point artifacts.

[0141] Through the embodiments of this application, the dual output of voxel-level NLL and hierarchical aggregation is integrated, which can accurately locate the position of a single abnormal voxel and quickly locate the corresponding circuit physical layer.

[0142] Figure 4 A flowchart illustrating an example of a circuit board defect detection method based on multi-band impedance matching according to an embodiment of this application is shown.

[0143] like Figure 4 As shown, in step S410, the corresponding test bias voltage of the reconfigurable impedance matching network at multiple test frequency points is determined according to the frequency band bias voltage relationship table.

[0144] In step S420, for each test frequency, a test bias voltage matching the test frequency is applied to each adjustable element to achieve impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency, and an RF signal is injected into the circuit board under test to collect the corresponding reflection coefficient through the test probe.

[0145] In step S430, the reflection coefficients corresponding to each test frequency point are analyzed based on a multi-frequency sparse dictionary and compressed sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board.

[0146] In step S440, the negative log-likelihood distribution corresponding to the three-dimensional scattering image is calculated, and the hierarchical anomaly score of the corresponding circuit physical layer is obtained by combining the spatial information of each circuit physical layer, so as to screen at least one abnormal circuit physical layer.

[0147] For details regarding the implementation of steps S410-S440, please refer to the description in the section on other embodiments above, which will not be repeated here.

[0148] In step S450, for each abnormal circuit physical layer, at least one abnormal voxel point with a negative log-likelihood value exceeding the layer abnormality threshold is extracted from the abnormal circuit physical layer according to a preset voxel sliding window, and the corresponding local abnormal voxel cluster is obtained by pixel clustering.

[0149] It should be noted that internal defects on circuit boards typically exhibit characteristics of "local clustering" or "connected blocks." For example, micro-hole cracks often cluster in a certain area, manifesting as a series of small, high-abnormality points; while delamination of blind / buried vias may present as a series of multiple high-abnormality points in the vertical structural direction. Therefore, relying solely on a single voxel point for defect assessment lacks spatial coherence and structural integrity.

[0150] Here, a preset three-dimensional sliding window is used to scan within the anomaly layer, identifying NLL values ​​exceeding the threshold T. ζ Abnormal voxel points are extracted first to avoid directly clustering all voxels in the entire layer. The abnormal voxels are divided into several local clusters by utilizing the spatial adjacency relationship between voxels, with each cluster corresponding to a possible defect region.

[0151] Specifically, a sliding window moves voxel by voxel within the physical layer of the abnormal circuit, extracting a local subset of voxels at each step, and counting whether there are regions where the negative log-likelihood value continuously exceeds a preset layer anomaly threshold. Once it is found that the negative log-likelihood value of at least one voxel is greater than the set threshold, it is considered that there is a potential abnormal response region in the sliding window.

[0152] Therefore, by introducing a sliding window local anomaly detection and voxel clustering mechanism, the spatial localization and separation of micro-structural defects inside the circuit board can be realized, supporting the hierarchical tracking and comparison of defect areas, which helps to achieve multi-layer defect penetration analysis.

[0153] In step S460, based on the local voxel clustering corresponding to each abnormal circuit physical layer, the circuit board defect type for the circuit board under test is output. The circuit board defect type includes at least one of the following: micro-hole crack, interlayer delamination, blind buried via peeling, or dielectric layer void.

[0154] In some implementations, rule-based pattern matching or trained classification models (such as SVM, decision trees, or lightweight neural networks) can be introduced to fuse multiple feature dimensions for multi-class classification. More specifically, the feature dimensions of the model can be diverse and can be determined based on structural hierarchical position and voxel clustering morphology.

[0155] For example, in terms of structural layer location, different types of defects tend to concentrate in specific circuit structure layers. Specifically, micro-hole cracks tend to appear near metal vias that penetrate multiple layers, generally spanning signal and ground layers. Interlayer delamination and dielectric voids mostly occur within dielectric layers, typically containing no metal conductors, exhibiting weak reflected signal response but strong structural continuity. Blind via peeling is concentrated at the interface between wiring layers and blind vias, presenting a sheet-like distribution along the Z-axis, and is often confined to the space between two layers.

[0156] On the other hand, voxel clustering morphology can reflect the unique spatial morphology of different defects. For example, crack defects often appear as linear or small dot-like bands with high connectivity; peeling defects are sheet-like, large in volume but thin in thickness; void defects are blocky or irregular in shape, dense in the middle and with blurred boundaries. Thus, morphological clustering morphology can be used to specifically classify circuit board defects.

[0157] Through the embodiments of this application, by using sliding window + clustering, potential abnormal voxels can be spontaneously "clustered" in three-dimensional space, which greatly improves the defect positioning accuracy, makes the crack clusters and void clusters clearly separated, and can automatically switch the judgment logic for the corresponding defects according to the geometry of the clusters.

[0158] Figure 5 A schematic diagram illustrating the effect of an example of a circuit board defect type according to an embodiment of this application is shown.

[0159] like Figure 5 As shown, micro-via cracks refer to intersecting crack lines visible at the edges of multilayer vias. Specifically, micro-vias are blind or buried vias in high-density interconnect (HDI) boards, typically with diameters between 50μm and 150μm, penetrating only a few layers. Due to their extremely thin copper walls and concentrated thermal and mechanical stress during reflow soldering or thermal cycling tests, they are prone to developing micro-cracks along the copper foil-resin interface. These cracks are often less than 50μm wide, between 100μm and 1mm long, and irregularly distributed, affecting the continuity of the electrical conductivity path within the via and causing local impedance abrupt changes or signal reflections during high-frequency signal transmission. Traditional optical and X-ray inspections struggle to detect these cracks online. In this embodiment of the invention, high-sensitivity localization of sub-50μm cracks can be achieved through high-frequency (≥5GHz) near-field scattering imaging and depth anomaly detection.

[0160] Interlayer delamination refers to the appearance of noticeable peeling gaps between intermediate layers. Specifically, in the lamination process, multilayer PCBs are composed of multiple layers of copper foil and prepreg or epoxy glass cloth. If the lamination temperature, pressure, curing profile, or material ratio is improper, or if the internal stress of the board is too high, the bonding interface between two layers will separate—that is, "internal layer delamination." This defect is not directly visible to the naked eye and is often accompanied by a sudden increase in dielectric constant and dielectric loss, affecting high-frequency signal transmission.

[0161] Blind via peeling refers to the appearance of sheet-like peeling areas at the top or bottom of a blind via (which only penetrates a portion of the layer). Blind vias or buried vias are through-hole structures that only penetrate a portion of the layer, and their surrounding copper walls must also have good adhesion to the substrate. During lamination or subsequent thermal cycling, due to mismatched coefficients of thermal expansion and stress concentration at high and low temperatures, tiny cracks appear at the interface between the copper wall and the adjacent resin layer, resulting in "blind via peeling." This defect creates an electrical open circuit or impedance abrupt change at the via wall, making it extremely difficult to detect at high speed using traditional AOI or X-ray lines.

[0162] Dielectric layer voids refer to circular or irregular voids visible within a single dielectric layer. These are common material defects in multilayer PCB manufacturing, resulting from incomplete wetting, insufficient curing, or failure to timely expel volatile gases during the lamination process. This leads to irregularly shaped cavities with a diameter >100μm within the resin layer of the substrate. These voids locally reduce the dielectric constant, increase dielectric loss, and easily cause phase distortion and signal attenuation in high-frequency signals. Because these voids are covered by copper layers and their locations are concealed, they are difficult to detect using AOI and flying probe testing. Through compressed sensing imaging combining low-frequency penetration (0.7-2GHz) and high-frequency resolution (5-9GHz) as described in this application embodiment, the distribution of internal voids can be captured at the three-dimensional voxel level, achieving high-precision positioning within 0.5mm.

[0163] In some examples of embodiments of this application, cluster morphological features corresponding to each local voxel cluster are extracted. These cluster morphological features include at least one of the following: voxel count, axial range, volume-to-surface area ratio, and shape factor. Then, each cluster morphological feature is matched according to a predefined defect type feature pattern library to output the circuit board defect type for the circuit board under test.

[0164] Here, a set of geometric morphological features is calculated for each cluster, including the number of voxels to highlight the size of the defect, the axial range to represent the extension of the cluster in the x, y, and z directions, the volume-to-surface area ratio to distinguish between spherical voids and sheet cracks, and a shape factor to characterize elongated or flattened distributions. Finally, the cluster feature vectors are matched with predefined feature patterns for various types of defects to obtain the final circuit board defect type identification.

[0165] For example, for micro-hole cracks, a large length / width ratio, small axial thickness, and cluster center close to the hole location are required; for interlayer delamination, a large width / thickness ratio and large-area cluster distribution along the layer are required; for blind / buried via peeling, clusters should be circular or semi-circular, with their location geometrically overlapping with the blind / buried via; for dielectric layer voids, a high volume-to-surface area ratio and a near-spherical distribution are required. Furthermore, hard thresholding rules or lightweight classification models (such as decision trees) can be used to determine the optimal matching type. Finally, all clusters and their matching results are summarized, outputting the most representative defect type or multiple parallel defects, labeling the corresponding abnormal layer and approximate spatial location. This allows engineers to clearly see the shape and location of defects, facilitating targeted maintenance of the PCB production line.

[0166] In some implementations, for each cluster Calculate the eigenvector f respectively n :

[0167] 1. Number of voxels N n :

[0168]

[0169] 2. Axial range:

[0170] Maximum - minimum difference along the x, y, z directions:

[0171]

[0172] Similarly, we can calculate △y and △z.

[0173] 3. Principal Component Analysis (PCA)

[0174] coordinate matrix of the cluster Calculate the covariance and obtain the eigenvalues ​​λ1≥λ2≥λ3, length width thickness

[0175] 4. Shape factor

[0176] Slenderness: L / W;

[0177] Flatness: W / T;

[0178] Sphericity:

[0179] 5. Volume-to-surface area ratio

[0180] Voxel volume: V n =N n ×△V;

[0181] Surface area approximation: estimated from the three-dimensional boundary voxels, or the convex hull surface area;

[0182] Ratio: V n / S n Distinguish between spherical and sheet-like shapes.

[0183] Based on the above feature f n The circuit board defect type is identified and located by matching it with a defect type feature pattern library.

[0184] Table 1. Defect Type Feature Pattern Library

[0185]

[0186]

[0187] In this embodiment of the application, by matching the cluster morphological features with the defect type feature pattern library according to rules, the type determination of a single cluster can be completed efficiently, and the detection of point defects (cracks, voids) and surface defects (interlayer peeling) can be supported at the same time. Moreover, the determination logic can be automatically switched according to the geometry of the cluster without manual intervention.

[0188] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of combined actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Secondly, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application. In the above embodiments, the descriptions of each embodiment have their own emphasis; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0189] Figure 6 A structural block diagram of an example of a circuit board defect detection system based on multi-band impedance matching according to an embodiment of this application is shown.

[0190] like Figure 6As shown, the circuit board defect detection system 600 based on multi-band impedance matching includes a reconstructed bias determination unit 610, a bias impedance matching unit 620, a three-dimensional scattering reconstruction unit 630, and an anomaly layer identification unit 640.

[0191] The reconfigurable bias determination unit 610 is used to determine the corresponding test bias voltage of the reconfigurable impedance matching network at multiple test frequency points according to the frequency band bias voltage relationship table; the reconfigurable impedance matching network includes multiple adjustable elements and is coupled to the test probe, and the frequency band bias voltage relationship table includes the relationship between multiple frequency points and bias voltages pre-calibrated for a defect-free circuit board.

[0192] The bias impedance matching unit 620 is used to apply a test bias voltage matching the test frequency to each of the adjustable elements to achieve impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency, and to inject radio frequency signals into the circuit board under test so as to acquire the corresponding reflection coefficient through the test probe.

[0193] The three-dimensional scattering reconstruction unit 630 is used to analyze the reflection coefficients corresponding to each of the test frequency points based on a multi-frequency sparse dictionary and compressed sensing algorithm, so as to reconstruct a three-dimensional scattering image inside the circuit board.

[0194] The anomaly layer identification unit 640 is used to calculate the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and to obtain the hierarchical anomaly score of the corresponding circuit physical layer in combination with the spatial information of each circuit physical layer, so as to screen at least one abnormal circuit physical layer.

[0195] In some embodiments, this application provides a non-volatile computer-readable storage medium storing one or more programs including execution instructions. The execution instructions can be read and executed by an electronic device (including but not limited to a computer, server, or network device) to perform the steps of any of the circuit board defect detection methods based on multi-band impedance matching described above.

[0196] In some embodiments, this application also provides a computer program product, the computer program product including a computer program stored on a non-volatile computer-readable storage medium, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the steps of any of the above-described circuit board defect detection methods based on multi-band impedance matching.

[0197] In some embodiments, this application also provides an electronic device, comprising: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform steps of a circuit board defect detection method based on multi-band impedance matching.

[0198] Figure 7 This is a schematic diagram of the hardware structure of an electronic device that performs a circuit board defect detection method based on multi-band impedance matching, according to another embodiment of this application. Figure 7 As shown, the device includes:

[0199] One or more processors 710 and memory 720, Figure 7 Take the 710 processor as an example.

[0200] The device for performing the circuit board defect detection method based on multi-band impedance matching may further include: an input device 730 and an output device 740.

[0201] The processor 710, memory 720, input device 730, and output device 740 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0202] The memory 720, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the circuit board defect detection method based on multi-band impedance matching in the embodiments of this application. The processor 710 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 720, thereby realizing the circuit board defect detection method based on multi-band impedance matching in the above-described method embodiments.

[0203] The memory 720 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 720 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 720 may optionally include memory remotely located relative to the processor 710, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0204] Input device 730 can receive input digital or character information and generate signals related to user settings and function control of the electronic device. Output device 740 may include display devices such as a display screen.

[0205] The one or more modules are stored in the memory 720, and when executed by the one or more processors 710, they execute the circuit board defect detection method based on multi-band impedance matching in any of the above method embodiments.

[0206] The above-described product can perform the methods provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects for performing the methods. Technical details not described in detail in this embodiment can be found in the methods provided in the embodiments of this application.

[0207] The electronic devices in this application embodiments exist in various forms, including but not limited to:

[0208] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and primarily aim to provide voice and data communication. These terminals include smartphones, multimedia phones, feature phones, and low-end phones.

[0209] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include: PDAs, MIDs, and UMPCs, etc.

[0210] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes audio and video players, handheld game consoles, e-book readers, as well as smart toys and portable car navigation devices.

[0211] (4) Other airborne electronic devices with data interaction capabilities, such as vehicle-mounted systems installed on vehicles.

[0212] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0213] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0214] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A circuit board defect detection method based on multi-band impedance matching, comprising: Based on the frequency band bias voltage relationship table, determine the corresponding test bias voltage of the reconfigurable impedance matching network at multiple test frequencies; The reconfigurable impedance matching network includes multiple adjustable elements and is coupled to the test probe, and the frequency band bias voltage relationship table includes the relationship between multiple frequency points and bias voltages pre-calibrated for a defect-free circuit board. For each of the aforementioned test frequencies, a test bias voltage matching the test frequency is applied to each of the adjustable elements to achieve impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency. An RF signal is then injected into the circuit board under test to acquire the corresponding complex reflection coefficient through the test probe. The test probe moves along a pre-planned grid path on the circuit board surface, automatically switching to the current frequency at each grid point, recording and buffering the complex reflection coefficient once. The complex reflection coefficients corresponding to each test frequency point are analyzed based on a multi-frequency sparse dictionary and compressed sensing algorithm to reconstruct a three-dimensional scattering image inside the circuit board, specifically including: The test probe is used at each frequency point And in the spatial sampling points Complex reflection coefficient measured at [location] According to measurement sequence number Arrange and generate measurement vectors ;in, This represents the total number of spatial sampling points at a single test frequency. Discretize the interior of the circuit board into Individual element, let the first The coordinates of the individual element center are The test probe position is Construct a measurement matrix The elements in the measurement matrix are expressed by the following formula: ， In the formula, For measurement matrix The Line number Column element, representing the first Individual factors on the first The linear coupling coefficient of the second measurement; No. Individual elements at frequency points Below, from the voxel center to probe position The electromagnetic Green's function; Indicates the frequency point of the test probe. voxel The intensity of the excited incident field, This represents the volume of each voxel; make ,in The multi-frequency sparse dictionary is obtained by training the K-SVD algorithm on multi-frequency scattering samples collected offline on healthy and defective boards. Each column is a dictionary atom to sparsely represent the scattering characteristics of various defect voxels. For three-dimensional scattering fields in the dictionary The sparse representation coefficients under the condition have only a few non-zero elements, corresponding to the sparse distribution of defect voxels; The optimal sparsity coefficients are obtained by solving the compressed sensing optimization objective function. To reconstruct a three-dimensional scattering image inside the circuit board. The compressed sensing optimization objective function is expressed by the following formula: ， In the formula, express Least squares term; express Sparse regularization term, weight Controlling sparsity; Denotes the total variation regularity term. To reconstruct the voxel vector in three dimensions The gradient operator is calculated, and the sum of its magnitudes is given. Used to suppress noise and artifacts during reconstruction. To control the weights; This represents the spectral smoothing regularization term. This is a spectral operator that smooths the reconstruction results in the frequency dimension. Control the consistency of the spectrum to ensure the continuity of reconstructed voxels at different frequency points in the frequency domain; Calculate the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and combine it with the spatial information of each circuit physical layer to obtain the hierarchical anomaly score of the corresponding circuit physical layer, so as to screen at least one anomalous circuit physical layer, specifically including: The online reconstruction obtained and indexed by voxels Arranged three-dimensional scattering images Encoder network for input variational autoencoder: , In the formula, Indicates encoder distribution, Represents a vector of latent variables. and Let these represent the mean vector and variance vector of the latent variables, respectively. The prior of the latent variables is assumed to be standard normal. ; Assuming the output likelihood of the decoder, i.e., the voxels are independent given the latent variables, then the following holds: ， In the formula, The conditional likelihood of the decoder is represented by the set of network parameters. Defined for evaluating a given latent variable. Time reconstruction value The probability of; Each voxel The negative log-likelihood is defined as its reconstructed negative log-marginal likelihood: , In the formula, Indicates the first The negative log-likelihood value of an individual element. Indicates the encoder distribution The expected value of the following mathematical expression The KL divergence between the encoder output distribution and the standard normal prior is uniformly distributed across all voxels to ensure NLL aggregation consistency. All voxels Reorganization into 3D NLL volume map of equal size ; Based on each voxel in the PCB design Corresponding physical layer index The voxel set is divided into sets of different levels. , Indicates the first The set of voxel indices of a layer; This is a physical layer mapping function, representing the mapping of voxel indices. Assign to the corresponding physical layer number; Indicates the total number of physical layers on the circuit board; For the The negative log-likelihood value of all voxels in the layer is maximized: ， In the formula, Indicates the first Layer-level anomaly score; Will Offline on the health board Layer anomaly threshold obtained from layer statistics Compare, take ， Output the set of layer indices of the physical layers of the detected abnormal circuits. ; For each of the abnormal circuit physical layers, at least one abnormal voxel point with a negative log-likelihood value exceeding the layer abnormality threshold is extracted from the abnormal circuit physical layer according to a preset voxel sliding window, and the corresponding local abnormal voxel cluster is obtained by pixel clustering. Extract the cluster morphology features corresponding to each local voxel cluster; the cluster morphology features include at least one of the following: voxel number, axial range, volume-to-surface area ratio, and shape factor; The cluster morphological features are matched according to a predefined defect type feature pattern library to output the circuit board defect type for the circuit board under test. The circuit board defect type includes at least one of the following: micro-hole crack, interlayer delamination, blind buried via peeling or dielectric layer void.

2. The method according to claim 1, wherein, The generation of the bias voltage relationship table for the aforementioned frequency band includes: Obtain the preset frequency point set and the initial bias voltage vector: , ， ， In the formula, This refers to a preset set of frequency points, which includes 0.7GHz, 2GHz, 5GHz, and 9GHz. Indicates the first One preset frequency point This indicates the total number of preset frequency points. Indicates the first The initial bias voltage vector at a preset frequency point; This indicates the number of adjustable elements in the reconfigurable impedance matching network, corresponding to the dimension of the bias voltage vector; and These represent the lower and upper limits of the bias voltage for each adjustable element, respectively. Indicates the voltage step size; Indicates the voltage range The total number of equally divided segments is used to construct a discrete candidate voltage value set; For each preset frequency point, the following two-stage combined optimization is performed on a defect-free circuit board to obtain the corresponding optimal bias voltage, specifically including: The cost function is defined as follows: ， ， In the formula, Indicates the first Preset frequency points Below, regarding the bias voltage vector Calculate the overall cost function; and These represent the weighting coefficients for the amplitude term of the complex reflection coefficient and the weighting coefficients for the standing wave ratio deviation term, respectively. Indicates frequency point And apply a bias voltage vector At that time, the complex reflection coefficient measured at the test probe; This represents the magnitude of the complex reflection coefficient. Indicates frequency point And apply a bias voltage vector At that time, the voltage standing wave ratio measured at the test probe; In the first stage, a cost function is fitted according to the Gaussian process surrogate model, the training set is initialized using the initial bias voltage vector, bias voltage sampling iteration is performed using the EI function, and the approximate optimal bias matrix is ​​solved through Bayesian optimization. EI functions are expressed by the following formula: ， In the formula, The acquisition function used in Bayesian optimization to select the next bias voltage vector is used to measure the performance of candidates. Expected cost improvement; This is the expectation operator, indicating that the expectation is taken for the improved value under the Gaussian process surrogate model; This represents the minimum cost value observed in the current training set; For the In the next iteration, perform the following operations: Maximize the EI function value from the current Gaussian process proxy model to select the bias voltage vector. , Injecting frequency points using a vector network analyzer and in the bias voltage vector The complex reflection coefficient and voltage standing wave ratio are measured to iteratively calculate the corresponding values. , Will Add to the training set to update the Gaussian process proxy model; Repeated iterations This yields an approximate optimal bias voltage vector. ; In the second stage, the central difference method is used to solve for the approximate gradient of each bias component in the approximate optimal bias voltage vector: ， In the formula, The cost function is expressed as follows: The Middle Bar offset components The partial derivatives, It represents a small voltage disturbance used for numerical differentiation; for The 1st dimension in 3D space Unit vectors, representing only the bias components Add perturbation; The approximate optimal bias voltage vector is iteratively updated based on the gradient descent step size: ， In the formula, Indicates the first Bias voltage vector in subgradient iteration This represents the gradient descent step size. Represents the gradient vector Used to guide the direction of updates; If two consecutive iterations satisfy Then let ,in Indicates the convergence threshold. Indicates the first The optimal bias voltage vector for each frequency point; Each optimal bias voltage vector is loaded into the matching network in sequence, and the voltage standing wave ratio (VSWR) is measured at the corresponding frequency. If there is a frequency in the measured VSWR that exceeds the preset VSWR threshold, it is confirmed that the frequency does not meet the flatness requirement and the process is reversed to the second stage of the frequency for local fine-tuning. If the measured voltage standing wave ratio (VSWR) at each frequency point does not exceed the preset VSWR threshold, then the corresponding optimal bias voltage at each frequency point is output to generate a frequency band bias voltage relationship table.

3. The method according to claim 1, wherein, The adjustable element is a PIN diode array. Each PIN diode achieves radio frequency conduction or cutoff state by applying a forward or reverse bias current. The PIN diode array is integrated in series or parallel in the main signal path or bypass branch of the reconfigurable impedance matching network. By controlling the conduction combination of different PIN diodes in the PIN diode array through the test bias voltage, the equivalent inductance and / or equivalent capacitance of the corresponding branch are changed, thereby achieving impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency.

4. A circuit board defect detection system based on multi-band impedance matching, used to implement the method as described in any one of claims 1-3; the system comprises: The reconfigurable bias determination unit is used to determine the corresponding test bias voltage of the reconfigurable impedance matching network at multiple test frequencies based on the frequency band bias voltage relationship table. The reconfigurable impedance matching network includes multiple adjustable elements and is coupled to the test probe, and the frequency band bias voltage relationship table includes the relationship between multiple frequency points and bias voltages pre-calibrated for a defect-free circuit board. The bias impedance matching unit is used to apply a test bias voltage matching the test frequency to each of the adjustable elements for each test frequency to achieve impedance matching between the reconfigurable impedance matching network and the circuit board under test at the corresponding test frequency, and to inject radio frequency signals into the circuit board under test so as to acquire the corresponding complex reflection coefficient through the test probe. The three-dimensional scattering reconstruction unit is used to analyze the complex reflection coefficients corresponding to each of the test frequency points based on a multi-frequency sparse dictionary and compressed sensing algorithm, so as to reconstruct the three-dimensional scattering image inside the circuit board. Anomaly layer identification unit is used to calculate the negative log-likelihood distribution corresponding to the three-dimensional scattering image, and to obtain the hierarchical anomaly score of the corresponding circuit physical layer in combination with the spatial information of each circuit physical layer, so as to screen at least one abnormal circuit physical layer.

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