Minimum system circuit of multi-core DSP + FPGA hardware platform

Abstract

A minimum system circuit of a multi-core DSP + FPGA hardware platform comprises a power supply circuit, a reset circuit, a clock circuit and a communication circuit, the power supply circuit adopts a dual-channel switch type DC / DC module to supply power to kernel power supplies of a DSP and an FPGA at the same time, and adopts two four-channel switch type DC / DC modules to supply power to IO power supplies and auxiliary power supplies of the DSP and the FPGA. The two-channel switch type DC / DC module is connected with the two four-channel switch type DC / DC modules; and the DDR power supply LDO modules for the DSP and the FPGA are respectively controlled by the two four-channel switch type DC / DC modules. A plurality of modules are mutually connected and matched, power rail power-on sequence control is achieved through interconnection of an input enabling pin and a power-on completion mark pin, logic participation of a DSP and an FPGA is not needed, the power requirement for full-speed operation of a heterogeneous multi-core processor is met, and the performance of a multi-core DSP + FPGA hardware platform is improved.

Description

Technical Field

[0001] The present invention relates to the field of embedded computers, and more specifically, to a minimum system circuit of a multi-core DSP+FPGA hardware platform for an embedded computer. Background Art

[0002] Multi-processor systems are currently the mainstream technology of embedded computers. The cooperative processing architecture based on "DSP+FPGA" has become the preferred choice for standard hardware platforms due to its excellent computing performance and resource expansion capabilities. The core of the minimum system of the DSP+FPGA hardware platform is: (1) high-performance DSP and FPGA; (2) power supply circuit; (3) clock circuit; (4) communication circuit between DSP and FPGA.

[0003] CN102567280B discloses a design method for a computer hardware platform based on DSP and FPGA. Its power supply circuit only uses a single power supply chip TPS70445, with low power and does not meet the power-on sequence requirements of multiple power rails. "Design of the Hardware Platform of an On-board Computer Based on a Domestic Multi-core DSP+FPGA Architecture" by Jing Desheng et al., Aeronautical Computing Technique, November 2021 discloses a design method for the peripheral circuits of some DSP+FPGA dual-core processors. However, its clock circuit design uses multiple crystal oscillators + clock drivers, and the FPGA is required to participate in converting the clock interface voltage. In current circuit designs, the power supply circuit does not meet the requirements of high power and power-on sequence of multiple power rails, and the clock circuit is complex in composition and poor in synchronization, affecting the performance of the multi-core DSP+FPGA hardware platform. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a minimum system circuit of a multi-core DSP+FPGA hardware platform to solve problems such as the difficulty of the power supply circuit in meeting the power-on sequence requirements of multiple power rails.

[0005] The technical solution adopted by the present invention to solve the above technical problems is as follows: A minimum system circuit of a multi-core DSP+FPGA hardware platform includes a power supply circuit for power supply, a reset circuit for FPGA reset, a clock circuit for providing a clock signal, and a communication circuit for communication between the DSP and the FPGA. The power supply circuit includes multiple DC / DC modules and LDO modules. Among them, a dual-channel switched-mode DC / DC module is used to supply power to the core power supplies of both the DSP and the FPGA at the same time. Two four-channel switched-mode DC / DC modules are used to supply power to the IO power supply and auxiliary power supply of the DSP and the FPGA. The enable input pin that controls the power supply to the FPGA core power supply in the dual-channel switched-mode DC / DC module is provided with an enable signal by the power-on completion flag pin of the clock network power supply. The enable input pin that controls the power supply to the DSP core power supply in the dual-channel switched-mode DC / DC module is provided with an enable signal by one of the four-channel switched-mode DC / DC modules based on the power-on completion flag pin after the DSP digital IO power supply is powered on by the system main power supply; the dual-channel switched-mode DC / DC module is connected to the two four-channel switched-mode DC / DC modules, and the power-on sequence control of the power rails is realized through the interconnection of the input enable pin and the power-on completion flag pin; the DDR power supply LDO modules for the DSP and the FPGA are respectively controlled by the two four-channel switched-mode DC / DC modules.

[0006] The dual-channel switched-mode DC / DC module uses the SM4630 chip, which includes two enable input pins and two outputs, respectively used to supply power to the core power supplies of the DSP and the FPGA; the four-channel switched-mode DC / DC module uses the SM4644 chip, and the two SM4644 chips are respectively used to supply power to the internal power supply of the FPGA GTX transceiver, the FPGA auxiliary power supply, the FPGA GTX transceiver terminal analog power supply, the FPGA DDR IO power supply, the DSP digital IO power supply, the DSP DDR IO power supply, the DSP SERDES core power supply, and the 3.3V power supply of other circuits.

[0007] The LDO module includes multiple SM74401 chips, which are respectively used to supply power to the FPGA GTX auxiliary analog QPLL power supply, the FPGA IO auxiliary power supply, and the DSP SERDES IO power supply. It also includes two SM51200 chips, which are respectively used to supply power to the DDR power supplies of the DSP and the FPGA and the external DDR chip power supply.

[0008] The power-on sequence of each power rail of the FPGA is as follows: The main power enables the power-on of the clock network power supply. After its power-on completion flag is input, the dual-channel switched-mode DC / DC module enables the power-on of the FPGA core power supply. After its power-on completion flag is input, the quad-channel switched-mode DC / DC module enables the power-on of the internal power supply of the FPGA GTX transceiver and the FPGA auxiliary power supply. After completion, the two power-on completion flags respectively enable the power-on of the terminal analog power supply of the FPGA GTX transceiver and the FPGA DDR IO power supply. After the power-on of the terminal analog power supply of the FPGA GTX transceiver is completed, the FPGA first completion flag is output. The power-on completion flag after the power-on of the FPGA DDR IO power supply enables the power-on of the 3.3V power supply of other circuits. After completion, the power-on completion flag enables the FPGA GTX auxiliary analog QPLL power supply and the FPGA IO auxiliary power supply, and the FPGA second completion flag and the FPGA third completion flag are respectively output after completion. The FPGA first completion flag, the FPGA second completion flag, and the FPGA third completion flag are simultaneously connected to the indication circuit. The indication circuit lights up the FPGA power-on completion indicator when the FPGA first completion flag, the FPGA second completion flag, and the FPGA third completion flag are all valid.

[0009] The power-on sequence of each power rail of the DSP is as follows: The main power enables the DSP digital IO power supply. Its power-on completion flag enables the DSP core power supply and the DSP DDR IO power supply. After the power-on of the DSP DDR IO power supply is completed, the DSP first completion flag is output. The power-on completion flag after the power-on of the DSP core power supply enables the DSP SERDES core power supply and the DSP SERDES IO power supply, and the DSP second completion flag and the DSP third completion flag are respectively output after completion. The DSP first completion flag, the DSP second completion flag, and the DSP third completion flag are simultaneously connected to the indication circuit. The indication circuit lights up the DSP power-on completion indicator when the DSP first completion flag, the DSP second completion flag, and the DSP third completion flag are all valid.

[0010] The described clock circuit includes a first clock network for generating clock signals for the DSP core, the FPGA core, the DSP peripheral DDR, and the DSP PASSCLK, a second clock network for generating clock signals for the SRIO interface for communication between the DSP and the FPGA, and a third clock network for generating clock signals for the input clock of the FPGA peripheral DDR. Among them, the first clock network and the second clock network are generated by corresponding clock chips based on the same crystal oscillator, and the third clock network is generated based on an independent crystal oscillator.

[0011] The first clock network and the second clock network respectively adopt the SM3807 chip and the GMD841608 chip. The SM3807 chip of the first clock network generates a corresponding 25 MHz clock signal based on a 25 MHz crystal oscillator input. The SM3807 chip also outputs the 25 MHz signal to the GMD841608 chip of the second clock network for it to generate a corresponding 125 MHz clock signal.

[0012] The third clock network mentioned above generates a 100 MHz differential clock signal by the SCX023G100MCVIT chip.

[0013] The FPGA selected is the SMQ7K325TFFG900 chip, and the DSP selected is the FT-M6678 chip.

[0014] A four-channel SRIO high-speed transceiver circuit is used for communication connection between the FPGA and the DSP.

[0015] The beneficial effects of the present invention are as follows: adopting a heterogeneous dual-processor architecture of multi-core high-performance DSP + FPGA can not only meet the real-time high computing power requirements but also flexibly expand the interface resources through the FPGA. The power supply circuit adopts multiple DC / DC modules and LDO modules. The multiple modules are interconnected and cooperate with each other. The power-on sequence control of the power rails is realized through the interconnection of the input enable pin and the power-on completion flag pin, without the participation of the logic of the DSP and the FPGA. It powers on independently, shortens and stabilizes the startup time of the heterogeneous dual-processor architecture, enables the power-on sequence to meet the best requirements of the power supply power, ripple voltage, etc. of each part of the DSP and the FPGA, enables it to meet the power requirements for the full-speed operation of the heterogeneous multi-core processor, and improves the performance of the multi-core DSP + FPGA hardware platform.

[0016] Furthermore, the first clock network synchronously drives the system clocks of the DSP core and the FPGA core to ensure that both are driven by the same external clock source. The second clock network obtains the clock signal from the first clock network, making the first clock network and the second clock network have the same source. The third clock network with a separate crystal oscillator generates the FPGA peripheral DDR input clock signal, which not only simplifies the clock circuit design but also ensures the clock synchronization of the heterogeneous dual-core processor.

[0017] Furthermore, the FPGA and the DSP are connected by a four-channel SRIO high-speed transceiver communication circuit and an EMIF communication circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the system circuit structure of the present invention.

[0019] Figure 2 is a schematic diagram of the composition and connection of the power supply circuit of the present invention.

[0020] Figure 3 It is a schematic diagram of the connection of the reset circuit.

[0021] Figure 4 It is a schematic diagram of the composition and connection of the clock circuit of the present invention.

[0022] Figure 5 It is a schematic diagram of the connection of the power supply circuit of the FPGA.

[0023] Figure 6 It is a schematic diagram of the connection of the power supply circuit of the DSP.

[0024] Figure 7 It is a schematic diagram of the connection of the SRIO communication circuit between the FPGA and the DSP.

[0025] Figure 8 It is a schematic diagram of the connection of the EMIF communication circuit between the FPGA and the DSP. Specific implementation manners

[0026] The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and specific implementation manners. The specific contents listed in the following embodiments are not limited to the technical features necessary for solving the technical problems recorded in the claims. At the same time, the listed embodiments are only a part of the present invention, rather than all embodiments.

[0027] As Figure 1 shown, the minimum system circuit of the multi-core DSP+FPGA hardware platform of the present invention includes an FPGA, a DSP and its related circuits. The FPGA can select the domestic FPGA chip SMQ7K325TFFG900, and the DSP can select the domestic multi-core DSP chip FT-M6678 to meet the high-performance requirements of the platform. The related circuits include a power supply circuit, a reset circuit, a clock circuit, a communication circuit, etc. Among them, the power supply circuit is used to supply power to the FPGA and the DSP.

[0028] As Figure 2As shown, the power supply circuit includes multiple DC / DC modules and LDO modules. Specifically, it includes a dual-channel switching DC / DC module and two quad-channel switching DC / DC modules. The dual-channel switching DC / DC module selects the SM4630 chip, which includes two enable input pins and two outputs. The output voltage of each path is adjustable and can provide a stable current of 18A. It has an output voltage tracking function for power rail sequencing, meeting the fast response requirements of large loads and high power. The present invention uses the SM4630 for power supply to the cores of DSP and FPGA. The quad-channel switching DC / DC module selects the SM4644 chip. The output voltage of each path is adjustable and can provide a stable current of 4A. It has an output voltage tracking function for power rail sequencing. The present invention uses two SM4644 chips for power supply to the IO power and auxiliary power of DSP and FPGA, such as for the internal power supply of the FPGA GTX transceiver, the FPGA auxiliary power supply, the terminal analog power supply of the FPGA GTX transceiver, the FPGA DDR IO power supply, the DSP digital IO power supply, the DSP DDRIO power supply, the DSP SERDES core power supply, and the 3.3V power supply of other circuits.

[0029] The multiple LDO modules include multiple SM74401 chips and two SM51200 chips. Figure 2 In the embodiment, 3 SM74401 chips are used. The SM74401 chip is a high-performance, low-dropout LDO (linear voltage regulator) module. It can provide a stable current of 3A for a single path and has an output voltage tracking function for power rail sequencing. It is used for power supply to the power with lower ripple requirements of DSP and FPGA, such as for power supply to the FPGA GTX auxiliary analog QPLL power supply, the FPGA IO auxiliary power supply, and the DSP SERDES IO power supply respectively. The SM51200 chip is an LDO (linear voltage regulator) module specifically used for DDR devices. The two SM51200 chips are respectively used for power supply to the DDR power of DSP and FPGA and the power supply to the external DDR chips.

[0030] Multiple modules are interconnected and coordinated to achieve power rail power-up sequence control through the interconnection of the input enable pin and the power-up completion flag pin. Among them, the enable input pin that controls the power supply of the FPGA core in the dual-channel switched-mode DC / DC module SM4630 is provided with an enable signal by the power-up completion flag pin of the clock network power supply. The enable input pin that controls the power supply of the DSP core in the dual-channel switched-mode DC / DC module is provided with an enable signal by one of the four-channel switched-mode DC / DC modules SM4644 based on the DSP digital IO power supply being powered up by the system main power supply and then using its power-up completion flag pin; the dual-channel switched-mode DC / DC module is connected to two four-channel switched-mode DC / DC modules, and power rail power-up sequence control is achieved through the interconnection of the input enable pin and the power-up completion flag pin; the DDR power supply LDO modules for the DSP and FPGA are respectively controlled by two four-channel switched-mode DC / DC modules.

[0031] Figure 2 The signal meanings of the input and output pins of each chip are shown, and the corresponding power-up steps (FPGA-STEP1 to FPGA-STEP7, DSP--STEP1 to DSP—STEP5) are marked on the output signals.

[0032] The power-up sequence of each power rail of the FPGA is as follows: (1), FPGA-STEP1: The main power supply +5V (P1_RUN) enables the clock network power supply 3.3V (P1_OUT) and the power-up completion flag CLK_3.3V_PG (P1_PGOOD).

[0033] (2), FPGA-STEP2: The power-up completion flag CLK_3.3V_PG is input to the dual-channel switched-mode DC / DC module P2 (SM4630AMPV), and through P2_RUN1, it enables the FPGA core power supply 1.0V (P2_OUT1) and the power-up completion flag FPGA_INT_1.0V_PG (P2_PGOOD1).

[0034] (3), FPGA-STEP3: The power-up completion flag FPGA_INT_1.0V_PG is respectively input to two four-channel switched-mode DC / DC modules P3, P4 (SM4644MPY), and through P3_RUN1, P4_RUN4, it enables the internal power supply 1.0V (P3_OUT1) of the FPGA GTX transceiver, the FPGA auxiliary power supply 1.8V (P4_OUT4), and the power-up completion flags FPGA_MGTAVCC_1.0V_PG (P3_PGOOD1), FPGA_AUX_1.8V_PG (P4_PGOOD4).

[0035] (4) FPGA-STEP4: The power-on completion flag FPGA_MGTAVCC_1.0V_PG enables the FPGA GTX transceiver terminal analog power supply 1.2V (P3_OUT2) and the FPGA first completion flag FPGA_ALL_PG (P3_PGOOD2) through P3_RUN2; at the same time, the power-on completion flag FPGA_MGTAVCC_1.0V_PG enables the FPGA DDR IO power supply 1.5V (P3_OUT3) and the power-on completion flag FPGA_DDR_1.5V_PG (P3_PGOOD3) through P3_RUN3.

[0036] (5) FPGA-STEP5: The power-on completion flag FPGA_DDR_1.5V_PG enables the 3.3V power supply (P3_OUT4) of other circuits and the power-on completion flag 3.3V_PG (P3_PGOOD4) through P3_RUN4.

[0037] (6) FPGA-STEP6: The power-on completion flag 3.3V_PG enables the FPGA GTX auxiliary analog QPLL power supply 1.0V (P5_OUT), the FPGA second completion flag FPGA_ALL_PG (P5_PGOOD), the FPGA IO auxiliary power supply 2.0V (P6_OUT), and the FPGA third completion flag FPGA_ALL_PG (P6_PGOOD) through P5_RUN and P6_RUN respectively. The LDO module P7 (SM51200DRCR) that supplies power to the FPGA's DDR power supply and the external DDR chip power supply is input with the FPGA DDR IO power supply (FPGA DDR 1.5V) output from step (4), and the enable signal is the 3.3V power supply for other circuits output from step (5). After power-on is completed, the FPGA fourth completion flag FPGA_ALL_PG (P7_PGOOD) is output.

[0038] (7) FPGA-STEP7: The FPGA first completion flag FPGA_ALL_PG (P3_PGOOD2), the FPGA second completion flag FPGA_ALL_PG (P5_PGOOD), the FPGA third completion flag FPGA_ALL_PG (P6_PGOOD) and the FPGA fourth completion flag FPGA_ALL_PG (P7_PGOOD) are connected to the indication circuit at the same time. The completion flag FPGA_ALL_PG signal is an open-drain type. When each FPGA_ALL_PG is valid at the same time, the FPGA power-on completion indicator V1 is lit. At this point, each FPGA power rail is powered on successfully in sequence.

[0039] The power-on sequence of each power rail of DSP is: (1) DSP-STEP1: The main power supply +5V is input into a four-channel switching DC / DC module P4, and the DSP digital IO power supply 1.8V (P4_OUT2) and the power-on completion flag DSP_IO_1.8V_PG (P1_PGOOD2) are enabled through P4_RUN2; the DSP digital IO power supply 1.8V (DSP IO 1.8V) is input into the LDO module P8 for DSP SERDES IO power supply.

[0040] (2) DSP-STEP2: The power-on completion flag DSP_IO_1.8V_PG is input to the dual-channel switching DC / DC module P2, and enables the DSP core power supply 0.95V (P2_OUT2) and the power-on completion flag DSP_INT_0.95V_PG (P2_PGOOD2) through P2_RUN2; at the same time, the power-on completion flag DSP_IO_1.8V_PG enables the DSP DDR IO power supply 1.5V (P4_OUT1) and the DSP first completion flag DSP_ALL_PG (P4_PGOOD1) through P4_RUN1; (3) DSP-STEP3: DSP DDR IO power supply 1.5V (DSP DDR 1.5V) is input to the input pin of LDO module P9 for DSP DDR power supply and external DDR chip power supply. The enable pin P9_RUN of LDO module P9 is driven by the 3.3V signal of other circuits mentioned above. The power-on completion flag DSP_INT_0.95V_PG is input to the four-channel switch type DC / DC module P4 on the one hand, and enables DSP SERDES core power supply 0.95V (P4_OUT3) and DSP second completion flag DSP_ALL_PG (P4_PGOOD3) through P4_RUN3; the power-on completion flag DSP_INT_0.95V_PG is input to an LDO module P8 for DSP SERDES IO power supply on the other hand, and enables DSP SERDES IO power supply 1.5V (P8_OUT) and DSP third completion flag DSP_ALL_PG (P8_PGOOD) through P8_RUN.

[0041] (4) DSP-STEP4: The DSP first completion flag DSP_ALL_PG (P4_PGOOD1), the DSP second completion flag DSP_ALL_PG (P4_PGOOD3) and the DSP third completion flag DSP_ALL_PG (P8_PGOOD) are connected to the indication circuit at the same time. When each DSP_ALL_PG is valid at the same time, the DSP power-on completion indicator V2 is turned on. At this point, the DSP power rails are powered on successfully in sequence.

[0042] According to the above design, the actual power-on sequence of each power rail of the FPGA and DSP is as follows: 1) FPGA: Clock network power supply 3.3V (FPGA-STEP1) → FPGA core power supply 1.0V (FPGA-STEP2) → Internal power supply 1.0V of FPGA GTX transceiver, FPGA auxiliary power supply 1.8V (FPGA-STEP3) → Terminal analog power supply 1.2V of FPGA GTX transceiver, FPGA DDR IO power supply 1.5V (FPGA-STEP4) → 3.3V power supply for other circuits (FPGA-STEP5) → Auxiliary analog QPLL power supply 1.0V of FPGA GTX, FPGA IO auxiliary power supply 2.0V, FPGA DDR chip reference power supply 0.75V, FPGA DDR termination power supply 0.75V (FPGA-STEP6) → FPGA power-on completion indicator V1 (FPGA-STEP7); 2) DSP: DSP digital IO power supply 1.8V (DSP-STEP1) → DSP core power supply 0.95V, DSP DDR IO power supply 1.5V (DSP-STEP2) → DSP SERDES core power supply 0.95V, DSP SERDES IO power supply 1.5V, DSP DDR chip reference power supply 0.75V, DSP DDR termination power supply 0.75V (DSP-STEP3) → DSP power-on completion indicator V2 (DSP-STEP4).

[0043] Figure 3 The figure shows a schematic diagram of the reset circuit connection, which is used for FPGA reset. After the FPGA configuration is completed, it controls the SM706 chip to output a reset signal (RESET_N) and a power error indication signal (PF0_N) to the FPGA to complete the reset and monitoring of the FPGA.

[0044] Figure 4The figure shows the composition and connection schematic diagram of the clock circuit. The clock circuit includes three clock networks. The first clock network is used to provide a 25MHz clock signal for the DSP core, FPGA core, DSP peripheral DDR, and DSP PASSCLK. The second clock network is used to provide a 125MHz clock signal for the SRIO interface for communication between the DSP and FPGA. The third clock network is used to provide a 100MHz differential clock signal for the FPGA peripheral DDR input clock. Among them, the first clock network and the second clock network are of the same origin, both originating from the same 25MHz crystal oscillator. The external clock source frequency is less than 50Mhz, and the high main frequency requirement is realized by the internal PLL of the chip to improve the reliability of the clock circuit. As shown in the figure, a single crystal oscillator (SCXO-7050DFB-25MHZ) outputs 25MHz to the clock driver chip (SM3807) of the first clock network. The SM3807 chip of the first clock network generates a corresponding 25MHz clock signal based on the 25MHz crystal oscillator input. The SM3807 chip also outputs the 25MHz signal to the clock management chip (GMD841608) of the second clock network for generating a corresponding 125MHz clock signal. The third clock network separately generates a 100MHz differential clock signal by a crystal oscillator (SCX023G100MCVIT).

[0045] In the present invention, the FPGA selects SMQ7K325TFFG900, which has rich logic resources and excellent performance. The FPGA circuit mainly includes an FPGA power supply circuit, an FPGA configuration circuit, and an FPGA and DDR circuit.

[0046] The FPGA power supply circuit is as Figure 5 shown, and the pin definitions of each circuit are as follows in the table: The FPGA configuration circuit and the FPGA and DDR circuit refer to the existing technical documents and will not be described in detail.

[0047] In the present invention, the DSP selects FT-M6678, which is a high-performance multi-core floating-point DSP with a single-core frequency of 1.25GHz, meeting the requirements of high-performance computing, and is applied in fields such as radar signal processing, image processing, and flight control. The DSP circuit has a DSP power supply circuit and a DSP and DDR circuit. The DSP power supply circuit is as Figure 6 shown.

[0048] Two high-speed communication circuits, SRIO and EMIF, are designed between the DSP and FPGA heterogeneous dual processors, ensuring high-speed data transmission and processing. Among them, the SRIO (Serial RapidIO high-speed serial communication) communication circuit transmits high-speed serial differential signals and features high bandwidth, low latency, and high efficiency. The present invention adopts a four-channel SRIO high-speed transceiver circuit, which can achieve a communication rate of 1.25 Gb / s per channel.

[0049] Figure 7 The following figure shows the schematic diagram of the SRIO communication circuit connection. The communication circuit connections are as follows in the table: EMIF, i.e., the external memory interface, is a general data interface on the DSP device and can realize the connection between the DSP and different types of memories. When the DSP and FPGA are connected through EMIF, the FPGA is mapped as the storage space of the DSP. After actual use and testing, the communication rate is more than 20 MB / s.

[0050] Figure 8 The following figure shows the schematic diagram of the EMIF communication circuit connection. The communication circuit connections are as follows in the table: The above description of the specific implementation manners is only used to help understand the technical concept and its core idea of the present invention. Although specific preferred embodiments are used in this article to describe and illustrate the technical solutions, it should not be construed as a limitation to the present invention itself. Those skilled in the art can make various changes in form and details without departing from the technical concept of the present invention. These easily conceived changes or substitutions should be covered within the protection scope of the present invention.

Claims

1. A minimum system circuit of a multi-core DSP + FPGA hardware platform, comprising a power supply circuit for power supply, a reset circuit for FPGA reset, a clock circuit for providing clock signals, and a communication circuit for communication between the DSP and the FPGA, characterized in that: The described power supply circuit includes multiple DC / DC modules and LDO modules. Among them, a dual-channel switching DC / DC module is used to supply power to the core power supplies of both the DSP and the FPGA simultaneously. Two four-channel switching DC / DC modules are used to supply power to the IO power supplies and auxiliary power supplies of the DSP and the FPGA. The enable input pin that controls the power supply to the FPGA core power supply in the dual-channel switching DC / DC module is provided with an enable signal by the power-on completion flag pin of the clock network power supply. The enable input pin that controls the power supply to the DSP core power supply in the dual-channel switching DC / DC module is provided with an enable signal by one of the four-channel switching DC / DC modules based on the power-on completion flag pin after the DSP digital IO power supply is powered on by the system main power supply; the dual-channel switching DC / DC module is connected to the two four-channel switching DC / DC modules, and the power-on sequence control of the power rails is realized through the interconnection of the input enable pin and the power-on completion flag pin; the LDO modules for the DDR power supply of the DSP and the FPGA are respectively controlled by the two four-channel switching DC / DC modules.

2. The minimum system circuit of a multi-core DSP+FPGA hardware platform as described in claim 1, characterized in that: The described dual-channel switching DC / DC module uses the SM4630 chip, which includes two enable input pins and two outputs, respectively used to supply power to the core power supplies of the DSP and the FPGA; the described four-channel switching DC / DC module uses the SM4644 chip, and the two SM4644 chips are respectively used to supply power to the internal power supply of the FPGA GTX transceiver, the FPGA auxiliary power supply, the terminal analog power supply of the FPGA GTX transceiver, the FPGA DDR IO power supply, the DSP digital IO power supply, the DSP DDR IO power supply, the DSP SERDES core power supply, and the 3.3V power supply of other circuits.

3. The minimum system circuit of a multi-core DSP+FPGA hardware platform as described in claim 1, characterized in that: The described LDO module includes multiple SM74401 chips, which are respectively used to supply power to the FPGA GTX auxiliary analog QPLL power supply, the FPGA IO auxiliary power supply, and the DSP SERDES IO power supply. It also includes two SM51200 chips, which are respectively used to supply power to the DDR power supplies of the DSP and the FPGA and the power supply of the external DDR chip.

4. The minimum system circuit of a multi-core DSP+FPGA hardware platform according to claim 2, characterized in that: The power-on sequence of each power rail of the FPGA is as follows: The main power enables the power-on of the clock network power supply. After its power-on completion flag is input, the dual-channel switched-mode DC / DC module enables the power-on of the FPGA core power supply. After its power-on completion flag is input, the quad-channel switched-mode DC / DC module enables the power-on of the internal power supply of the FPGA GTX transceiver and the FPGA auxiliary power supply. The two power-on completion flags after completion respectively enable the power-on of the FPGA GTX transceiver terminal analog power supply and the FPGA DDR IO power supply. After the power-on of the FPGA GTX transceiver terminal analog power supply is completed, the FPGA first completion flag is output. The power-on completion flag after the power-on of the FPGA DDR IO power supply enables the power-on of the 3.3V power supply of other circuits. The power-on completion flag after completion enables the FPGA GTX auxiliary analog QPLL power supply and the FPGA IO auxiliary power supply, and the FPGA second completion flag and the FPGA third completion flag are respectively output after completion. The FPGA first completion flag, the FPGA second completion flag, and the FPGA third completion flag are simultaneously connected to the indication circuit. The indication circuit lights up the FPGA power-on completion indicator when the FPGA first completion flag, the FPGA second completion flag, and the FPGA third completion flag are all valid.

5. The minimum system circuit of a multi-core DSP+FPGA hardware platform according to claim 2, characterized in that: The power-on sequence of each power rail of the DSP is as follows: The main power enables the DSP digital IO power supply. Its power-on completion flag enables the DSP core power supply and the DSP DDR IO power supply. After the power-on of the DSP DDR IO power supply is completed, the DSP first completion flag is output. The power-on completion flag after the power-on of the DSP core power supply enables the DSP SERDES core power supply and the DSP SERDES IO power supply, and the DSP second completion flag and the DSP third completion flag are respectively output after completion. The DSP first completion flag, the DSP second completion flag, and the DSP third completion flag are simultaneously connected to the indication circuit. The indication circuit lights up the DSP power-on completion indicator when the DSP first completion flag, the DSP second completion flag, and the DSP third completion flag are all valid.

6. The minimum system circuit of a multi-core DSP+FPGA hardware platform as described in claim 1, characterized in that: The described clock circuit includes a first clock network for generating clock signals for the DSP core, FPGA core, DSP peripheral DDR, and DSP PASSCLK, a second clock network for generating clock signals for the DSP and FPGA communication SRIO interface, and a third clock network for generating clock signals for the FPGA peripheral DDR input. Among them, the first clock network and the second clock network are generated by corresponding clock chips based on the same crystal oscillator, and the third clock network is generated based on an independent crystal oscillator.

7. The minimum system circuit of a multi-core DSP+FPGA hardware platform according to claim 6, characterized in that: The first clock network and the second clock network respectively use the SM3807 chip and the GMD841608 chip. The SM3807 chip of the first clock network generates the corresponding 25MHz clock signal based on the 25MHz crystal oscillator input. The SM3807 chip also outputs the 25MHz signal to the GMD841608 chip of the second clock network for it to generate the corresponding 125MHz clock signal.

8. The minimum system circuit of a multi-core DSP+FPGA hardware platform according to claim 6, characterized in that: The third clock network generates a 100 MHz differential clock signal by the SCX023G100MCVIT chip.

9. The minimum system circuit of a multi-core DSP+FPGA hardware platform according to claim 1, characterized in that: The selected FPGA is the SMQ7K325TFFG900 chip, and the selected DSP is the FT-M6678 chip.

10. The minimum system circuit of a multi-core DSP + FPGA hardware platform according to claim 1, characterized in that: A four-channel SRIO high-speed transceiver communication circuit and an EMIF communication circuit are used to connect the FPGA and the DSP.

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