FPGA (Field Programmable Gate Array) loading configuration method, chip circuit and routing equipment
By dynamically switching the AS and PS modes of the FPGA, and using CPLD and MUX to realize configuration path switching, solving the low efficiency and reliability problems caused by static FPGA configuration mode, and improving the system's adaptability and fault tolerance capabilities.
Patent Information
- Application Number
- CN202510388542.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-18
Smart Images
Figure CN120336251A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of communication technologies, and particularly to a method for loading and configuring an FPGA, a chip circuit, and a routing device. Background Art
[0002] The loading and configuration of an FPGA (Field Programmable Gate Array) refers to writing the circuit configuration data designed by a user into the FPGA so that it can perform specific logic functions. The configuration of an FPGA is the basis for its flexible application, enabling it to be widely used in fields such as communication, industrial control, consumer electronics, and artificial intelligence. The FPGA uses SRAM cells to store configuration data, and the configuration data is lost after power-off, so the FPGA needs to be reconfigured every time it is powered on.
[0003] Currently, the AS (Active Serial) mode and the PS (Passive Serial) mode are the two most commonly used configuration methods due to their advantages such as simple hardware connection and low cost. The AS (Active Serial) mode means that the FPGA actively reads configuration data from an external non-volatile memory (such as FLASH) through a serial interface, and the PS (Passive Serial) mode means that the FPGA passively receives configuration data from an external controller or processor.
[0004] As FPGAs are applied more and more widely, higher requirements are placed on the flexibility and reliability of configuration. Existing technical problems include: 1) The FPGA configuration mode is usually static, set through the MODE pin during manufacturing, and cannot be dynamically switched. This results in frequent Flash programming during the development and debugging phase, with low efficiency, and different configuration methods are required during mass production, increasing the hardware complexity and cost; 2) A single configuration mode easily leads to system reliability problems, such as being unable to recover when the Flash is damaged or the transmission file fails. Summary of the Invention
[0005] To overcome the problems existing in the related technologies, this specification provides a method for loading and configuring an FPGA, a chip circuit, and a routing device.
[0006] According to the first aspect of the embodiments of this specification, a method for loading and configuring a Field Programmable Gate Array (FPGA) is provided, the method including:
[0007] The FPGA obtains a mode instruction sent by a controller;
[0008] When it is recognized that the mode instruction is a first instruction, the FPGA loads configuration from the FLASH connected below; or,
[0009] When the pattern instruction is identified as the second instruction, the FPGA loads the configuration from the Complex Programmable Logic Device (CPLD).
[0010] Wherein, when the pattern instruction is identified as the first instruction, the method further includes:
[0011] When the FPGA fails to load the configuration from the externally-connected FLASH, the CPLD is triggered to send the second instruction to the FPGA.
[0012] Wherein, the FPGA loading the configuration from the externally-connected FLASH includes:
[0013] The CPLD controls the multiplexer (MUX) to connect the data channel between the FPGA and the externally-connected FLASH.
[0014] Wherein, when the pattern instruction is identified as the second instruction, the FPGA loading the configuration from the CPLD includes:
[0015] The CPLD controls the multiplexer (MUX) to connect the data channel between the CPLD and the FPGA.
[0016] It can be seen from the above embodiments that by implementing the dynamic switching mechanism between the Active Serial (AS) mode and the Passive Serial (PS) mode, integrating the reliability of AS and the flexibility of PS, the adaptability and fault tolerance of the FPGA configuration system are realized.
[0017] According to the second aspect of the embodiments of the present specification, a chip circuit is provided, and the chip circuit includes: a first multiplexer (MUX), a Complex Programmable Logic Device (CPLD), a Field Programmable Gate Array (FPGA), and a FLASH;
[0018] The first MUX is respectively connected to the CPLD, the FPGA, and the FLASH through data channels;
[0019] When the FPGA obtains the pattern instruction sent by the CPLD, when the pattern instruction is identified as the first instruction, the FPGA loads the configuration from the externally-connected FLASH through the first MUX; or,
[0020] When the pattern instruction is identified as the second instruction, the FPGA loads the configuration from the Complex Programmable Logic Device (CPLD) through the first MUX.
[0021] Wherein, the chip circuit further includes: a second MUX;
[0022] The second MUX is respectively connected to the CPLD, the FPGA, and the FLASH through clock channels.
[0023] Among them, when it is recognized that the pattern instruction is the first instruction, the FPGA loads the configuration from the attached FLASH through the second MUX, including:
[0024] The CPLD issues an instruction to the first MUX to connect the FPGA and the FLASH, so that the FPGA loads the configuration from the FLASH through the first MUX;
[0025] When it is recognized that the pattern instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD through the first MUX, including:
[0026] The CPLD issues an instruction to the first MUX to connect the FPGA and the CPLD, so that the FPGA loads the configuration from the CPLD through the first MUX.
[0027] According to the third aspect of the embodiments of the present specification, a routing device is provided. The routing device includes a chip circuit, and the chip circuit includes: a first multiplexer MUX, a complex programmable logic device CPLD, a field programmable gate array FPGA, and a FLASH;
[0028] The first MUX is connected to the CPLD, the FPGA, and the FLASH respectively through data channels;
[0029] The FPGA obtains the pattern instruction sent by the CPLD. When it is recognized that the pattern instruction is the first instruction, the FPGA loads the configuration from the attached FLASH through the first MUX; or,
[0030] When it is recognized that the pattern instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD through the first MUX.
[0031] Among them, the chip circuit further includes: a second MUX;
[0032] The second MUX is connected to the CPLD, the FPGA, and the FLASH respectively through clock channels.
[0033] Among them, when it is recognized that the pattern instruction is the first instruction, the FPGA loads the configuration from the attached FLASH through the first MUX, including:
[0034] The CPLD issues an instruction to the first MUX to connect the FPGA and the FLASH, so that the FPGA loads the configuration from the FLASH through the first MUX;
[0035] When it is recognized that the pattern instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device (CPLD) through the first multiplexer (MUX), including:
[0036] The CPLD issues an instruction to the first MUX to connect the FPGA and the CPLD, so that the FPGA can load the configuration from the CPLD through the first MUX.
[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this specification. Brief Description of the Drawings
[0038] The drawings here are incorporated into the specification and form a part of this specification, showing the embodiments consistent with this specification, and are used together with the specification to explain the principles of this specification.
[0039] Figure 1 is a logical schematic diagram of a method for an FPGA to load a configuration shown in accordance with an exemplary embodiment of this specification.
[0040] Figure 2 is a schematic diagram of a dual-mode FPGA system configuration with dynamic switching between AS and PS shown in accordance with an exemplary embodiment of this specification. Detailed Embodiments
[0041] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.
[0042] The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit this specification. The singular forms "a", "the", and "that" used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0043] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to a determination".
[0044] Currently, in a scheme for FPGA loading configuration, the FPGA configuration file is stored locally in the CPU. When the configuration file is updated, the CPU sends the configuration file to the CPLD through a dedicated data channel. The FPGA transmits the initialization completion information to the CPLD through the configuration (data) channel, and the CPLD transmits the configuration file to the FPGA through the configuration (data) channel to complete the FPGA configuration.
[0045] When the above method only implements the mode of the FPGA passively receiving configuration data from an external controller or processor, that is, the PS mode, the single configuration mode easily leads to system reliability problems. For example, when the CPU is abnormal or the file transmission through the dedicated channel fails, the FPGA cannot load the configuration file, and the system will not be able to recover, lacking fault tolerance.
[0046] To solve the above technical problems, an embodiment of the present disclosure provides a method for FPGA loading configuration, as Figure 1 shown, the method includes:
[0047] S101 The FPGA obtains a mode instruction sent by the controller;
[0048] S102 When it is recognized that the mode instruction is the first instruction, the FPGA loads the configuration from the FLASH attached below; or,
[0049] S103 When it is recognized that the mode instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD.
[0050] In this embodiment, the mutual switching between the AS and PS modes can be realized. Usually, the user can default the FPGA loading configuration to the AS mode to implement a fast and simple FPGA loading configuration process.
[0051] In this embodiment, the configuration mode can be preset by the controller (such as the CPLD). For example, the configuration mode through the controller includes: FPGA MODE[2:0], which includes the AS mode and the PS mode. The controller can send corresponding configuration mode instructions to the FPGA according to requirements, so that the FPGA uses the AS mode or the PS mode to load the configuration.
[0052] Suppose that when the controller sends an enable signal for the AS mode to the FPGA, the FPGA loads the configuration from the attached FLASH. Specifically, the controller controls the first multiplexer (MUX) to connect the data channel between the FPGA and the attached FLASH, so that the FPGA automatically loads the configuration from the FLASH through the first MUX.
[0053] In this embodiment, the controller can detect the status of the FPGA loading the configuration in real time. When it detects that the FPGA fails to load the configuration in the AS mode (for example, when a loading failure signal is obtained, or when no notification of the completion of the configuration loading is received within a preset time, it can be determined that the FPGA fails to load the configuration).
[0054] In the example, when the controller recognizes that the FPGA fails to load the configuration in the AS mode, the controller can automatically send an enable signal for the PS mode to the FPGA. At the same time, the controller connects the data channel between the controller and the FPGA through the first MUX. In the PS mode, the controller obtains the configuration to be loaded from the CPU and sends the configuration to be loaded to the FPGA through the data channel connected to the FPGA.
[0055] In this embodiment, a second MUX is also provided between the controller and the FPGA. The second MUX is connected to the CPLD, the FPGA, and the FLASH through the clock channel respectively. When the controller instructs the FPGA to obtain the configuration through the AS mode, the controller controls the FPGA to connect to the clock channel of the FLASH through the second MUX, so that the FPGA is synchronized with the FLASH clock, thereby enabling the FPGA to load the configuration from the FLASH.
[0056] When the controller instructs the FPGA to obtain the configuration through the PS mode, the controller controls the FPGA to connect to the clock channel of the controller through the second MUX, so that the FPGA is synchronized with the controller clock, thereby enabling the FPGA to load the configuration from the controller.
[0057] As can be seen from the above embodiments, the present disclosure provides a brand-new system architecture, including a multiplexer (MUX), a controller, and a hardware design for the FPGA peripheral configuration. Through this system architecture, the automatic switching function between the AP mode and the PS mode is realized, integrating the reliability of the AS and the flexibility of the PS, and realizing the adaptability and fault tolerance of the FPGA configuration system.
[0058] Based on the above method embodiments, the present disclosure also provides a chip circuit, which includes: a first multiplexer (MUX), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), and a FLASH;
[0059] The first MUX is connected to the CPLD, the FPGA, and the FLASH through the data channel respectively;
[0060] When the FPGA obtains the mode instruction sent by the CPLD, when it recognizes that the mode instruction is the first instruction, the FPGA loads the configuration from the FLASH attached below through the first MUX; or,
[0061] When it recognizes that the mode instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD through the first MUX.
[0062] As Figure 2 shown, a first MUX and a second MUX are provided between the controller (such as CPLD) and the FPGA. Among them, the first MUX is respectively connected to the CPLD, FPGA, and FLASH through data channels, and the second MUX is respectively connected to the CPLD, FPGA, and FLASH through clock channels.
[0063] When the controller instructs the FPGA to load the configuration in the AS mode (for example, MODE[0] between the controller and the FPGA represents the AS mode), the FPGA loads the configuration from the attached FLASH through the first MUX. At the same time, the controller connects the second MUX between the FPGA and the FLASH to synchronize the clocks of the FPGA and the FLASH.
[0064] For example, in one instance, in the high-reliability priority scenario, the power-on default AS mode can be selected to load the configuration from the local FLASH, without external dependencies and capable of rapid startup. When the controller monitors that the CFG_DONE signal of the FPGA has not been pulled high for a long time, it is determined that the AS mode has failed (such as FLASH damage), the RSTN signal is pulled low, and at the same time, MODE[2:0] is reconfigured to control the multiplexer MUX to switch the data and clock lines to the controller for PS loading. In addition, under normal circumstances, the local configuration file in the FLASH can also be updated through the PS interface.
[0065] It can be seen from this that the automatic switching function between the AS mode and the PS mode is realized through the technical solution in the present disclosure.
[0066] In another instance, in the flexible configuration priority scenario, the default PS mode is dynamically managed and configured by the controller, supporting multi-version or remote updates. When the PS mode fails (such as file transfer failure), it is dynamically switched to the AS mode to restore the basic functions from the local FLASH.
[0067] Based on the above method embodiments, an embodiment of the present disclosure further provides a routing device, where the routing device includes a chip circuit, and the chip circuit includes: a first multiplexer MUX, a complex programmable logic device CPLD, a field programmable gate array FPGA, and a FLASH;
[0068] The first MUX is connected to the CPLD, FPGA, and FLASH respectively through data channels;
[0069] When the FPGA obtains the mode instruction sent by the CPLD and recognizes that the mode instruction is the first instruction, the FPGA loads the configuration from the subordinate FLASH through the first MUX; or,
[0070] When recognizing that the mode instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD through the first MUX.
[0071] Wherein, the chip circuit further includes: a second MUX;
[0072] The second MUX is connected to the CPLD, FPGA, and FLASH respectively through clock channels.
[0073] Wherein, when recognizing that the mode instruction is the first instruction, the FPGA loads the configuration from the subordinate FLASH through the first MUX, including:
[0074] The CPLD issues an instruction to the first MUX to connect the FPGA and the FLASH, so that the FPGA loads the configuration from the FLASH through the first MUX;
[0075] When recognizing that the mode instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD through the first MUX, including:
[0076] The CPLD issues an instruction to the first MUX to connect the FPGA and the CPLD, so that the FPGA loads the configuration from the CPLD through the first MUX.
[0077] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution in this specification. Those of ordinary skill in the art can understand and implement it without creative work.
[0078] The foregoing describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0079] Those skilled in the art will readily conceive of other implementations of the present specification after considering the specification and practicing the invention claimed herein. The present specification is intended to cover any variations, uses, or adaptations of the present specification, which follow the general principles of the present specification and include common general knowledge or conventional technical means in the technical field not claimed in the present specification. The specification and embodiments are to be considered illustrative only, and the true scope and spirit of the present specification are pointed out by the following claims.
[0080] It should be understood that the present specification is not limited to the exact structures described above and shown in the figures, and various modifications and changes can be made without departing from its scope. The scope of the present specification is limited only by the appended claims.
[0081] The foregoing is only a preferred embodiment of the present specification and is not intended to limit the present specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present specification shall be included within the scope of protection of the present specification.
Claims
1. A method for loading and configuring a Field Programmable Gate Array (FPGA), characterized in that, The method includes: The FPGA obtains the mode instruction sent by the controller; When it is recognized that the mode instruction is the first instruction, the FPGA loads the configuration from the attached FLASH; or, When it is recognized that the mode instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD.
2. The method according to claim 1, wherein When it is recognized that the mode instruction is the first instruction, the method further includes: When the FPGA fails to load the configuration from the attached FLASH, trigger the CPLD to send the second instruction to the FPGA.
3. The method according to claim 1, wherein The FPGA loading the configuration from the attached FLASH includes: The CPLD controls the multiplexer MUX to make the data channel between the FPGA and the attached FLASH communicate.
4. The method according to claim 1, wherein When it is recognized that the mode instruction is the second instruction, the FPGA loading the configuration from the CPLD includes: The CPLD controls the multiplexer MUX to make the data channel between the CPLD and the FPGA communicate.
5. A chip circuit, characterized in that, The chip circuit includes: a first multiplexer MUX, a complex programmable logic device CPLD, a field programmable gate array FPGA, and a FLASH; The first MUX is connected to the CPLD, FPGA, and FLASH respectively through the data channel; The FPGA obtains the mode instruction sent by the CPLD. When it is recognized that the mode instruction is the first instruction, the FPGA loads the configuration from the attached FLASH through the first MUX; or, When it is recognized that the mode instruction is the second instruction, the FPGA loads the configuration from the complex programmable logic device CPLD through the first MUX.
6. The chip circuit according to claim 5, wherein The chip circuit further includes: a second MUX; The second MUX is connected to the CPLD, FPGA, and FLASH respectively through the clock channel.
7. The chip circuit according to claim 5, characterized in that, When it is recognized that the mode instruction is the first instruction, the FPGA loading the configuration from the attached FLASH through the first MUX includes: The CPLD issues an instruction to the first MUX to make the first MUX connect the FPGA and the FLASH, so that the FPGA loads the configuration from the FLASH through the first MUX; When it is recognized that the mode instruction is the second instruction, the FPGA loading the configuration from the complex programmable logic device CPLD through the first MUX includes: The CPLD issues an instruction to the first MUX to make the first MUX connect the FPGA and the CPLD, so that the FPGA loads the configuration from the CPLD through the first MUX.
8. A routing device, characterized in that, The routing device includes a chip circuit, and the chip circuit includes: a first multiplexer MUX, a complex programmable logic device CPLD, a field programmable gate array FPGA, and a FLASH; The first MUX is connected to the CPLD, FPGA, and FLASH respectively through the data channel; The FPGA obtains the mode instruction sent by the CPLD. When it is recognized that the mode instruction is the first instruction, the FPGA loads the configuration from the attached FLASH through the first MUX; or, When the pattern instruction is recognized as the second instruction, the FPGA loads the configuration from the complex programmable logic device (CPLD) through the first MUX.
9. The routing device according to claim 8, characterized in that The chip circuit further includes: a second MUX; The second MUX is respectively connected to the CPLD, the FPGA, and the FLASH through clock channels.
10. The routing device according to claim 8, characterized in that When the pattern instruction is recognized as the first instruction, the FPGA loads the configuration from the subordinate FLASH through the first MUX, including: The CPLD issues an instruction to the first MUX to connect the FPGA and the FLASH, enabling the FPGA to load the configuration from the FLASH through the first MUX; When the pattern instruction is recognized as the second instruction, the FPGA loads the configuration from the complex programmable logic device (CPLD) through the first MUX, including: The CPLD issues an instruction to the first MUX to connect the FPGA and the CPLD, enabling the FPGA to load the configuration from the CPLD through the first MUX.